1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/media/qcom,sm8550-iris.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm iris video encode and decode accelerators 8 9maintainers: 10 - Vikash Garodia <quic_vgarodia@quicinc.com> 11 - Dikshita Agarwal <quic_dikshita@quicinc.com> 12 13description: 14 The iris video processing unit is a video encode and decode accelerator 15 present on Qualcomm platforms. 16 17properties: 18 compatible: 19 oneOf: 20 - items: 21 - enum: 22 - qcom,sa8775p-iris 23 - const: qcom,sm8550-iris 24 - enum: 25 - qcom,qcs8300-iris 26 - qcom,sm8550-iris 27 - qcom,sm8650-iris 28 29 power-domains: 30 maxItems: 4 31 32 power-domain-names: 33 items: 34 - const: venus 35 - const: vcodec0 36 - const: mxc 37 - const: mmcx 38 39 clocks: 40 maxItems: 3 41 42 clock-names: 43 items: 44 - const: iface 45 - const: core 46 - const: vcodec0_core 47 48 interconnects: 49 maxItems: 2 50 51 interconnect-names: 52 items: 53 - const: cpu-cfg 54 - const: video-mem 55 56 resets: 57 minItems: 1 58 maxItems: 3 59 60 reset-names: 61 minItems: 1 62 items: 63 - const: bus 64 - const: xo 65 - const: core 66 67 iommus: 68 maxItems: 2 69 70 dma-coherent: true 71 72 operating-points-v2: true 73 74 opp-table: 75 type: object 76 77required: 78 - compatible 79 - power-domain-names 80 - interconnects 81 - interconnect-names 82 - resets 83 - reset-names 84 - iommus 85 - dma-coherent 86 87allOf: 88 - $ref: qcom,venus-common.yaml# 89 - if: 90 properties: 91 compatible: 92 enum: 93 - qcom,sm8650-iris 94 then: 95 properties: 96 resets: 97 minItems: 3 98 reset-names: 99 minItems: 3 100 else: 101 properties: 102 resets: 103 maxItems: 1 104 reset-names: 105 maxItems: 1 106 107unevaluatedProperties: false 108 109examples: 110 - | 111 #include <dt-bindings/clock/qcom,rpmh.h> 112 #include <dt-bindings/clock/qcom,sm8550-gcc.h> 113 #include <dt-bindings/clock/qcom,sm8450-videocc.h> 114 #include <dt-bindings/interrupt-controller/arm-gic.h> 115 #include <dt-bindings/interconnect/qcom,icc.h> 116 #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h> 117 #include <dt-bindings/power/qcom-rpmpd.h> 118 #include <dt-bindings/power/qcom,rpmhpd.h> 119 120 video-codec@aa00000 { 121 compatible = "qcom,sm8550-iris"; 122 reg = <0x0aa00000 0xf0000>; 123 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 124 125 power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, 126 <&videocc VIDEO_CC_MVS0_GDSC>, 127 <&rpmhpd RPMHPD_MXC>, 128 <&rpmhpd RPMHPD_MMCX>; 129 power-domain-names = "venus", "vcodec0", "mxc", "mmcx"; 130 131 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 132 <&videocc VIDEO_CC_MVS0C_CLK>, 133 <&videocc VIDEO_CC_MVS0_CLK>; 134 clock-names = "iface", "core", "vcodec0_core"; 135 136 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 137 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ALWAYS>, 138 <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS 139 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 140 interconnect-names = "cpu-cfg", "video-mem"; 141 142 memory-region = <&video_mem>; 143 144 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; 145 reset-names = "bus"; 146 147 iommus = <&apps_smmu 0x1940 0x0000>, 148 <&apps_smmu 0x1947 0x0000>; 149 dma-coherent; 150 151 operating-points-v2 = <&iris_opp_table>; 152 153 iris_opp_table: opp-table { 154 compatible = "operating-points-v2"; 155 156 opp-240000000 { 157 opp-hz = /bits/ 64 <240000000>; 158 required-opps = <&rpmhpd_opp_svs>, 159 <&rpmhpd_opp_low_svs>; 160 }; 161 162 opp-338000000 { 163 opp-hz = /bits/ 64 <338000000>; 164 required-opps = <&rpmhpd_opp_svs>, 165 <&rpmhpd_opp_svs>; 166 }; 167 168 opp-366000000 { 169 opp-hz = /bits/ 64 <366000000>; 170 required-opps = <&rpmhpd_opp_svs_l1>, 171 <&rpmhpd_opp_svs_l1>; 172 }; 173 174 opp-444000000 { 175 opp-hz = /bits/ 64 <444000000>; 176 required-opps = <&rpmhpd_opp_turbo>, 177 <&rpmhpd_opp_turbo>; 178 }; 179 180 opp-533333334 { 181 opp-hz = /bits/ 64 <533333334>; 182 required-opps = <&rpmhpd_opp_turbo_l1>, 183 <&rpmhpd_opp_turbo_l1>; 184 }; 185 }; 186 }; 187... 188