xref: /src/sys/contrib/device-tree/Bindings/media/qcom,sm8250-camss.yaml (revision 833e5d42ab135b0238e61c5b3c19b8619677cbfa) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/qcom,sm8250-camss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm CAMSS ISP
8
9maintainers:
10  - Robert Foss <robert.foss@linaro.org>
11
12description: |
13  The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
14
15properties:
16  compatible:
17    const: qcom,sm8250-camss
18
19  clocks:
20    minItems: 37
21    maxItems: 37
22
23  clock-names:
24    items:
25      - const: cam_ahb_clk
26      - const: cam_hf_axi
27      - const: cam_sf_axi
28      - const: camnoc_axi
29      - const: camnoc_axi_src
30      - const: core_ahb
31      - const: cpas_ahb
32      - const: csiphy0
33      - const: csiphy0_timer
34      - const: csiphy1
35      - const: csiphy1_timer
36      - const: csiphy2
37      - const: csiphy2_timer
38      - const: csiphy3
39      - const: csiphy3_timer
40      - const: csiphy4
41      - const: csiphy4_timer
42      - const: csiphy5
43      - const: csiphy5_timer
44      - const: slow_ahb_src
45      - const: vfe0_ahb
46      - const: vfe0_axi
47      - const: vfe0
48      - const: vfe0_cphy_rx
49      - const: vfe0_csid
50      - const: vfe0_areg
51      - const: vfe1_ahb
52      - const: vfe1_axi
53      - const: vfe1
54      - const: vfe1_cphy_rx
55      - const: vfe1_csid
56      - const: vfe1_areg
57      - const: vfe_lite_ahb
58      - const: vfe_lite_axi
59      - const: vfe_lite
60      - const: vfe_lite_cphy_rx
61      - const: vfe_lite_csid
62
63  interrupts:
64    minItems: 14
65    maxItems: 14
66
67  interrupt-names:
68    items:
69      - const: csiphy0
70      - const: csiphy1
71      - const: csiphy2
72      - const: csiphy3
73      - const: csiphy4
74      - const: csiphy5
75      - const: csid0
76      - const: csid1
77      - const: csid2
78      - const: csid3
79      - const: vfe0
80      - const: vfe1
81      - const: vfe_lite0
82      - const: vfe_lite1
83
84  iommus:
85    minItems: 8
86    maxItems: 8
87
88  interconnects:
89    minItems: 4
90    maxItems: 4
91
92  interconnect-names:
93    items:
94      - const: cam_ahb
95      - const: cam_hf_0_mnoc
96      - const: cam_sf_0_mnoc
97      - const: cam_sf_icp_mnoc
98
99  power-domains:
100    items:
101      - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
102      - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
103      - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.
104
105  ports:
106    $ref: /schemas/graph.yaml#/properties/ports
107
108    description:
109      CSI input ports.
110
111    properties:
112      port@0:
113        $ref: /schemas/graph.yaml#/$defs/port-base
114        unevaluatedProperties: false
115        description:
116          Input port for receiving CSI data.
117
118        properties:
119          endpoint:
120            $ref: video-interfaces.yaml#
121            unevaluatedProperties: false
122
123            properties:
124              clock-lanes:
125                maxItems: 1
126
127              data-lanes:
128                minItems: 1
129                maxItems: 4
130
131              bus-type:
132                enum:
133                  - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
134                  - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
135
136            required:
137              - clock-lanes
138              - data-lanes
139
140      port@1:
141        $ref: /schemas/graph.yaml#/$defs/port-base
142        unevaluatedProperties: false
143        description:
144          Input port for receiving CSI data.
145
146        properties:
147          endpoint:
148            $ref: video-interfaces.yaml#
149            unevaluatedProperties: false
150
151            properties:
152              clock-lanes:
153                maxItems: 1
154
155              data-lanes:
156                minItems: 1
157                maxItems: 4
158
159              bus-type:
160                enum:
161                  - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
162                  - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
163
164            required:
165              - clock-lanes
166              - data-lanes
167
168      port@2:
169        $ref: /schemas/graph.yaml#/$defs/port-base
170        unevaluatedProperties: false
171        description:
172          Input port for receiving CSI data.
173
174        properties:
175          endpoint:
176            $ref: video-interfaces.yaml#
177            unevaluatedProperties: false
178
179            properties:
180              clock-lanes:
181                maxItems: 1
182
183              data-lanes:
184                minItems: 1
185                maxItems: 4
186
187              bus-type:
188                enum:
189                  - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
190                  - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
191
192            required:
193              - clock-lanes
194              - data-lanes
195
196      port@3:
197        $ref: /schemas/graph.yaml#/$defs/port-base
198        unevaluatedProperties: false
199        description:
200          Input port for receiving CSI data.
201
202        properties:
203          endpoint:
204            $ref: video-interfaces.yaml#
205            unevaluatedProperties: false
206
207            properties:
208              clock-lanes:
209                maxItems: 1
210
211              data-lanes:
212                minItems: 1
213                maxItems: 4
214
215              bus-type:
216                enum:
217                  - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
218                  - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
219
220            required:
221              - clock-lanes
222              - data-lanes
223
224      port@4:
225        $ref: /schemas/graph.yaml#/$defs/port-base
226        unevaluatedProperties: false
227        description:
228          Input port for receiving CSI data.
229
230        properties:
231          endpoint:
232            $ref: video-interfaces.yaml#
233            unevaluatedProperties: false
234
235            properties:
236              clock-lanes:
237                maxItems: 1
238
239              data-lanes:
240                minItems: 1
241                maxItems: 4
242
243              bus-type:
244                enum:
245                  - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
246                  - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
247
248            required:
249              - clock-lanes
250              - data-lanes
251
252      port@5:
253        $ref: /schemas/graph.yaml#/$defs/port-base
254        unevaluatedProperties: false
255        description:
256          Input port for receiving CSI data.
257
258        properties:
259          endpoint:
260            $ref: video-interfaces.yaml#
261            unevaluatedProperties: false
262
263            properties:
264              clock-lanes:
265                maxItems: 1
266
267              data-lanes:
268                minItems: 1
269                maxItems: 4
270
271              bus-type:
272                enum:
273                  - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
274                  - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
275
276            required:
277              - clock-lanes
278              - data-lanes
279
280  reg:
281    minItems: 10
282    maxItems: 10
283
284  reg-names:
285    items:
286      - const: csiphy0
287      - const: csiphy1
288      - const: csiphy2
289      - const: csiphy3
290      - const: csiphy4
291      - const: csiphy5
292      - const: vfe0
293      - const: vfe1
294      - const: vfe_lite0
295      - const: vfe_lite1
296
297  vdda-phy-supply:
298    description:
299      Phandle to a regulator supply to PHY core block.
300
301  vdda-pll-supply:
302    description:
303      Phandle to 1.8V regulator supply to PHY refclk pll block.
304
305required:
306  - clock-names
307  - clocks
308  - compatible
309  - interconnects
310  - interconnect-names
311  - interrupts
312  - interrupt-names
313  - iommus
314  - power-domains
315  - reg
316  - reg-names
317  - vdda-phy-supply
318  - vdda-pll-supply
319
320additionalProperties: false
321
322examples:
323  - |
324    #include <dt-bindings/interrupt-controller/arm-gic.h>
325    #include <dt-bindings/clock/qcom,camcc-sm8250.h>
326    #include <dt-bindings/interconnect/qcom,sm8250.h>
327    #include <dt-bindings/clock/qcom,gcc-sm8250.h>
328    #include <dt-bindings/power/qcom-rpmpd.h>
329
330    soc {
331        #address-cells = <2>;
332        #size-cells = <2>;
333
334        camss: camss@ac6a000 {
335            compatible = "qcom,sm8250-camss";
336
337            reg = <0 0xac6a000 0 0x2000>,
338                  <0 0xac6c000 0 0x2000>,
339                  <0 0xac6e000 0 0x1000>,
340                  <0 0xac70000 0 0x1000>,
341                  <0 0xac72000 0 0x1000>,
342                  <0 0xac74000 0 0x1000>,
343                  <0 0xacb4000 0 0xd000>,
344                  <0 0xacc3000 0 0xd000>,
345                  <0 0xacd9000 0 0x2200>,
346                  <0 0xacdb200 0 0x2200>;
347            reg-names = "csiphy0",
348                        "csiphy1",
349                        "csiphy2",
350                        "csiphy3",
351                        "csiphy4",
352                        "csiphy5",
353                        "vfe0",
354                        "vfe1",
355                        "vfe_lite0",
356                        "vfe_lite1";
357
358            vdda-phy-supply = <&vreg_l5a_0p88>;
359            vdda-pll-supply = <&vreg_l9a_1p2>;
360
361            interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
362                         <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
363                         <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
364                         <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
365                         <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>,
366                         <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>,
367                         <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
368                         <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
369                         <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
370                         <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
371                         <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
372                         <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
373                         <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
374                         <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
375            interrupt-names = "csiphy0",
376                              "csiphy1",
377                              "csiphy2",
378                              "csiphy3",
379                              "csiphy4",
380                              "csiphy5",
381                              "csid0",
382                              "csid1",
383                              "csid2",
384                              "csid3",
385                              "vfe0",
386                              "vfe1",
387                              "vfe_lite0",
388                              "vfe_lite1";
389
390            power-domains = <&camcc IFE_0_GDSC>,
391                            <&camcc IFE_1_GDSC>,
392                            <&camcc TITAN_TOP_GDSC>;
393
394            clocks = <&gcc GCC_CAMERA_AHB_CLK>,
395                     <&gcc GCC_CAMERA_HF_AXI_CLK>,
396                     <&gcc GCC_CAMERA_SF_AXI_CLK>,
397                     <&camcc CAM_CC_CAMNOC_AXI_CLK>,
398                     <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
399                     <&camcc CAM_CC_CORE_AHB_CLK>,
400                     <&camcc CAM_CC_CPAS_AHB_CLK>,
401                     <&camcc CAM_CC_CSIPHY0_CLK>,
402                     <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
403                     <&camcc CAM_CC_CSIPHY1_CLK>,
404                     <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
405                     <&camcc CAM_CC_CSIPHY2_CLK>,
406                     <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
407                     <&camcc CAM_CC_CSIPHY3_CLK>,
408                     <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
409                     <&camcc CAM_CC_CSIPHY4_CLK>,
410                     <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
411                     <&camcc CAM_CC_CSIPHY5_CLK>,
412                     <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
413                     <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
414                     <&camcc CAM_CC_IFE_0_AHB_CLK>,
415                     <&camcc CAM_CC_IFE_0_AXI_CLK>,
416                     <&camcc CAM_CC_IFE_0_CLK>,
417                     <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
418                     <&camcc CAM_CC_IFE_0_CSID_CLK>,
419                     <&camcc CAM_CC_IFE_0_AREG_CLK>,
420                     <&camcc CAM_CC_IFE_1_AHB_CLK>,
421                     <&camcc CAM_CC_IFE_1_AXI_CLK>,
422                     <&camcc CAM_CC_IFE_1_CLK>,
423                     <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
424                     <&camcc CAM_CC_IFE_1_CSID_CLK>,
425                     <&camcc CAM_CC_IFE_1_AREG_CLK>,
426                     <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
427                     <&camcc CAM_CC_IFE_LITE_AXI_CLK>,
428                     <&camcc CAM_CC_IFE_LITE_CLK>,
429                     <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
430                     <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
431            clock-names = "cam_ahb_clk",
432                          "cam_hf_axi",
433                          "cam_sf_axi",
434                          "camnoc_axi",
435                          "camnoc_axi_src",
436                          "core_ahb",
437                          "cpas_ahb",
438                          "csiphy0",
439                          "csiphy0_timer",
440                          "csiphy1",
441                          "csiphy1_timer",
442                          "csiphy2",
443                          "csiphy2_timer",
444                          "csiphy3",
445                          "csiphy3_timer",
446                          "csiphy4",
447                          "csiphy4_timer",
448                          "csiphy5",
449                          "csiphy5_timer",
450                          "slow_ahb_src",
451                          "vfe0_ahb",
452                          "vfe0_axi",
453                          "vfe0",
454                          "vfe0_cphy_rx",
455                          "vfe0_csid",
456                          "vfe0_areg",
457                          "vfe1_ahb",
458                          "vfe1_axi",
459                          "vfe1",
460                          "vfe1_cphy_rx",
461                          "vfe1_csid",
462                          "vfe1_areg",
463                          "vfe_lite_ahb",
464                          "vfe_lite_axi",
465                          "vfe_lite",
466                          "vfe_lite_cphy_rx",
467                          "vfe_lite_csid";
468
469            iommus = <&apps_smmu 0x800 0x400>,
470                     <&apps_smmu 0x801 0x400>,
471                     <&apps_smmu 0x840 0x400>,
472                     <&apps_smmu 0x841 0x400>,
473                     <&apps_smmu 0xC00 0x400>,
474                     <&apps_smmu 0xC01 0x400>,
475                     <&apps_smmu 0xC40 0x400>,
476                     <&apps_smmu 0xC41 0x400>;
477
478            interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_CAMERA_CFG>,
479                            <&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI_CH0>,
480                            <&mmss_noc MASTER_CAMNOC_SF &mc_virt SLAVE_EBI_CH0>,
481                            <&mmss_noc MASTER_CAMNOC_ICP &mc_virt SLAVE_EBI_CH0>;
482            interconnect-names = "cam_ahb",
483                                 "cam_hf_0_mnoc",
484                                 "cam_sf_0_mnoc",
485                                 "cam_sf_icp_mnoc";
486
487            ports {
488                #address-cells = <1>;
489                #size-cells = <0>;
490            };
491        };
492    };
493