1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/media/qcom,sc8280xp-camss.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm SC8280XP Camera Subsystem (CAMSS) 8 9maintainers: 10 - Bryan O'Donoghue <bryan.odonoghue@linaro.org> 11 12description: | 13 The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. 14 15properties: 16 compatible: 17 const: qcom,sc8280xp-camss 18 19 clocks: 20 maxItems: 40 21 22 clock-names: 23 items: 24 - const: camnoc_axi 25 - const: cpas_ahb 26 - const: csiphy0 27 - const: csiphy0_timer 28 - const: csiphy1 29 - const: csiphy1_timer 30 - const: csiphy2 31 - const: csiphy2_timer 32 - const: csiphy3 33 - const: csiphy3_timer 34 - const: vfe0_axi 35 - const: vfe0 36 - const: vfe0_cphy_rx 37 - const: vfe0_csid 38 - const: vfe1_axi 39 - const: vfe1 40 - const: vfe1_cphy_rx 41 - const: vfe1_csid 42 - const: vfe2_axi 43 - const: vfe2 44 - const: vfe2_cphy_rx 45 - const: vfe2_csid 46 - const: vfe3_axi 47 - const: vfe3 48 - const: vfe3_cphy_rx 49 - const: vfe3_csid 50 - const: vfe_lite0 51 - const: vfe_lite0_cphy_rx 52 - const: vfe_lite0_csid 53 - const: vfe_lite1 54 - const: vfe_lite1_cphy_rx 55 - const: vfe_lite1_csid 56 - const: vfe_lite2 57 - const: vfe_lite2_cphy_rx 58 - const: vfe_lite2_csid 59 - const: vfe_lite3 60 - const: vfe_lite3_cphy_rx 61 - const: vfe_lite3_csid 62 - const: gcc_axi_hf 63 - const: gcc_axi_sf 64 65 interrupts: 66 maxItems: 20 67 68 interrupt-names: 69 items: 70 - const: csid1_lite 71 - const: vfe_lite1 72 - const: csiphy3 73 - const: csid0 74 - const: vfe0 75 - const: csid1 76 - const: vfe1 77 - const: csid0_lite 78 - const: vfe_lite0 79 - const: csiphy0 80 - const: csiphy1 81 - const: csiphy2 82 - const: csid2 83 - const: vfe2 84 - const: csid3_lite 85 - const: csid2_lite 86 - const: vfe_lite3 87 - const: vfe_lite2 88 - const: csid3 89 - const: vfe3 90 91 iommus: 92 maxItems: 16 93 94 interconnects: 95 maxItems: 4 96 97 interconnect-names: 98 items: 99 - const: cam_ahb 100 - const: cam_hf_mnoc 101 - const: cam_sf_mnoc 102 - const: cam_sf_icp_mnoc 103 104 power-domains: 105 items: 106 - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. 107 - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. 108 - description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller. 109 - description: IFE3 GDSC - Image Front End, Global Distributed Switch Controller. 110 - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller. 111 112 power-domain-names: 113 items: 114 - const: ife0 115 - const: ife1 116 - const: ife2 117 - const: ife3 118 - const: top 119 120 ports: 121 $ref: /schemas/graph.yaml#/properties/ports 122 123 description: 124 CSI input ports. 125 126 properties: 127 port@0: 128 $ref: /schemas/graph.yaml#/$defs/port-base 129 unevaluatedProperties: false 130 description: 131 Input port for receiving CSI data from CSIPHY0. 132 133 properties: 134 endpoint: 135 $ref: video-interfaces.yaml# 136 unevaluatedProperties: false 137 138 properties: 139 clock-lanes: 140 maxItems: 1 141 142 data-lanes: 143 minItems: 1 144 maxItems: 4 145 146 bus-type: 147 enum: 148 - 1 # MEDIA_BUS_TYPE_CSI2_CPHY 149 - 4 # MEDIA_BUS_TYPE_CSI2_DPHY 150 151 required: 152 - clock-lanes 153 - data-lanes 154 155 port@1: 156 $ref: /schemas/graph.yaml#/$defs/port-base 157 unevaluatedProperties: false 158 description: 159 Input port for receiving CSI data from CSIPHY1. 160 161 properties: 162 endpoint: 163 $ref: video-interfaces.yaml# 164 unevaluatedProperties: false 165 166 properties: 167 clock-lanes: 168 maxItems: 1 169 170 data-lanes: 171 minItems: 1 172 maxItems: 4 173 174 bus-type: 175 enum: 176 - 1 # MEDIA_BUS_TYPE_CSI2_CPHY 177 - 4 # MEDIA_BUS_TYPE_CSI2_DPHY 178 179 required: 180 - clock-lanes 181 - data-lanes 182 183 port@2: 184 $ref: /schemas/graph.yaml#/$defs/port-base 185 unevaluatedProperties: false 186 description: 187 Input port for receiving CSI data from CSIPHY2. 188 189 properties: 190 endpoint: 191 $ref: video-interfaces.yaml# 192 unevaluatedProperties: false 193 194 properties: 195 clock-lanes: 196 maxItems: 1 197 198 data-lanes: 199 minItems: 1 200 maxItems: 4 201 202 bus-type: 203 enum: 204 - 1 # MEDIA_BUS_TYPE_CSI2_CPHY 205 - 4 # MEDIA_BUS_TYPE_CSI2_DPHY 206 207 required: 208 - clock-lanes 209 - data-lanes 210 211 port@3: 212 $ref: /schemas/graph.yaml#/$defs/port-base 213 unevaluatedProperties: false 214 description: 215 Input port for receiving CSI data from CSIPHY3. 216 217 properties: 218 endpoint: 219 $ref: video-interfaces.yaml# 220 unevaluatedProperties: false 221 222 properties: 223 clock-lanes: 224 maxItems: 1 225 226 data-lanes: 227 minItems: 1 228 maxItems: 4 229 230 bus-type: 231 enum: 232 - 1 # MEDIA_BUS_TYPE_CSI2_CPHY 233 - 4 # MEDIA_BUS_TYPE_CSI2_DPHY 234 235 required: 236 - clock-lanes 237 - data-lanes 238 239 reg: 240 maxItems: 20 241 242 reg-names: 243 items: 244 - const: csiphy2 245 - const: csiphy3 246 - const: csiphy0 247 - const: csiphy1 248 - const: vfe0 249 - const: csid0 250 - const: vfe1 251 - const: csid1 252 - const: vfe2 253 - const: csid2 254 - const: vfe_lite0 255 - const: csid0_lite 256 - const: vfe_lite1 257 - const: csid1_lite 258 - const: vfe_lite2 259 - const: csid2_lite 260 - const: vfe_lite3 261 - const: csid3_lite 262 - const: vfe3 263 - const: csid3 264 265 vdda-phy-supply: 266 description: 267 Phandle to a regulator supply to PHY core block. 268 269 vdda-pll-supply: 270 description: 271 Phandle to 1.8V regulator supply to PHY refclk pll block. 272 273required: 274 - clock-names 275 - clocks 276 - compatible 277 - interconnects 278 - interconnect-names 279 - interrupts 280 - interrupt-names 281 - iommus 282 - power-domains 283 - power-domain-names 284 - reg 285 - reg-names 286 - vdda-phy-supply 287 - vdda-pll-supply 288 289additionalProperties: false 290 291examples: 292 - | 293 #include <dt-bindings/interrupt-controller/arm-gic.h> 294 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> 295 #include <dt-bindings/clock/qcom,sc8280xp-camcc.h> 296 #include <dt-bindings/interconnect/qcom,sc8280xp.h> 297 #include <dt-bindings/power/qcom-rpmpd.h> 298 299 soc { 300 #address-cells = <2>; 301 #size-cells = <2>; 302 303 camss: camss@ac5a000 { 304 compatible = "qcom,sc8280xp-camss"; 305 306 reg = <0 0x0ac5a000 0 0x2000>, 307 <0 0x0ac5c000 0 0x2000>, 308 <0 0x0ac65000 0 0x2000>, 309 <0 0x0ac67000 0 0x2000>, 310 <0 0x0acaf000 0 0x4000>, 311 <0 0x0acb3000 0 0x1000>, 312 <0 0x0acb6000 0 0x4000>, 313 <0 0x0acba000 0 0x1000>, 314 <0 0x0acbd000 0 0x4000>, 315 <0 0x0acc1000 0 0x1000>, 316 <0 0x0acc4000 0 0x4000>, 317 <0 0x0acc8000 0 0x1000>, 318 <0 0x0accb000 0 0x4000>, 319 <0 0x0accf000 0 0x1000>, 320 <0 0x0acd2000 0 0x4000>, 321 <0 0x0acd6000 0 0x1000>, 322 <0 0x0acd9000 0 0x4000>, 323 <0 0x0acdd000 0 0x1000>, 324 <0 0x0ace0000 0 0x4000>, 325 <0 0x0ace4000 0 0x1000>; 326 327 reg-names = "csiphy2", 328 "csiphy3", 329 "csiphy0", 330 "csiphy1", 331 "vfe0", 332 "csid0", 333 "vfe1", 334 "csid1", 335 "vfe2", 336 "csid2", 337 "vfe_lite0", 338 "csid0_lite", 339 "vfe_lite1", 340 "csid1_lite", 341 "vfe_lite2", 342 "csid2_lite", 343 "vfe_lite3", 344 "csid3_lite", 345 "vfe3", 346 "csid3"; 347 348 vdda-phy-supply = <&vreg_l6d>; 349 vdda-pll-supply = <&vreg_l4d>; 350 351 interrupts = <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, 352 <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>, 353 <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 354 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, 355 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, 356 <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, 357 <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, 358 <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, 359 <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, 360 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, 361 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, 362 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, 363 <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>, 364 <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>, 365 <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>, 366 <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>, 367 <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>, 368 <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>, 369 <GIC_SPI 762 IRQ_TYPE_EDGE_RISING>, 370 <GIC_SPI 764 IRQ_TYPE_EDGE_RISING>; 371 372 interrupt-names = "csid1_lite", 373 "vfe_lite1", 374 "csiphy3", 375 "csid0", 376 "vfe0", 377 "csid1", 378 "vfe1", 379 "csid0_lite", 380 "vfe_lite0", 381 "csiphy0", 382 "csiphy1", 383 "csiphy2", 384 "csid2", 385 "vfe2", 386 "csid3_lite", 387 "csid2_lite", 388 "vfe_lite3", 389 "vfe_lite2", 390 "csid3", 391 "vfe3"; 392 393 power-domains = <&camcc IFE_0_GDSC>, 394 <&camcc IFE_1_GDSC>, 395 <&camcc IFE_2_GDSC>, 396 <&camcc IFE_3_GDSC>, 397 <&camcc TITAN_TOP_GDSC>; 398 399 power-domain-names = "ife0", 400 "ife1", 401 "ife2", 402 "ife3", 403 "top"; 404 405 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 406 <&camcc CAMCC_CPAS_AHB_CLK>, 407 <&camcc CAMCC_CSIPHY0_CLK>, 408 <&camcc CAMCC_CSI0PHYTIMER_CLK>, 409 <&camcc CAMCC_CSIPHY1_CLK>, 410 <&camcc CAMCC_CSI1PHYTIMER_CLK>, 411 <&camcc CAMCC_CSIPHY2_CLK>, 412 <&camcc CAMCC_CSI2PHYTIMER_CLK>, 413 <&camcc CAMCC_CSIPHY3_CLK>, 414 <&camcc CAMCC_CSI3PHYTIMER_CLK>, 415 <&camcc CAMCC_IFE_0_AXI_CLK>, 416 <&camcc CAMCC_IFE_0_CLK>, 417 <&camcc CAMCC_IFE_0_CPHY_RX_CLK>, 418 <&camcc CAMCC_IFE_0_CSID_CLK>, 419 <&camcc CAMCC_IFE_1_AXI_CLK>, 420 <&camcc CAMCC_IFE_1_CLK>, 421 <&camcc CAMCC_IFE_1_CPHY_RX_CLK>, 422 <&camcc CAMCC_IFE_1_CSID_CLK>, 423 <&camcc CAMCC_IFE_2_AXI_CLK>, 424 <&camcc CAMCC_IFE_2_CLK>, 425 <&camcc CAMCC_IFE_2_CPHY_RX_CLK>, 426 <&camcc CAMCC_IFE_2_CSID_CLK>, 427 <&camcc CAMCC_IFE_3_AXI_CLK>, 428 <&camcc CAMCC_IFE_3_CLK>, 429 <&camcc CAMCC_IFE_3_CPHY_RX_CLK>, 430 <&camcc CAMCC_IFE_3_CSID_CLK>, 431 <&camcc CAMCC_IFE_LITE_0_CLK>, 432 <&camcc CAMCC_IFE_LITE_0_CPHY_RX_CLK>, 433 <&camcc CAMCC_IFE_LITE_0_CSID_CLK>, 434 <&camcc CAMCC_IFE_LITE_1_CLK>, 435 <&camcc CAMCC_IFE_LITE_1_CPHY_RX_CLK>, 436 <&camcc CAMCC_IFE_LITE_1_CSID_CLK>, 437 <&camcc CAMCC_IFE_LITE_2_CLK>, 438 <&camcc CAMCC_IFE_LITE_2_CPHY_RX_CLK>, 439 <&camcc CAMCC_IFE_LITE_2_CSID_CLK>, 440 <&camcc CAMCC_IFE_LITE_3_CLK>, 441 <&camcc CAMCC_IFE_LITE_3_CPHY_RX_CLK>, 442 <&camcc CAMCC_IFE_LITE_3_CSID_CLK>, 443 <&gcc GCC_CAMERA_HF_AXI_CLK>, 444 <&gcc GCC_CAMERA_SF_AXI_CLK>; 445 446 clock-names = "camnoc_axi", 447 "cpas_ahb", 448 "csiphy0", 449 "csiphy0_timer", 450 "csiphy1", 451 "csiphy1_timer", 452 "csiphy2", 453 "csiphy2_timer", 454 "csiphy3", 455 "csiphy3_timer", 456 "vfe0_axi", 457 "vfe0", 458 "vfe0_cphy_rx", 459 "vfe0_csid", 460 "vfe1_axi", 461 "vfe1", 462 "vfe1_cphy_rx", 463 "vfe1_csid", 464 "vfe2_axi", 465 "vfe2", 466 "vfe2_cphy_rx", 467 "vfe2_csid", 468 "vfe3_axi", 469 "vfe3", 470 "vfe3_cphy_rx", 471 "vfe3_csid", 472 "vfe_lite0", 473 "vfe_lite0_cphy_rx", 474 "vfe_lite0_csid", 475 "vfe_lite1", 476 "vfe_lite1_cphy_rx", 477 "vfe_lite1_csid", 478 "vfe_lite2", 479 "vfe_lite2_cphy_rx", 480 "vfe_lite2_csid", 481 "vfe_lite3", 482 "vfe_lite3_cphy_rx", 483 "vfe_lite3_csid", 484 "gcc_axi_hf", 485 "gcc_axi_sf"; 486 487 488 iommus = <&apps_smmu 0x2000 0x4e0>, 489 <&apps_smmu 0x2020 0x4e0>, 490 <&apps_smmu 0x2040 0x4e0>, 491 <&apps_smmu 0x2060 0x4e0>, 492 <&apps_smmu 0x2080 0x4e0>, 493 <&apps_smmu 0x20e0 0x4e0>, 494 <&apps_smmu 0x20c0 0x4e0>, 495 <&apps_smmu 0x20a0 0x4e0>, 496 <&apps_smmu 0x2400 0x4e0>, 497 <&apps_smmu 0x2420 0x4e0>, 498 <&apps_smmu 0x2440 0x4e0>, 499 <&apps_smmu 0x2460 0x4e0>, 500 <&apps_smmu 0x2480 0x4e0>, 501 <&apps_smmu 0x24e0 0x4e0>, 502 <&apps_smmu 0x24c0 0x4e0>, 503 <&apps_smmu 0x24a0 0x4e0>; 504 505 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>, 506 <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>, 507 <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>, 508 <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>; 509 interconnect-names = "cam_ahb", 510 "cam_hf_mnoc", 511 "cam_sf_mnoc", 512 "cam_sf_icp_mnoc"; 513 514 ports { 515 #address-cells = <1>; 516 #size-cells = <0>; 517 518 port@0 { 519 reg = <0>; 520 #address-cells = <1>; 521 #size-cells = <0>; 522 523 csiphy_ep0: endpoint@0 { 524 reg = <0>; 525 clock-lanes = <7>; 526 data-lanes = <0 1>; 527 remote-endpoint = <&sensor_ep>; 528 }; 529 }; 530 }; 531 }; 532 }; 533