xref: /src/sys/contrib/device-tree/Bindings/media/mediatek,mdp3-wrot.yaml (revision b4c3e9b5b09c829b4135aff738bd2893ed052377) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/mediatek,mdp3-wrot.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek Write DMA with Rotation
8
9maintainers:
10  - Matthias Brugger <matthias.bgg@gmail.com>
11  - Moudy Ho <moudy.ho@mediatek.com>
12
13description: |
14  One of Media Data Path 3 (MDP3) components used to write DMA with frame rotation.
15
16properties:
17  compatible:
18    oneOf:
19      - enum:
20          - mediatek,mt8183-mdp3-wrot
21      - items:
22          - enum:
23              - mediatek,mt8188-mdp3-wrot
24              - mediatek,mt8195-mdp3-wrot
25          - const: mediatek,mt8183-mdp3-wrot
26
27  reg:
28    maxItems: 1
29
30  mediatek,gce-client-reg:
31    $ref: /schemas/types.yaml#/definitions/phandle-array
32    items:
33      items:
34        - description: phandle of GCE
35        - description: GCE subsys id
36        - description: register offset
37        - description: register size
38    description: The register of client driver can be configured by gce with
39      4 arguments defined in this property. Each GCE subsys id is mapping to
40      a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
41
42  mediatek,gce-events:
43    description:
44      The event id which is mapping to the specific hardware event signal
45      to gce. The event id is defined in the gce header
46      include/dt-bindings/gce/<chip>-gce.h of each chips.
47    $ref: /schemas/types.yaml#/definitions/uint32-array
48
49  power-domains:
50    maxItems: 1
51
52  clocks:
53    minItems: 1
54
55  iommus:
56    maxItems: 1
57
58  '#dma-cells':
59    const: 1
60
61required:
62  - compatible
63  - reg
64  - mediatek,gce-client-reg
65  - mediatek,gce-events
66  - power-domains
67  - clocks
68  - iommus
69  - '#dma-cells'
70
71additionalProperties: false
72
73examples:
74  - |
75    #include <dt-bindings/clock/mt8183-clk.h>
76    #include <dt-bindings/gce/mt8183-gce.h>
77    #include <dt-bindings/power/mt8183-power.h>
78    #include <dt-bindings/memory/mt8183-larb-port.h>
79
80    dma-controller@14005000 {
81        compatible = "mediatek,mt8183-mdp3-wrot";
82        reg = <0x14005000 0x1000>;
83        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
84        mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>,
85                              <CMDQ_EVENT_MDP_WROT0_EOF>;
86        power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
87        clocks = <&mmsys CLK_MM_MDP_WROT0>;
88        iommus = <&iommu>;
89        #dma-cells = <1>;
90    };
91