1235ad806SAndrew TurnerBroadcom BCM7038-style Level 1 interrupt controller 2235ad806SAndrew Turner 3235ad806SAndrew TurnerThis block is a first level interrupt controller that is typically connected 4235ad806SAndrew Turnerdirectly to one of the HW INT lines on each CPU. Every BCM7xxx set-top chip 5235ad806SAndrew Turnersince BCM7038 has contained this hardware. 6235ad806SAndrew Turner 7235ad806SAndrew TurnerKey elements of the hardware design include: 8235ad806SAndrew Turner 9235ad806SAndrew Turner- 64, 96, 128, or 160 incoming level IRQ lines 10235ad806SAndrew Turner 11235ad806SAndrew Turner- Most onchip peripherals are wired directly to an L1 input 12235ad806SAndrew Turner 13235ad806SAndrew Turner- A separate instance of the register set for each CPU, allowing individual 14235ad806SAndrew Turner peripheral IRQs to be routed to any CPU 15235ad806SAndrew Turner 16235ad806SAndrew Turner- Atomic mask/unmask operations 17235ad806SAndrew Turner 18235ad806SAndrew Turner- No polarity/level/edge settings 19235ad806SAndrew Turner 20235ad806SAndrew Turner- No FIFO or priority encoder logic; software is expected to read all 21235ad806SAndrew Turner 2-5 status words to determine which IRQs are pending 22235ad806SAndrew Turner 23235ad806SAndrew TurnerRequired properties: 24235ad806SAndrew Turner 25235ad806SAndrew Turner- compatible: should be "brcm,bcm7038-l1-intc" 26235ad806SAndrew Turner- reg: specifies the base physical address and size of the registers; 27235ad806SAndrew Turner the number of supported IRQs is inferred from the size argument 28235ad806SAndrew Turner- interrupt-controller: identifies the node as an interrupt controller 29235ad806SAndrew Turner- #interrupt-cells: specifies the number of cells needed to encode an interrupt 30235ad806SAndrew Turner source, should be 1. 31235ad806SAndrew Turner- interrupts: specifies the interrupt line(s) in the interrupt-parent controller 32235ad806SAndrew Turner node; valid values depend on the type of parent interrupt controller 33235ad806SAndrew Turner 34995ee34fSEmmanuel VadotOptional properties: 35995ee34fSEmmanuel Vadot 36995ee34fSEmmanuel Vadot- brcm,irq-can-wake: If present, this means the L1 controller can be used as a 37995ee34fSEmmanuel Vadot wakeup source for system suspend/resume. 38995ee34fSEmmanuel Vadot 39995ee34fSEmmanuel VadotOptional properties: 40995ee34fSEmmanuel Vadot 41995ee34fSEmmanuel Vadot- brcm,int-fwd-mask: if present, a bit mask to indicate which interrupts 42995ee34fSEmmanuel Vadot have already been configured by the firmware and should be left unmanaged. 43995ee34fSEmmanuel Vadot This should have one 32-bit word per status/set/clear/mask group. 44995ee34fSEmmanuel Vadot 45235ad806SAndrew TurnerIf multiple reg ranges and interrupt-parent entries are present on an SMP 46235ad806SAndrew Turnersystem, the driver will allow IRQ SMP affinity to be set up through the 47235ad806SAndrew Turner/proc/irq/ interface. In the simplest possible configuration, only one 48235ad806SAndrew Turnerreg range and one interrupt-parent is needed. 49235ad806SAndrew Turner 50235ad806SAndrew TurnerExample: 51235ad806SAndrew Turner 52235ad806SAndrew Turnerperiph_intc: periph_intc@1041a400 { 53235ad806SAndrew Turner compatible = "brcm,bcm7038-l1-intc"; 54235ad806SAndrew Turner reg = <0x1041a400 0x30 0x1041a600 0x30>; 55235ad806SAndrew Turner 56235ad806SAndrew Turner interrupt-controller; 57235ad806SAndrew Turner #interrupt-cells = <1>; 58235ad806SAndrew Turner 59235ad806SAndrew Turner interrupt-parent = <&cpu_intc>; 60235ad806SAndrew Turner interrupts = <2>, <3>; 61235ad806SAndrew Turner}; 62