xref: /src/sys/contrib/device-tree/Bindings/dma/owl-dma.txt (revision c66ec88fed842fbaad62c30d510644ceb7bd2d71)
10bf7de31SEmmanuel Vadot* Actions Semi Owl SoCs DMA controller
20bf7de31SEmmanuel Vadot
30bf7de31SEmmanuel VadotThis binding follows the generic DMA bindings defined in dma.txt.
40bf7de31SEmmanuel Vadot
50bf7de31SEmmanuel VadotRequired properties:
60bf7de31SEmmanuel Vadot- compatible: Should be "actions,s900-dma".
70bf7de31SEmmanuel Vadot- reg: Should contain DMA registers location and length.
80bf7de31SEmmanuel Vadot- interrupts: Should contain 4 interrupts shared by all channel.
90bf7de31SEmmanuel Vadot- #dma-cells: Must be <1>. Used to represent the number of integer
100bf7de31SEmmanuel Vadot              cells in the dmas property of client device.
110bf7de31SEmmanuel Vadot- dma-channels: Physical channels supported.
120bf7de31SEmmanuel Vadot- dma-requests: Number of DMA request signals supported by the controller.
130bf7de31SEmmanuel Vadot                Refer to Documentation/devicetree/bindings/dma/dma.txt
140bf7de31SEmmanuel Vadot- clocks: Phandle and Specifier of the clock feeding the DMA controller.
150bf7de31SEmmanuel Vadot
160bf7de31SEmmanuel VadotExample:
170bf7de31SEmmanuel Vadot
180bf7de31SEmmanuel VadotController:
190bf7de31SEmmanuel Vadot                dma: dma-controller@e0260000 {
200bf7de31SEmmanuel Vadot                        compatible = "actions,s900-dma";
210bf7de31SEmmanuel Vadot                        reg = <0x0 0xe0260000 0x0 0x1000>;
220bf7de31SEmmanuel Vadot                        interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
230bf7de31SEmmanuel Vadot                                     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
240bf7de31SEmmanuel Vadot                                     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
250bf7de31SEmmanuel Vadot                                     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
260bf7de31SEmmanuel Vadot                        #dma-cells = <1>;
270bf7de31SEmmanuel Vadot                        dma-channels = <12>;
280bf7de31SEmmanuel Vadot                        dma-requests = <46>;
290bf7de31SEmmanuel Vadot                        clocks = <&clock CLK_DMAC>;
300bf7de31SEmmanuel Vadot                };
310bf7de31SEmmanuel Vadot
320bf7de31SEmmanuel VadotClient:
330bf7de31SEmmanuel Vadot
340bf7de31SEmmanuel VadotDMA clients connected to the Actions Semi Owl SoCs DMA controller must
350bf7de31SEmmanuel Vadotuse the format described in the dma.txt file, using a two-cell specifier
360bf7de31SEmmanuel Vadotfor each channel.
370bf7de31SEmmanuel Vadot
380bf7de31SEmmanuel VadotThe two cells in order are:
390bf7de31SEmmanuel Vadot1. A phandle pointing to the DMA controller.
400bf7de31SEmmanuel Vadot2. The channel id.
410bf7de31SEmmanuel Vadot
420bf7de31SEmmanuel Vadotuart5: serial@e012a000 {
430bf7de31SEmmanuel Vadot        ...
440bf7de31SEmmanuel Vadot        dma-names = "tx", "rx";
450bf7de31SEmmanuel Vadot        dmas = <&dma 26>, <&dma 27>;
460bf7de31SEmmanuel Vadot        ...
470bf7de31SEmmanuel Vadot};
48