1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/rockchip/rockchip,rk3399-cdn-dp.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Rockchip RK3399 specific extensions to the CDN Display Port 8 9maintainers: 10 - Andy Yan <andy.yan@rock-chip.com> 11 - Heiko Stuebner <heiko@sntech.de> 12 - Sandy Huang <hjc@rock-chips.com> 13 14allOf: 15 - $ref: /schemas/sound/dai-common.yaml# 16 17properties: 18 compatible: 19 items: 20 - const: rockchip,rk3399-cdn-dp 21 22 reg: 23 maxItems: 1 24 25 clocks: 26 items: 27 - description: DP core work clock 28 - description: APB clock 29 - description: SPDIF interface clock 30 - description: GRF clock 31 32 clock-names: 33 items: 34 - const: core-clk 35 - const: pclk 36 - const: spdif 37 - const: grf 38 39 extcon: 40 $ref: /schemas/types.yaml#/definitions/phandle-array 41 minItems: 1 42 items: 43 - description: Extcon device providing the cable state for DP PHY device 0 44 - description: Extcon device providing the cable state for DP PHY device 1 45 description: 46 List of phandle to the extcon device providing the cable state for the DP PHY. 47 48 interrupts: 49 maxItems: 1 50 51 phys: 52 minItems: 1 53 items: 54 - description: DP output to the DP PHY device 0 55 - description: DP output to the DP PHY device 1 56 description: 57 RK3399 have two DP-USB PHY, specifying one PHY which want to use, or 58 specify two PHYs here to let the driver determine which PHY to use. 59 60 ports: 61 $ref: /schemas/graph.yaml#/properties/ports 62 63 properties: 64 port@0: 65 $ref: /schemas/graph.yaml#/properties/port 66 description: Input of the CDN DP 67 68 properties: 69 endpoint@0: 70 description: Connection to the VOPB 71 72 endpoint@1: 73 description: Connection to the VOPL 74 75 port@1: 76 $ref: /schemas/graph.yaml#/properties/port 77 description: Output of the CDN DP 78 79 required: 80 - port@0 81 - port@1 82 83 power-domains: 84 maxItems: 1 85 86 resets: 87 maxItems: 4 88 89 reset-names: 90 items: 91 - const: spdif 92 - const: dptx 93 - const: apb 94 - const: core 95 96 rockchip,grf: 97 $ref: /schemas/types.yaml#/definitions/phandle 98 description: 99 Phandle to GRF register to control HPD. 100 101 "#sound-dai-cells": 102 const: 1 103 104required: 105 - compatible 106 - reg 107 - clocks 108 - clock-names 109 - interrupts 110 - phys 111 - ports 112 - resets 113 - reset-names 114 - rockchip,grf 115 - "#sound-dai-cells" 116 117unevaluatedProperties: false 118 119examples: 120 - | 121 #include <dt-bindings/clock/rk3399-cru.h> 122 #include <dt-bindings/interrupt-controller/arm-gic.h> 123 #include <dt-bindings/power/rk3399-power.h> 124 soc { 125 #address-cells = <2>; 126 #size-cells = <2>; 127 128 dp@fec00000 { 129 compatible = "rockchip,rk3399-cdn-dp"; 130 reg = <0x0 0xfec00000 0x0 0x100000>; 131 assigned-clocks = <&cru SCLK_DP_CORE>; 132 assigned-clock-rates = <100000000>; 133 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 134 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, <&cru SCLK_SPDIF_REC_DPTX>, 135 <&cru PCLK_VIO_GRF>; 136 clock-names = "core-clk", "pclk", "spdif", "grf"; 137 power-domains = <&power RK3399_PD_HDCP>; 138 phys = <&tcphy0_dp>, <&tcphy1_dp>; 139 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, 140 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>; 141 reset-names = "spdif", "dptx", "apb", "core"; 142 rockchip,grf = <&grf>; 143 #sound-dai-cells = <1>; 144 145 ports { 146 #address-cells = <1>; 147 #size-cells = <0>; 148 149 dp_in: port@0 { 150 reg = <0>; 151 #address-cells = <1>; 152 #size-cells = <0>; 153 154 dp_in_vopb: endpoint@0 { 155 reg = <0>; 156 remote-endpoint = <&vopb_out_dp>; 157 }; 158 159 dp_in_vopl: endpoint@1 { 160 reg = <1>; 161 remote-endpoint = <&vopl_out_dp>; 162 }; 163 }; 164 165 dp_out: port@1 { 166 reg = <1>; 167 }; 168 }; 169 }; 170 }; 171