1da75c2ccSWarner LoshGeneric cpufreq driver 2da75c2ccSWarner Losh 3da75c2ccSWarner LoshIt is a generic DT based cpufreq driver for frequency management. It supports 4da75c2ccSWarner Loshboth uniprocessor (UP) and symmetric multiprocessor (SMP) systems which share 5da75c2ccSWarner Loshclock and voltage across all CPUs. 6da75c2ccSWarner Losh 7da75c2ccSWarner LoshBoth required and optional properties listed below must be defined 8da75c2ccSWarner Loshunder node /cpus/cpu@0. 9da75c2ccSWarner Losh 10da75c2ccSWarner LoshRequired properties: 11da75c2ccSWarner Losh- None 12da75c2ccSWarner Losh 13da75c2ccSWarner LoshOptional properties: 141769b8f3SEmmanuel Vadot- operating-points: Refer to Documentation/devicetree/bindings/opp/opp-v1.yaml for 15da75c2ccSWarner Losh details. OPPs *must* be supplied either via DT, i.e. this property, or 16da75c2ccSWarner Losh populated at runtime. 17da75c2ccSWarner Losh- clock-latency: Specify the possible maximum transition latency for clock, 18da75c2ccSWarner Losh in unit of nanoseconds. 19da75c2ccSWarner Losh- voltage-tolerance: Specify the CPU voltage tolerance in percentage. 20da75c2ccSWarner Losh- #cooling-cells: 215ee353c3SEmmanuel Vadot Please refer to 225ee353c3SEmmanuel Vadot Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml. 23da75c2ccSWarner Losh 24da75c2ccSWarner LoshExamples: 25da75c2ccSWarner Losh 26da75c2ccSWarner Loshcpus { 27da75c2ccSWarner Losh #address-cells = <1>; 28da75c2ccSWarner Losh #size-cells = <0>; 29da75c2ccSWarner Losh 30da75c2ccSWarner Losh cpu@0 { 31da75c2ccSWarner Losh compatible = "arm,cortex-a9"; 32da75c2ccSWarner Losh reg = <0>; 33da75c2ccSWarner Losh next-level-cache = <&L2>; 34da75c2ccSWarner Losh operating-points = < 35da75c2ccSWarner Losh /* kHz uV */ 36da75c2ccSWarner Losh 792000 1100000 37da75c2ccSWarner Losh 396000 950000 38da75c2ccSWarner Losh 198000 850000 39da75c2ccSWarner Losh >; 40da75c2ccSWarner Losh clock-latency = <61036>; /* two CLK32 periods */ 41da75c2ccSWarner Losh #cooling-cells = <2>; 42da75c2ccSWarner Losh }; 43da75c2ccSWarner Losh 44da75c2ccSWarner Losh cpu@1 { 45da75c2ccSWarner Losh compatible = "arm,cortex-a9"; 46da75c2ccSWarner Losh reg = <1>; 47da75c2ccSWarner Losh next-level-cache = <&L2>; 48da75c2ccSWarner Losh }; 49da75c2ccSWarner Losh 50da75c2ccSWarner Losh cpu@2 { 51da75c2ccSWarner Losh compatible = "arm,cortex-a9"; 52da75c2ccSWarner Losh reg = <2>; 53da75c2ccSWarner Losh next-level-cache = <&L2>; 54da75c2ccSWarner Losh }; 55da75c2ccSWarner Losh 56da75c2ccSWarner Losh cpu@3 { 57da75c2ccSWarner Losh compatible = "arm,cortex-a9"; 58da75c2ccSWarner Losh reg = <3>; 59da75c2ccSWarner Losh next-level-cache = <&L2>; 60da75c2ccSWarner Losh }; 61da75c2ccSWarner Losh}; 62