1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/rockchip,rk3528-cru.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Rockchip RK3528 Clock and Reset Controller 8 9maintainers: 10 - Yao Zi <ziyao@disroot.org> 11 12description: | 13 The RK3528 clock controller generates the clock and also implements a reset 14 controller for SoC peripherals. For example, it provides SCLK_UART0 and 15 PCLK_UART0 as well as SRST_P_UART0 and SRST_S_UART0 for the first UART 16 module. 17 Each clock is assigned an identifier, consumer nodes can use it to specify 18 the clock. All available clock and reset IDs are defined in dt-binding 19 headers. 20 21properties: 22 compatible: 23 const: rockchip,rk3528-cru 24 25 reg: 26 maxItems: 1 27 28 clocks: 29 items: 30 - description: External 24MHz oscillator clock 31 - description: > 32 50MHz clock generated by PHY module, for generating GMAC0 clocks only. 33 34 clock-names: 35 items: 36 - const: xin24m 37 - const: gmac0 38 39 "#clock-cells": 40 const: 1 41 42 "#reset-cells": 43 const: 1 44 45required: 46 - compatible 47 - reg 48 - clocks 49 - clock-names 50 - "#clock-cells" 51 - "#reset-cells" 52 53additionalProperties: false 54 55examples: 56 - | 57 clock-controller@ff4a0000 { 58 compatible = "rockchip,rk3528-cru"; 59 reg = <0xff4a0000 0x30000>; 60 clocks = <&xin24m>, <&gmac0_clk>; 61 clock-names = "xin24m", "gmac0"; 62 #clock-cells = <1>; 63 #reset-cells = <1>; 64 }; 65