1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _FENV_H_ 30 #define _FENV_H_ 31 32 #include <sys/_types.h> 33 #include <machine/endian.h> 34 35 #ifndef __fenv_static 36 #define __fenv_static static 37 #endif 38 39 typedef __uint32_t fenv_t; 40 typedef __uint32_t fexcept_t; 41 42 /* Exception flags */ 43 #define FE_INEXACT 0x02000000 44 #define FE_DIVBYZERO 0x04000000 45 #define FE_UNDERFLOW 0x08000000 46 #define FE_OVERFLOW 0x10000000 47 #define FE_INVALID 0x20000000 /* all types of invalid FP ops */ 48 49 /* 50 * The PowerPC architecture has extra invalid flags that indicate the 51 * specific type of invalid operation occurred. These flags may be 52 * tested, set, and cleared---but not masked---separately. All of 53 * these bits are cleared when FE_INVALID is cleared, but only 54 * FE_VXSOFT is set when FE_INVALID is explicitly set in software. 55 */ 56 #define FE_VXCVI 0x00000100 /* invalid integer convert */ 57 #define FE_VXSQRT 0x00000200 /* square root of a negative */ 58 #define FE_VXSOFT 0x00000400 /* software-requested exception */ 59 #define FE_VXVC 0x00080000 /* ordered comparison involving NaN */ 60 #define FE_VXIMZ 0x00100000 /* inf * 0 */ 61 #define FE_VXZDZ 0x00200000 /* 0 / 0 */ 62 #define FE_VXIDI 0x00400000 /* inf / inf */ 63 #define FE_VXISI 0x00800000 /* inf - inf */ 64 #define FE_VXSNAN 0x01000000 /* operation on a signalling NaN */ 65 #define FE_ALL_INVALID (FE_VXCVI | FE_VXSQRT | FE_VXSOFT | FE_VXVC | \ 66 FE_VXIMZ | FE_VXZDZ | FE_VXIDI | FE_VXISI | \ 67 FE_VXSNAN | FE_INVALID) 68 69 #define _FPUSW_SHIFT 22 70 #define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \ 71 FE_ALL_INVALID | FE_OVERFLOW | FE_UNDERFLOW) 72 73 /* Rounding modes */ 74 #define FE_TONEAREST 0x0000 75 #define FE_TOWARDZERO 0x0001 76 #define FE_UPWARD 0x0002 77 #define FE_DOWNWARD 0x0003 78 #define _ROUND_MASK (FE_TONEAREST | FE_DOWNWARD | \ 79 FE_UPWARD | FE_TOWARDZERO) 80 81 __BEGIN_DECLS 82 83 /* Default floating-point environment */ 84 extern const fenv_t __fe_dfl_env; 85 #define FE_DFL_ENV (&__fe_dfl_env) 86 87 /* We need to be able to map status flag positions to mask flag positions */ 88 #define _ENABLE_MASK ((FE_DIVBYZERO | FE_INEXACT | FE_INVALID | \ 89 FE_OVERFLOW | FE_UNDERFLOW) >> _FPUSW_SHIFT) 90 91 #ifndef _SOFT_FLOAT 92 #define __mffs(__env) \ 93 __asm __volatile("mffs %0" : "=f" ((__env)->__d)) 94 #define __mtfsf(__env) \ 95 __asm __volatile("mtfsf 255,%0" :: "f" ((__env).__d)) 96 #else 97 #define __mffs(__env) 98 #define __mtfsf(__env) 99 #endif 100 101 union __fpscr { 102 double __d; 103 struct { 104 #if _BYTE_ORDER == _LITTLE_ENDIAN 105 fenv_t __reg; 106 __uint32_t __junk; 107 #else 108 __uint32_t __junk; 109 fenv_t __reg; 110 #endif 111 } __bits; 112 }; 113 114 __fenv_static inline int 115 feclearexcept(int __excepts) 116 { 117 union __fpscr __r; 118 119 if (__excepts & FE_INVALID) 120 __excepts |= FE_ALL_INVALID; 121 __mffs(&__r); 122 __r.__bits.__reg &= ~__excepts; 123 __mtfsf(__r); 124 return (0); 125 } 126 127 __fenv_static inline int 128 fegetexceptflag(fexcept_t *__flagp, int __excepts) 129 { 130 union __fpscr __r; 131 132 __mffs(&__r); 133 *__flagp = __r.__bits.__reg & __excepts; 134 return (0); 135 } 136 137 __fenv_static inline int 138 fesetexceptflag(const fexcept_t *__flagp, int __excepts) 139 { 140 union __fpscr __r; 141 142 if (__excepts & FE_INVALID) 143 __excepts |= FE_ALL_INVALID; 144 __mffs(&__r); 145 __r.__bits.__reg &= ~__excepts; 146 __r.__bits.__reg |= *__flagp & __excepts; 147 __mtfsf(__r); 148 return (0); 149 } 150 151 __fenv_static inline int 152 feraiseexcept(int __excepts) 153 { 154 union __fpscr __r; 155 156 if (__excepts & FE_INVALID) 157 __excepts |= FE_VXSOFT; 158 __mffs(&__r); 159 __r.__bits.__reg |= __excepts; 160 __mtfsf(__r); 161 return (0); 162 } 163 164 __fenv_static inline int 165 fetestexcept(int __excepts) 166 { 167 union __fpscr __r; 168 169 __mffs(&__r); 170 return (__r.__bits.__reg & __excepts); 171 } 172 173 __fenv_static inline int 174 fegetround(void) 175 { 176 union __fpscr __r; 177 178 __mffs(&__r); 179 return (__r.__bits.__reg & _ROUND_MASK); 180 } 181 182 __fenv_static inline int 183 fesetround(int __round) 184 { 185 union __fpscr __r; 186 187 if (__round & ~_ROUND_MASK) 188 return (-1); 189 __mffs(&__r); 190 __r.__bits.__reg &= ~_ROUND_MASK; 191 __r.__bits.__reg |= __round; 192 __mtfsf(__r); 193 return (0); 194 } 195 196 __fenv_static inline int 197 fegetenv(fenv_t *__envp) 198 { 199 union __fpscr __r; 200 201 __mffs(&__r); 202 *__envp = __r.__bits.__reg; 203 return (0); 204 } 205 206 __fenv_static inline int 207 feholdexcept(fenv_t *__envp) 208 { 209 union __fpscr __r; 210 211 __mffs(&__r); 212 *__envp = __r.__bits.__reg; 213 __r.__bits.__reg &= ~(FE_ALL_EXCEPT | _ENABLE_MASK); 214 __mtfsf(__r); 215 return (0); 216 } 217 218 __fenv_static inline int 219 fesetenv(const fenv_t *__envp) 220 { 221 union __fpscr __r; 222 223 __r.__bits.__reg = *__envp; 224 __mtfsf(__r); 225 return (0); 226 } 227 228 __fenv_static inline int 229 feupdateenv(const fenv_t *__envp) 230 { 231 union __fpscr __r; 232 233 __mffs(&__r); 234 __r.__bits.__reg &= FE_ALL_EXCEPT; 235 __r.__bits.__reg |= *__envp; 236 __mtfsf(__r); 237 return (0); 238 } 239 240 #if __BSD_VISIBLE 241 242 __fenv_static inline int 243 feenableexcept(int __mask) 244 { 245 union __fpscr __r; 246 fenv_t __oldmask; 247 248 __mffs(&__r); 249 __oldmask = __r.__bits.__reg; 250 __r.__bits.__reg |= (__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT; 251 __mtfsf(__r); 252 return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT); 253 } 254 255 __fenv_static inline int 256 fedisableexcept(int __mask) 257 { 258 union __fpscr __r; 259 fenv_t __oldmask; 260 261 __mffs(&__r); 262 __oldmask = __r.__bits.__reg; 263 __r.__bits.__reg &= ~((__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT); 264 __mtfsf(__r); 265 return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT); 266 } 267 268 /* We currently provide no external definition of fegetexcept(). */ 269 static inline int 270 fegetexcept(void) 271 { 272 union __fpscr __r; 273 274 __mffs(&__r); 275 return ((__r.__bits.__reg & _ENABLE_MASK) << _FPUSW_SHIFT); 276 } 277 278 #endif /* __BSD_VISIBLE */ 279 280 __END_DECLS 281 282 #endif /* !_FENV_H_ */ 283