1a6157d81SRuslan Bukin /*
2a6157d81SRuslan Bukin * \file trc_ret_stack.cpp
3a6157d81SRuslan Bukin * \brief OpenCSD : trace decoder return stack feature.
4a6157d81SRuslan Bukin *
5a6157d81SRuslan Bukin * \copyright Copyright (c) 2017, ARM Limited. All Rights Reserved.
6a6157d81SRuslan Bukin */
7a6157d81SRuslan Bukin
8a6157d81SRuslan Bukin /*
9a6157d81SRuslan Bukin * Redistribution and use in source and binary forms, with or without modification,
10a6157d81SRuslan Bukin * are permitted provided that the following conditions are met:
11a6157d81SRuslan Bukin *
12a6157d81SRuslan Bukin * 1. Redistributions of source code must retain the above copyright notice,
13a6157d81SRuslan Bukin * this list of conditions and the following disclaimer.
14a6157d81SRuslan Bukin *
15a6157d81SRuslan Bukin * 2. Redistributions in binary form must reproduce the above copyright notice,
16a6157d81SRuslan Bukin * this list of conditions and the following disclaimer in the documentation
17a6157d81SRuslan Bukin * and/or other materials provided with the distribution.
18a6157d81SRuslan Bukin *
19a6157d81SRuslan Bukin * 3. Neither the name of the copyright holder nor the names of its contributors
20a6157d81SRuslan Bukin * may be used to endorse or promote products derived from this software without
21a6157d81SRuslan Bukin * specific prior written permission.
22a6157d81SRuslan Bukin *
23a6157d81SRuslan Bukin * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS' AND
24a6157d81SRuslan Bukin * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25a6157d81SRuslan Bukin * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26a6157d81SRuslan Bukin * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
27a6157d81SRuslan Bukin * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28a6157d81SRuslan Bukin * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29a6157d81SRuslan Bukin * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30a6157d81SRuslan Bukin * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31a6157d81SRuslan Bukin * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32a6157d81SRuslan Bukin * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33a6157d81SRuslan Bukin */
34a6157d81SRuslan Bukin #include "common/trc_ret_stack.h"
35a6157d81SRuslan Bukin
36a6157d81SRuslan Bukin #ifdef TRC_RET_STACK_DEBUG
37a6157d81SRuslan Bukin #include <sstream>
38a6157d81SRuslan Bukin #include <iostream>
39a6157d81SRuslan Bukin #include "common/trc_component.h"
40a6157d81SRuslan Bukin
41a6157d81SRuslan Bukin #define LOG_POP(A,O,I) LogOp("Pop",A,O,I)
42a6157d81SRuslan Bukin #define LOG_PUSH(A,O,I) LogOp("Push",A,O,I)
43a6157d81SRuslan Bukin #define LOG_FLUSH() LogOp("Flush",0,-1000,(const ocsd_isa)0)
44a6157d81SRuslan Bukin
45a6157d81SRuslan Bukin // uncomment for forced std::cout log, bypassing normal library debug logger.
46a6157d81SRuslan Bukin // useful perhaps when perf is decoding w/o printing.
47a6157d81SRuslan Bukin // #define FORCE_STD_COUT
48a6157d81SRuslan Bukin
49a6157d81SRuslan Bukin #else
50a6157d81SRuslan Bukin #define LOG_POP(A,O,I)
51a6157d81SRuslan Bukin #define LOG_PUSH(A,O,I)
52a6157d81SRuslan Bukin #define LOG_FLUSH()
53a6157d81SRuslan Bukin #endif
54a6157d81SRuslan Bukin
TrcAddrReturnStack()55a6157d81SRuslan Bukin TrcAddrReturnStack::TrcAddrReturnStack() :
56a6157d81SRuslan Bukin m_active(false),
57a6157d81SRuslan Bukin m_pop_pending(false),
58a6157d81SRuslan Bukin head_idx(0),
59a6157d81SRuslan Bukin num_entries(0)
60a6157d81SRuslan Bukin {
61a6157d81SRuslan Bukin #ifdef TRC_RET_STACK_DEBUG
62a6157d81SRuslan Bukin m_p_debug_logger = 0;
63a6157d81SRuslan Bukin #endif
64a6157d81SRuslan Bukin }
65a6157d81SRuslan Bukin
push(const ocsd_vaddr_t addr,const ocsd_isa isa)66a6157d81SRuslan Bukin void TrcAddrReturnStack::push(const ocsd_vaddr_t addr, const ocsd_isa isa)
67a6157d81SRuslan Bukin {
68a6157d81SRuslan Bukin if (is_active())
69a6157d81SRuslan Bukin {
70a6157d81SRuslan Bukin head_idx++;
71a6157d81SRuslan Bukin head_idx &= 0xF;
72a6157d81SRuslan Bukin m_stack[head_idx].ret_addr = addr;
73a6157d81SRuslan Bukin m_stack[head_idx].ret_isa = isa;
74a6157d81SRuslan Bukin num_entries++;
75a6157d81SRuslan Bukin if (num_entries > 16)
76a6157d81SRuslan Bukin num_entries = 16;
77a6157d81SRuslan Bukin LOG_PUSH(addr,0,isa);
78a6157d81SRuslan Bukin m_pop_pending = false;
79a6157d81SRuslan Bukin }
80a6157d81SRuslan Bukin }
81a6157d81SRuslan Bukin
pop(ocsd_isa & isa)82a6157d81SRuslan Bukin ocsd_vaddr_t TrcAddrReturnStack::pop(ocsd_isa &isa)
83a6157d81SRuslan Bukin {
84a6157d81SRuslan Bukin ocsd_vaddr_t addr = (ocsd_vaddr_t)-1;
85a6157d81SRuslan Bukin if (is_active())
86a6157d81SRuslan Bukin {
87a6157d81SRuslan Bukin if (num_entries > 0)
88a6157d81SRuslan Bukin {
89a6157d81SRuslan Bukin addr = m_stack[head_idx].ret_addr;
90a6157d81SRuslan Bukin isa = m_stack[head_idx].ret_isa;
91a6157d81SRuslan Bukin head_idx--;
92a6157d81SRuslan Bukin head_idx &= 0xF;
93a6157d81SRuslan Bukin }
94a6157d81SRuslan Bukin num_entries--;
95a6157d81SRuslan Bukin LOG_POP(addr,1,isa);
96a6157d81SRuslan Bukin m_pop_pending = false;
97a6157d81SRuslan Bukin }
98a6157d81SRuslan Bukin return addr;
99a6157d81SRuslan Bukin }
100a6157d81SRuslan Bukin
101a6157d81SRuslan Bukin
flush()102a6157d81SRuslan Bukin void TrcAddrReturnStack::flush()
103a6157d81SRuslan Bukin {
104a6157d81SRuslan Bukin num_entries = 0;
105a6157d81SRuslan Bukin m_pop_pending = false;
106a6157d81SRuslan Bukin LOG_FLUSH();
107a6157d81SRuslan Bukin }
108a6157d81SRuslan Bukin
109a6157d81SRuslan Bukin #ifdef TRC_RET_STACK_DEBUG
LogOp(const char * pszOpString,ocsd_vaddr_t addr,int head_off,ocsd_isa isa)110a6157d81SRuslan Bukin void TrcAddrReturnStack::LogOp(const char * pszOpString, ocsd_vaddr_t addr, int head_off, ocsd_isa isa)
111a6157d81SRuslan Bukin {
112a6157d81SRuslan Bukin static const char *isa_names[] =
113a6157d81SRuslan Bukin {
114a6157d81SRuslan Bukin "A32", /**< V7 ARM 32, V8 AArch32 */
115a6157d81SRuslan Bukin "T32", /**< Thumb2 -> 16/32 bit instructions */
116a6157d81SRuslan Bukin "A64", /**< V8 AArch64 */
117a6157d81SRuslan Bukin "TEE", /**< Thumb EE - unsupported */
118a6157d81SRuslan Bukin "JZL", /**< Jazelle - unsupported in trace */
119a6157d81SRuslan Bukin "custom", /**< Instruction set - custom arch decoder */
120a6157d81SRuslan Bukin "unknown" /**< ISA not yet known */
121a6157d81SRuslan Bukin };
122a6157d81SRuslan Bukin
123a6157d81SRuslan Bukin if (m_p_debug_logger)
124a6157d81SRuslan Bukin {
125a6157d81SRuslan Bukin std::ostringstream oss;
126a6157d81SRuslan Bukin if(head_off == -1000)
127a6157d81SRuslan Bukin {
128a6157d81SRuslan Bukin oss << "Return stack " << pszOpString << "\n";
129a6157d81SRuslan Bukin }
130a6157d81SRuslan Bukin else
131a6157d81SRuslan Bukin {
132a6157d81SRuslan Bukin int name_idx = (int)isa;
133a6157d81SRuslan Bukin if (name_idx > 6)
134a6157d81SRuslan Bukin name_idx = 6;
135a6157d81SRuslan Bukin oss << "Return stack " << pszOpString << "[" << std::dec << (head_idx+head_off) << "](0x" << std::hex << addr << "), " << isa_names[name_idx] << ";";
136a6157d81SRuslan Bukin oss << "current entries = " << std::dec << num_entries << ";";
137a6157d81SRuslan Bukin oss << "new head idx = " << head_idx << ";";
138a6157d81SRuslan Bukin oss << "pop pend (pre op) = " << (m_pop_pending ? "true\n" : "false\n");
139a6157d81SRuslan Bukin }
140a6157d81SRuslan Bukin #ifdef FORCE_STD_COUT
141a6157d81SRuslan Bukin std::cout << oss.str();
142a6157d81SRuslan Bukin std::cout.flush();
143a6157d81SRuslan Bukin #endif
144a6157d81SRuslan Bukin m_p_debug_logger->LogDefMessage(oss.str());
145a6157d81SRuslan Bukin }
146a6157d81SRuslan Bukin }
147a6157d81SRuslan Bukin #endif
148a6157d81SRuslan Bukin
149a6157d81SRuslan Bukin /* End of File trc_ret_stack.cpp */
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