1 //===-- Host.cpp - Implement OS Host Detection ------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the operating system Host detection. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/TargetParser/Host.h" 14 #include "llvm/ADT/SmallVector.h" 15 #include "llvm/ADT/StringMap.h" 16 #include "llvm/ADT/StringRef.h" 17 #include "llvm/ADT/StringSwitch.h" 18 #include "llvm/Config/llvm-config.h" 19 #include "llvm/Support/MemoryBuffer.h" 20 #include "llvm/Support/raw_ostream.h" 21 #include "llvm/TargetParser/Triple.h" 22 #include "llvm/TargetParser/X86TargetParser.h" 23 #include <string.h> 24 25 // Include the platform-specific parts of this class. 26 #ifdef LLVM_ON_UNIX 27 #include "Unix/Host.inc" 28 #include <sched.h> 29 #endif 30 #ifdef _WIN32 31 #include "Windows/Host.inc" 32 #endif 33 #ifdef _MSC_VER 34 #include <intrin.h> 35 #endif 36 #ifdef __MVS__ 37 #include "llvm/Support/BCD.h" 38 #endif 39 #if defined(__APPLE__) 40 #include <mach/host_info.h> 41 #include <mach/mach.h> 42 #include <mach/mach_host.h> 43 #include <mach/machine.h> 44 #include <sys/param.h> 45 #include <sys/sysctl.h> 46 #endif 47 #ifdef _AIX 48 #include <sys/systemcfg.h> 49 #endif 50 #if defined(__sun__) && defined(__svr4__) 51 #include <kstat.h> 52 #endif 53 54 #define DEBUG_TYPE "host-detection" 55 56 //===----------------------------------------------------------------------===// 57 // 58 // Implementations of the CPU detection routines 59 // 60 //===----------------------------------------------------------------------===// 61 62 using namespace llvm; 63 64 static std::unique_ptr<llvm::MemoryBuffer> 65 LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() { 66 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 67 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 68 if (std::error_code EC = Text.getError()) { 69 llvm::errs() << "Can't read " 70 << "/proc/cpuinfo: " << EC.message() << "\n"; 71 return nullptr; 72 } 73 return std::move(*Text); 74 } 75 76 StringRef sys::detail::getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent) { 77 // Access to the Processor Version Register (PVR) on PowerPC is privileged, 78 // and so we must use an operating-system interface to determine the current 79 // processor type. On Linux, this is exposed through the /proc/cpuinfo file. 80 const char *generic = "generic"; 81 82 // The cpu line is second (after the 'processor: 0' line), so if this 83 // buffer is too small then something has changed (or is wrong). 84 StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin(); 85 StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end(); 86 87 StringRef::const_iterator CIP = CPUInfoStart; 88 89 StringRef::const_iterator CPUStart = nullptr; 90 size_t CPULen = 0; 91 92 // We need to find the first line which starts with cpu, spaces, and a colon. 93 // After the colon, there may be some additional spaces and then the cpu type. 94 while (CIP < CPUInfoEnd && CPUStart == nullptr) { 95 if (CIP < CPUInfoEnd && *CIP == '\n') 96 ++CIP; 97 98 if (CIP < CPUInfoEnd && *CIP == 'c') { 99 ++CIP; 100 if (CIP < CPUInfoEnd && *CIP == 'p') { 101 ++CIP; 102 if (CIP < CPUInfoEnd && *CIP == 'u') { 103 ++CIP; 104 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 105 ++CIP; 106 107 if (CIP < CPUInfoEnd && *CIP == ':') { 108 ++CIP; 109 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 110 ++CIP; 111 112 if (CIP < CPUInfoEnd) { 113 CPUStart = CIP; 114 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && 115 *CIP != ',' && *CIP != '\n')) 116 ++CIP; 117 CPULen = CIP - CPUStart; 118 } 119 } 120 } 121 } 122 } 123 124 if (CPUStart == nullptr) 125 while (CIP < CPUInfoEnd && *CIP != '\n') 126 ++CIP; 127 } 128 129 if (CPUStart == nullptr) 130 return generic; 131 132 return StringSwitch<const char *>(StringRef(CPUStart, CPULen)) 133 .Case("604e", "604e") 134 .Case("604", "604") 135 .Case("7400", "7400") 136 .Case("7410", "7400") 137 .Case("7447", "7400") 138 .Case("7455", "7450") 139 .Case("G4", "g4") 140 .Case("POWER4", "970") 141 .Case("PPC970FX", "970") 142 .Case("PPC970MP", "970") 143 .Case("G5", "g5") 144 .Case("POWER5", "g5") 145 .Case("A2", "a2") 146 .Case("POWER6", "pwr6") 147 .Case("POWER7", "pwr7") 148 .Case("POWER8", "pwr8") 149 .Case("POWER8E", "pwr8") 150 .Case("POWER8NVL", "pwr8") 151 .Case("POWER9", "pwr9") 152 .Case("POWER10", "pwr10") 153 // FIXME: If we get a simulator or machine with the capabilities of 154 // mcpu=future, we should revisit this and add the name reported by the 155 // simulator/machine. 156 .Default(generic); 157 } 158 159 StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) { 160 // The cpuid register on arm is not accessible from user space. On Linux, 161 // it is exposed through the /proc/cpuinfo file. 162 163 // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line 164 // in all cases. 165 SmallVector<StringRef, 32> Lines; 166 ProcCpuinfoContent.split(Lines, "\n"); 167 168 // Look for the CPU implementer line. 169 StringRef Implementer; 170 StringRef Hardware; 171 StringRef Part; 172 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 173 if (Lines[I].starts_with("CPU implementer")) 174 Implementer = Lines[I].substr(15).ltrim("\t :"); 175 if (Lines[I].starts_with("Hardware")) 176 Hardware = Lines[I].substr(8).ltrim("\t :"); 177 if (Lines[I].starts_with("CPU part")) 178 Part = Lines[I].substr(8).ltrim("\t :"); 179 } 180 181 if (Implementer == "0x41") { // ARM Ltd. 182 // MSM8992/8994 may give cpu part for the core that the kernel is running on, 183 // which is undeterministic and wrong. Always return cortex-a53 for these SoC. 184 if (Hardware.ends_with("MSM8994") || Hardware.ends_with("MSM8996")) 185 return "cortex-a53"; 186 187 188 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 189 // values correspond to the "Part number" in the CP15/c0 register. The 190 // contents are specified in the various processor manuals. 191 // This corresponds to the Main ID Register in Technical Reference Manuals. 192 // and is used in programs like sys-utils 193 return StringSwitch<const char *>(Part) 194 .Case("0x926", "arm926ej-s") 195 .Case("0xb02", "mpcore") 196 .Case("0xb36", "arm1136j-s") 197 .Case("0xb56", "arm1156t2-s") 198 .Case("0xb76", "arm1176jz-s") 199 .Case("0xc05", "cortex-a5") 200 .Case("0xc07", "cortex-a7") 201 .Case("0xc08", "cortex-a8") 202 .Case("0xc09", "cortex-a9") 203 .Case("0xc0f", "cortex-a15") 204 .Case("0xc0e", "cortex-a17") 205 .Case("0xc20", "cortex-m0") 206 .Case("0xc23", "cortex-m3") 207 .Case("0xc24", "cortex-m4") 208 .Case("0xc27", "cortex-m7") 209 .Case("0xd20", "cortex-m23") 210 .Case("0xd21", "cortex-m33") 211 .Case("0xd24", "cortex-m52") 212 .Case("0xd22", "cortex-m55") 213 .Case("0xd23", "cortex-m85") 214 .Case("0xc18", "cortex-r8") 215 .Case("0xd13", "cortex-r52") 216 .Case("0xd16", "cortex-r52plus") 217 .Case("0xd15", "cortex-r82") 218 .Case("0xd14", "cortex-r82ae") 219 .Case("0xd02", "cortex-a34") 220 .Case("0xd04", "cortex-a35") 221 .Case("0xd03", "cortex-a53") 222 .Case("0xd05", "cortex-a55") 223 .Case("0xd46", "cortex-a510") 224 .Case("0xd80", "cortex-a520") 225 .Case("0xd88", "cortex-a520ae") 226 .Case("0xd07", "cortex-a57") 227 .Case("0xd06", "cortex-a65") 228 .Case("0xd43", "cortex-a65ae") 229 .Case("0xd08", "cortex-a72") 230 .Case("0xd09", "cortex-a73") 231 .Case("0xd0a", "cortex-a75") 232 .Case("0xd0b", "cortex-a76") 233 .Case("0xd0e", "cortex-a76ae") 234 .Case("0xd0d", "cortex-a77") 235 .Case("0xd41", "cortex-a78") 236 .Case("0xd42", "cortex-a78ae") 237 .Case("0xd4b", "cortex-a78c") 238 .Case("0xd47", "cortex-a710") 239 .Case("0xd4d", "cortex-a715") 240 .Case("0xd81", "cortex-a720") 241 .Case("0xd89", "cortex-a720ae") 242 .Case("0xd87", "cortex-a725") 243 .Case("0xd44", "cortex-x1") 244 .Case("0xd4c", "cortex-x1c") 245 .Case("0xd48", "cortex-x2") 246 .Case("0xd4e", "cortex-x3") 247 .Case("0xd82", "cortex-x4") 248 .Case("0xd85", "cortex-x925") 249 .Case("0xd4a", "neoverse-e1") 250 .Case("0xd0c", "neoverse-n1") 251 .Case("0xd49", "neoverse-n2") 252 .Case("0xd8e", "neoverse-n3") 253 .Case("0xd40", "neoverse-v1") 254 .Case("0xd4f", "neoverse-v2") 255 .Case("0xd84", "neoverse-v3") 256 .Case("0xd83", "neoverse-v3ae") 257 .Default("generic"); 258 } 259 260 if (Implementer == "0x42" || Implementer == "0x43") { // Broadcom | Cavium. 261 return StringSwitch<const char *>(Part) 262 .Case("0x516", "thunderx2t99") 263 .Case("0x0516", "thunderx2t99") 264 .Case("0xaf", "thunderx2t99") 265 .Case("0x0af", "thunderx2t99") 266 .Case("0xa1", "thunderxt88") 267 .Case("0x0a1", "thunderxt88") 268 .Default("generic"); 269 } 270 271 if (Implementer == "0x46") { // Fujitsu Ltd. 272 return StringSwitch<const char *>(Part) 273 .Case("0x001", "a64fx") 274 .Default("generic"); 275 } 276 277 if (Implementer == "0x4e") { // NVIDIA Corporation 278 return StringSwitch<const char *>(Part) 279 .Case("0x004", "carmel") 280 .Default("generic"); 281 } 282 283 if (Implementer == "0x48") // HiSilicon Technologies, Inc. 284 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 285 // values correspond to the "Part number" in the CP15/c0 register. The 286 // contents are specified in the various processor manuals. 287 return StringSwitch<const char *>(Part) 288 .Case("0xd01", "tsv110") 289 .Default("generic"); 290 291 if (Implementer == "0x51") // Qualcomm Technologies, Inc. 292 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 293 // values correspond to the "Part number" in the CP15/c0 register. The 294 // contents are specified in the various processor manuals. 295 return StringSwitch<const char *>(Part) 296 .Case("0x06f", "krait") // APQ8064 297 .Case("0x201", "kryo") 298 .Case("0x205", "kryo") 299 .Case("0x211", "kryo") 300 .Case("0x800", "cortex-a73") // Kryo 2xx Gold 301 .Case("0x801", "cortex-a73") // Kryo 2xx Silver 302 .Case("0x802", "cortex-a75") // Kryo 3xx Gold 303 .Case("0x803", "cortex-a75") // Kryo 3xx Silver 304 .Case("0x804", "cortex-a76") // Kryo 4xx Gold 305 .Case("0x805", "cortex-a76") // Kryo 4xx/5xx Silver 306 .Case("0xc00", "falkor") 307 .Case("0xc01", "saphira") 308 .Case("0x001", "oryon-1") 309 .Default("generic"); 310 if (Implementer == "0x53") { // Samsung Electronics Co., Ltd. 311 // The Exynos chips have a convoluted ID scheme that doesn't seem to follow 312 // any predictive pattern across variants and parts. 313 unsigned Variant = 0, Part = 0; 314 315 // Look for the CPU variant line, whose value is a 1 digit hexadecimal 316 // number, corresponding to the Variant bits in the CP15/C0 register. 317 for (auto I : Lines) 318 if (I.consume_front("CPU variant")) 319 I.ltrim("\t :").getAsInteger(0, Variant); 320 321 // Look for the CPU part line, whose value is a 3 digit hexadecimal 322 // number, corresponding to the PartNum bits in the CP15/C0 register. 323 for (auto I : Lines) 324 if (I.consume_front("CPU part")) 325 I.ltrim("\t :").getAsInteger(0, Part); 326 327 unsigned Exynos = (Variant << 12) | Part; 328 switch (Exynos) { 329 default: 330 // Default by falling through to Exynos M3. 331 [[fallthrough]]; 332 case 0x1002: 333 return "exynos-m3"; 334 case 0x1003: 335 return "exynos-m4"; 336 } 337 } 338 339 if (Implementer == "0x6d") { // Microsoft Corporation. 340 // The Microsoft Azure Cobalt 100 CPU is handled as a Neoverse N2. 341 return StringSwitch<const char *>(Part) 342 .Case("0xd49", "neoverse-n2") 343 .Default("generic"); 344 } 345 346 if (Implementer == "0xc0") { // Ampere Computing 347 return StringSwitch<const char *>(Part) 348 .Case("0xac3", "ampere1") 349 .Case("0xac4", "ampere1a") 350 .Case("0xac5", "ampere1b") 351 .Default("generic"); 352 } 353 354 return "generic"; 355 } 356 357 namespace { 358 StringRef getCPUNameFromS390Model(unsigned int Id, bool HaveVectorSupport) { 359 switch (Id) { 360 case 2064: // z900 not supported by LLVM 361 case 2066: 362 case 2084: // z990 not supported by LLVM 363 case 2086: 364 case 2094: // z9-109 not supported by LLVM 365 case 2096: 366 return "generic"; 367 case 2097: 368 case 2098: 369 return "z10"; 370 case 2817: 371 case 2818: 372 return "z196"; 373 case 2827: 374 case 2828: 375 return "zEC12"; 376 case 2964: 377 case 2965: 378 return HaveVectorSupport? "z13" : "zEC12"; 379 case 3906: 380 case 3907: 381 return HaveVectorSupport? "z14" : "zEC12"; 382 case 8561: 383 case 8562: 384 return HaveVectorSupport? "z15" : "zEC12"; 385 case 3931: 386 case 3932: 387 default: 388 return HaveVectorSupport? "z16" : "zEC12"; 389 } 390 } 391 } // end anonymous namespace 392 393 StringRef sys::detail::getHostCPUNameForS390x(StringRef ProcCpuinfoContent) { 394 // STIDP is a privileged operation, so use /proc/cpuinfo instead. 395 396 // The "processor 0:" line comes after a fair amount of other information, 397 // including a cache breakdown, but this should be plenty. 398 SmallVector<StringRef, 32> Lines; 399 ProcCpuinfoContent.split(Lines, "\n"); 400 401 // Look for the CPU features. 402 SmallVector<StringRef, 32> CPUFeatures; 403 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 404 if (Lines[I].starts_with("features")) { 405 size_t Pos = Lines[I].find(':'); 406 if (Pos != StringRef::npos) { 407 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); 408 break; 409 } 410 } 411 412 // We need to check for the presence of vector support independently of 413 // the machine type, since we may only use the vector register set when 414 // supported by the kernel (and hypervisor). 415 bool HaveVectorSupport = false; 416 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 417 if (CPUFeatures[I] == "vx") 418 HaveVectorSupport = true; 419 } 420 421 // Now check the processor machine type. 422 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 423 if (Lines[I].starts_with("processor ")) { 424 size_t Pos = Lines[I].find("machine = "); 425 if (Pos != StringRef::npos) { 426 Pos += sizeof("machine = ") - 1; 427 unsigned int Id; 428 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) 429 return getCPUNameFromS390Model(Id, HaveVectorSupport); 430 } 431 break; 432 } 433 } 434 435 return "generic"; 436 } 437 438 StringRef sys::detail::getHostCPUNameForRISCV(StringRef ProcCpuinfoContent) { 439 // There are 24 lines in /proc/cpuinfo 440 SmallVector<StringRef> Lines; 441 ProcCpuinfoContent.split(Lines, "\n"); 442 443 // Look for uarch line to determine cpu name 444 StringRef UArch; 445 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 446 if (Lines[I].starts_with("uarch")) { 447 UArch = Lines[I].substr(5).ltrim("\t :"); 448 break; 449 } 450 } 451 452 return StringSwitch<const char *>(UArch) 453 .Case("sifive,u74-mc", "sifive-u74") 454 .Case("sifive,bullet0", "sifive-u74") 455 .Default(""); 456 } 457 458 StringRef sys::detail::getHostCPUNameForBPF() { 459 #if !defined(__linux__) || !defined(__x86_64__) 460 return "generic"; 461 #else 462 uint8_t v3_insns[40] __attribute__ ((aligned (8))) = 463 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 464 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 465 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 466 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 467 /* BPF_JMP32_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 468 0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 469 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 470 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 471 /* BPF_EXIT_INSN() */ 472 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 473 474 uint8_t v2_insns[40] __attribute__ ((aligned (8))) = 475 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 476 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 477 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 478 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 479 /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 480 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 481 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 482 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 483 /* BPF_EXIT_INSN() */ 484 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 485 486 struct bpf_prog_load_attr { 487 uint32_t prog_type; 488 uint32_t insn_cnt; 489 uint64_t insns; 490 uint64_t license; 491 uint32_t log_level; 492 uint32_t log_size; 493 uint64_t log_buf; 494 uint32_t kern_version; 495 uint32_t prog_flags; 496 } attr = {}; 497 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 498 attr.insn_cnt = 5; 499 attr.insns = (uint64_t)v3_insns; 500 attr.license = (uint64_t)"DUMMY"; 501 502 int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, 503 sizeof(attr)); 504 if (fd >= 0) { 505 close(fd); 506 return "v3"; 507 } 508 509 /* Clear the whole attr in case its content changed by syscall. */ 510 memset(&attr, 0, sizeof(attr)); 511 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 512 attr.insn_cnt = 5; 513 attr.insns = (uint64_t)v2_insns; 514 attr.license = (uint64_t)"DUMMY"; 515 fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr)); 516 if (fd >= 0) { 517 close(fd); 518 return "v2"; 519 } 520 return "v1"; 521 #endif 522 } 523 524 #if defined(__i386__) || defined(_M_IX86) || \ 525 defined(__x86_64__) || defined(_M_X64) 526 527 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max). 528 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID 529 // support. Consequently, for i386, the presence of CPUID is checked first 530 // via the corresponding eflags bit. 531 // Removal of cpuid.h header motivated by PR30384 532 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp 533 // or test-suite, but are used in external projects e.g. libstdcxx 534 static bool isCpuIdSupported() { 535 #if defined(__GNUC__) || defined(__clang__) 536 #if defined(__i386__) 537 int __cpuid_supported; 538 __asm__(" pushfl\n" 539 " popl %%eax\n" 540 " movl %%eax,%%ecx\n" 541 " xorl $0x00200000,%%eax\n" 542 " pushl %%eax\n" 543 " popfl\n" 544 " pushfl\n" 545 " popl %%eax\n" 546 " movl $0,%0\n" 547 " cmpl %%eax,%%ecx\n" 548 " je 1f\n" 549 " movl $1,%0\n" 550 "1:" 551 : "=r"(__cpuid_supported) 552 : 553 : "eax", "ecx"); 554 if (!__cpuid_supported) 555 return false; 556 #endif 557 return true; 558 #endif 559 return true; 560 } 561 562 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in 563 /// the specified arguments. If we can't run cpuid on the host, return true. 564 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, 565 unsigned *rECX, unsigned *rEDX) { 566 #if defined(__GNUC__) || defined(__clang__) 567 #if defined(__x86_64__) 568 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 569 // FIXME: should we save this for Clang? 570 __asm__("movq\t%%rbx, %%rsi\n\t" 571 "cpuid\n\t" 572 "xchgq\t%%rbx, %%rsi\n\t" 573 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 574 : "a"(value)); 575 return false; 576 #elif defined(__i386__) 577 __asm__("movl\t%%ebx, %%esi\n\t" 578 "cpuid\n\t" 579 "xchgl\t%%ebx, %%esi\n\t" 580 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 581 : "a"(value)); 582 return false; 583 #else 584 return true; 585 #endif 586 #elif defined(_MSC_VER) 587 // The MSVC intrinsic is portable across x86 and x64. 588 int registers[4]; 589 __cpuid(registers, value); 590 *rEAX = registers[0]; 591 *rEBX = registers[1]; 592 *rECX = registers[2]; 593 *rEDX = registers[3]; 594 return false; 595 #else 596 return true; 597 #endif 598 } 599 600 namespace llvm { 601 namespace sys { 602 namespace detail { 603 namespace x86 { 604 605 VendorSignatures getVendorSignature(unsigned *MaxLeaf) { 606 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 607 if (MaxLeaf == nullptr) 608 MaxLeaf = &EAX; 609 else 610 *MaxLeaf = 0; 611 612 if (!isCpuIdSupported()) 613 return VendorSignatures::UNKNOWN; 614 615 if (getX86CpuIDAndInfo(0, MaxLeaf, &EBX, &ECX, &EDX) || *MaxLeaf < 1) 616 return VendorSignatures::UNKNOWN; 617 618 // "Genu ineI ntel" 619 if (EBX == 0x756e6547 && EDX == 0x49656e69 && ECX == 0x6c65746e) 620 return VendorSignatures::GENUINE_INTEL; 621 622 // "Auth enti cAMD" 623 if (EBX == 0x68747541 && EDX == 0x69746e65 && ECX == 0x444d4163) 624 return VendorSignatures::AUTHENTIC_AMD; 625 626 return VendorSignatures::UNKNOWN; 627 } 628 629 } // namespace x86 630 } // namespace detail 631 } // namespace sys 632 } // namespace llvm 633 634 using namespace llvm::sys::detail::x86; 635 636 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return 637 /// the 4 values in the specified arguments. If we can't run cpuid on the host, 638 /// return true. 639 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, 640 unsigned *rEAX, unsigned *rEBX, unsigned *rECX, 641 unsigned *rEDX) { 642 #if defined(__GNUC__) || defined(__clang__) 643 #if defined(__x86_64__) 644 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 645 // FIXME: should we save this for Clang? 646 __asm__("movq\t%%rbx, %%rsi\n\t" 647 "cpuid\n\t" 648 "xchgq\t%%rbx, %%rsi\n\t" 649 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 650 : "a"(value), "c"(subleaf)); 651 return false; 652 #elif defined(__i386__) 653 __asm__("movl\t%%ebx, %%esi\n\t" 654 "cpuid\n\t" 655 "xchgl\t%%ebx, %%esi\n\t" 656 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 657 : "a"(value), "c"(subleaf)); 658 return false; 659 #else 660 return true; 661 #endif 662 #elif defined(_MSC_VER) 663 int registers[4]; 664 __cpuidex(registers, value, subleaf); 665 *rEAX = registers[0]; 666 *rEBX = registers[1]; 667 *rECX = registers[2]; 668 *rEDX = registers[3]; 669 return false; 670 #else 671 return true; 672 #endif 673 } 674 675 // Read control register 0 (XCR0). Used to detect features such as AVX. 676 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) { 677 #if defined(__GNUC__) || defined(__clang__) 678 // Check xgetbv; this uses a .byte sequence instead of the instruction 679 // directly because older assemblers do not include support for xgetbv and 680 // there is no easy way to conditionally compile based on the assembler used. 681 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0)); 682 return false; 683 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) 684 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); 685 *rEAX = Result; 686 *rEDX = Result >> 32; 687 return false; 688 #else 689 return true; 690 #endif 691 } 692 693 static void detectX86FamilyModel(unsigned EAX, unsigned *Family, 694 unsigned *Model) { 695 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 696 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 697 if (*Family == 6 || *Family == 0xf) { 698 if (*Family == 0xf) 699 // Examine extended family ID if family ID is F. 700 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27 701 // Examine extended model ID if family ID is 6 or F. 702 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 703 } 704 } 705 706 #define testFeature(F) (Features[F / 32] & (1 << (F % 32))) != 0 707 708 static StringRef getIntelProcessorTypeAndSubtype(unsigned Family, 709 unsigned Model, 710 const unsigned *Features, 711 unsigned *Type, 712 unsigned *Subtype) { 713 StringRef CPU; 714 715 switch (Family) { 716 case 3: 717 CPU = "i386"; 718 break; 719 case 4: 720 CPU = "i486"; 721 break; 722 case 5: 723 if (testFeature(X86::FEATURE_MMX)) { 724 CPU = "pentium-mmx"; 725 break; 726 } 727 CPU = "pentium"; 728 break; 729 case 6: 730 switch (Model) { 731 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile 732 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad 733 // mobile processor, Intel Core 2 Extreme processor, Intel 734 // Pentium Dual-Core processor, Intel Xeon processor, model 735 // 0Fh. All processors are manufactured using the 65 nm process. 736 case 0x16: // Intel Celeron processor model 16h. All processors are 737 // manufactured using the 65 nm process 738 CPU = "core2"; 739 *Type = X86::INTEL_CORE2; 740 break; 741 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model 742 // 17h. All processors are manufactured using the 45 nm process. 743 // 744 // 45nm: Penryn , Wolfdale, Yorkfield (XE) 745 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using 746 // the 45 nm process. 747 CPU = "penryn"; 748 *Type = X86::INTEL_CORE2; 749 break; 750 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All 751 // processors are manufactured using the 45 nm process. 752 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. 753 // As found in a Summer 2010 model iMac. 754 case 0x1f: 755 case 0x2e: // Nehalem EX 756 CPU = "nehalem"; 757 *Type = X86::INTEL_COREI7; 758 *Subtype = X86::INTEL_COREI7_NEHALEM; 759 break; 760 case 0x25: // Intel Core i7, laptop version. 761 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All 762 // processors are manufactured using the 32 nm process. 763 case 0x2f: // Westmere EX 764 CPU = "westmere"; 765 *Type = X86::INTEL_COREI7; 766 *Subtype = X86::INTEL_COREI7_WESTMERE; 767 break; 768 case 0x2a: // Intel Core i7 processor. All processors are manufactured 769 // using the 32 nm process. 770 case 0x2d: 771 CPU = "sandybridge"; 772 *Type = X86::INTEL_COREI7; 773 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; 774 break; 775 case 0x3a: 776 case 0x3e: // Ivy Bridge EP 777 CPU = "ivybridge"; 778 *Type = X86::INTEL_COREI7; 779 *Subtype = X86::INTEL_COREI7_IVYBRIDGE; 780 break; 781 782 // Haswell: 783 case 0x3c: 784 case 0x3f: 785 case 0x45: 786 case 0x46: 787 CPU = "haswell"; 788 *Type = X86::INTEL_COREI7; 789 *Subtype = X86::INTEL_COREI7_HASWELL; 790 break; 791 792 // Broadwell: 793 case 0x3d: 794 case 0x47: 795 case 0x4f: 796 case 0x56: 797 CPU = "broadwell"; 798 *Type = X86::INTEL_COREI7; 799 *Subtype = X86::INTEL_COREI7_BROADWELL; 800 break; 801 802 // Skylake: 803 case 0x4e: // Skylake mobile 804 case 0x5e: // Skylake desktop 805 case 0x8e: // Kaby Lake mobile 806 case 0x9e: // Kaby Lake desktop 807 case 0xa5: // Comet Lake-H/S 808 case 0xa6: // Comet Lake-U 809 CPU = "skylake"; 810 *Type = X86::INTEL_COREI7; 811 *Subtype = X86::INTEL_COREI7_SKYLAKE; 812 break; 813 814 // Rocketlake: 815 case 0xa7: 816 CPU = "rocketlake"; 817 *Type = X86::INTEL_COREI7; 818 *Subtype = X86::INTEL_COREI7_ROCKETLAKE; 819 break; 820 821 // Skylake Xeon: 822 case 0x55: 823 *Type = X86::INTEL_COREI7; 824 if (testFeature(X86::FEATURE_AVX512BF16)) { 825 CPU = "cooperlake"; 826 *Subtype = X86::INTEL_COREI7_COOPERLAKE; 827 } else if (testFeature(X86::FEATURE_AVX512VNNI)) { 828 CPU = "cascadelake"; 829 *Subtype = X86::INTEL_COREI7_CASCADELAKE; 830 } else { 831 CPU = "skylake-avx512"; 832 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; 833 } 834 break; 835 836 // Cannonlake: 837 case 0x66: 838 CPU = "cannonlake"; 839 *Type = X86::INTEL_COREI7; 840 *Subtype = X86::INTEL_COREI7_CANNONLAKE; 841 break; 842 843 // Icelake: 844 case 0x7d: 845 case 0x7e: 846 CPU = "icelake-client"; 847 *Type = X86::INTEL_COREI7; 848 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT; 849 break; 850 851 // Tigerlake: 852 case 0x8c: 853 case 0x8d: 854 CPU = "tigerlake"; 855 *Type = X86::INTEL_COREI7; 856 *Subtype = X86::INTEL_COREI7_TIGERLAKE; 857 break; 858 859 // Alderlake: 860 case 0x97: 861 case 0x9a: 862 // Gracemont 863 case 0xbe: 864 // Raptorlake: 865 case 0xb7: 866 case 0xba: 867 case 0xbf: 868 // Meteorlake: 869 case 0xaa: 870 case 0xac: 871 CPU = "alderlake"; 872 *Type = X86::INTEL_COREI7; 873 *Subtype = X86::INTEL_COREI7_ALDERLAKE; 874 break; 875 876 // Arrowlake: 877 case 0xc5: 878 CPU = "arrowlake"; 879 *Type = X86::INTEL_COREI7; 880 *Subtype = X86::INTEL_COREI7_ARROWLAKE; 881 break; 882 883 // Arrowlake S: 884 case 0xc6: 885 // Lunarlake: 886 case 0xbd: 887 CPU = "arrowlake-s"; 888 *Type = X86::INTEL_COREI7; 889 *Subtype = X86::INTEL_COREI7_ARROWLAKE_S; 890 break; 891 892 // Pantherlake: 893 case 0xcc: 894 CPU = "pantherlake"; 895 *Type = X86::INTEL_COREI7; 896 *Subtype = X86::INTEL_COREI7_PANTHERLAKE; 897 break; 898 899 // Graniterapids: 900 case 0xad: 901 CPU = "graniterapids"; 902 *Type = X86::INTEL_COREI7; 903 *Subtype = X86::INTEL_COREI7_GRANITERAPIDS; 904 break; 905 906 // Granite Rapids D: 907 case 0xae: 908 CPU = "graniterapids-d"; 909 *Type = X86::INTEL_COREI7; 910 *Subtype = X86::INTEL_COREI7_GRANITERAPIDS_D; 911 break; 912 913 // Icelake Xeon: 914 case 0x6a: 915 case 0x6c: 916 CPU = "icelake-server"; 917 *Type = X86::INTEL_COREI7; 918 *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER; 919 break; 920 921 // Emerald Rapids: 922 case 0xcf: 923 // Sapphire Rapids: 924 case 0x8f: 925 CPU = "sapphirerapids"; 926 *Type = X86::INTEL_COREI7; 927 *Subtype = X86::INTEL_COREI7_SAPPHIRERAPIDS; 928 break; 929 930 case 0x1c: // Most 45 nm Intel Atom processors 931 case 0x26: // 45 nm Atom Lincroft 932 case 0x27: // 32 nm Atom Medfield 933 case 0x35: // 32 nm Atom Midview 934 case 0x36: // 32 nm Atom Midview 935 CPU = "bonnell"; 936 *Type = X86::INTEL_BONNELL; 937 break; 938 939 // Atom Silvermont codes from the Intel software optimization guide. 940 case 0x37: 941 case 0x4a: 942 case 0x4d: 943 case 0x5a: 944 case 0x5d: 945 case 0x4c: // really airmont 946 CPU = "silvermont"; 947 *Type = X86::INTEL_SILVERMONT; 948 break; 949 // Goldmont: 950 case 0x5c: // Apollo Lake 951 case 0x5f: // Denverton 952 CPU = "goldmont"; 953 *Type = X86::INTEL_GOLDMONT; 954 break; 955 case 0x7a: 956 CPU = "goldmont-plus"; 957 *Type = X86::INTEL_GOLDMONT_PLUS; 958 break; 959 case 0x86: 960 case 0x8a: // Lakefield 961 case 0x96: // Elkhart Lake 962 case 0x9c: // Jasper Lake 963 CPU = "tremont"; 964 *Type = X86::INTEL_TREMONT; 965 break; 966 967 // Sierraforest: 968 case 0xaf: 969 CPU = "sierraforest"; 970 *Type = X86::INTEL_SIERRAFOREST; 971 break; 972 973 // Grandridge: 974 case 0xb6: 975 CPU = "grandridge"; 976 *Type = X86::INTEL_GRANDRIDGE; 977 break; 978 979 // Clearwaterforest: 980 case 0xdd: 981 CPU = "clearwaterforest"; 982 *Type = X86::INTEL_CLEARWATERFOREST; 983 break; 984 985 // Xeon Phi (Knights Landing + Knights Mill): 986 case 0x57: 987 CPU = "knl"; 988 *Type = X86::INTEL_KNL; 989 break; 990 case 0x85: 991 CPU = "knm"; 992 *Type = X86::INTEL_KNM; 993 break; 994 995 default: // Unknown family 6 CPU, try to guess. 996 // Don't both with Type/Subtype here, they aren't used by the caller. 997 // They're used above to keep the code in sync with compiler-rt. 998 // TODO detect tigerlake host from model 999 if (testFeature(X86::FEATURE_AVX512VP2INTERSECT)) { 1000 CPU = "tigerlake"; 1001 } else if (testFeature(X86::FEATURE_AVX512VBMI2)) { 1002 CPU = "icelake-client"; 1003 } else if (testFeature(X86::FEATURE_AVX512VBMI)) { 1004 CPU = "cannonlake"; 1005 } else if (testFeature(X86::FEATURE_AVX512BF16)) { 1006 CPU = "cooperlake"; 1007 } else if (testFeature(X86::FEATURE_AVX512VNNI)) { 1008 CPU = "cascadelake"; 1009 } else if (testFeature(X86::FEATURE_AVX512VL)) { 1010 CPU = "skylake-avx512"; 1011 } else if (testFeature(X86::FEATURE_CLFLUSHOPT)) { 1012 if (testFeature(X86::FEATURE_SHA)) 1013 CPU = "goldmont"; 1014 else 1015 CPU = "skylake"; 1016 } else if (testFeature(X86::FEATURE_ADX)) { 1017 CPU = "broadwell"; 1018 } else if (testFeature(X86::FEATURE_AVX2)) { 1019 CPU = "haswell"; 1020 } else if (testFeature(X86::FEATURE_AVX)) { 1021 CPU = "sandybridge"; 1022 } else if (testFeature(X86::FEATURE_SSE4_2)) { 1023 if (testFeature(X86::FEATURE_MOVBE)) 1024 CPU = "silvermont"; 1025 else 1026 CPU = "nehalem"; 1027 } else if (testFeature(X86::FEATURE_SSE4_1)) { 1028 CPU = "penryn"; 1029 } else if (testFeature(X86::FEATURE_SSSE3)) { 1030 if (testFeature(X86::FEATURE_MOVBE)) 1031 CPU = "bonnell"; 1032 else 1033 CPU = "core2"; 1034 } else if (testFeature(X86::FEATURE_64BIT)) { 1035 CPU = "core2"; 1036 } else if (testFeature(X86::FEATURE_SSE3)) { 1037 CPU = "yonah"; 1038 } else if (testFeature(X86::FEATURE_SSE2)) { 1039 CPU = "pentium-m"; 1040 } else if (testFeature(X86::FEATURE_SSE)) { 1041 CPU = "pentium3"; 1042 } else if (testFeature(X86::FEATURE_MMX)) { 1043 CPU = "pentium2"; 1044 } else { 1045 CPU = "pentiumpro"; 1046 } 1047 break; 1048 } 1049 break; 1050 case 15: { 1051 if (testFeature(X86::FEATURE_64BIT)) { 1052 CPU = "nocona"; 1053 break; 1054 } 1055 if (testFeature(X86::FEATURE_SSE3)) { 1056 CPU = "prescott"; 1057 break; 1058 } 1059 CPU = "pentium4"; 1060 break; 1061 } 1062 default: 1063 break; // Unknown. 1064 } 1065 1066 return CPU; 1067 } 1068 1069 static const char *getAMDProcessorTypeAndSubtype(unsigned Family, 1070 unsigned Model, 1071 const unsigned *Features, 1072 unsigned *Type, 1073 unsigned *Subtype) { 1074 const char *CPU = 0; 1075 1076 switch (Family) { 1077 case 4: 1078 CPU = "i486"; 1079 break; 1080 case 5: 1081 CPU = "pentium"; 1082 switch (Model) { 1083 case 6: 1084 case 7: 1085 CPU = "k6"; 1086 break; 1087 case 8: 1088 CPU = "k6-2"; 1089 break; 1090 case 9: 1091 case 13: 1092 CPU = "k6-3"; 1093 break; 1094 case 10: 1095 CPU = "geode"; 1096 break; 1097 } 1098 break; 1099 case 6: 1100 if (testFeature(X86::FEATURE_SSE)) { 1101 CPU = "athlon-xp"; 1102 break; 1103 } 1104 CPU = "athlon"; 1105 break; 1106 case 15: 1107 if (testFeature(X86::FEATURE_SSE3)) { 1108 CPU = "k8-sse3"; 1109 break; 1110 } 1111 CPU = "k8"; 1112 break; 1113 case 16: 1114 CPU = "amdfam10"; 1115 *Type = X86::AMDFAM10H; // "amdfam10" 1116 switch (Model) { 1117 case 2: 1118 *Subtype = X86::AMDFAM10H_BARCELONA; 1119 break; 1120 case 4: 1121 *Subtype = X86::AMDFAM10H_SHANGHAI; 1122 break; 1123 case 8: 1124 *Subtype = X86::AMDFAM10H_ISTANBUL; 1125 break; 1126 } 1127 break; 1128 case 20: 1129 CPU = "btver1"; 1130 *Type = X86::AMD_BTVER1; 1131 break; 1132 case 21: 1133 CPU = "bdver1"; 1134 *Type = X86::AMDFAM15H; 1135 if (Model >= 0x60 && Model <= 0x7f) { 1136 CPU = "bdver4"; 1137 *Subtype = X86::AMDFAM15H_BDVER4; 1138 break; // 60h-7Fh: Excavator 1139 } 1140 if (Model >= 0x30 && Model <= 0x3f) { 1141 CPU = "bdver3"; 1142 *Subtype = X86::AMDFAM15H_BDVER3; 1143 break; // 30h-3Fh: Steamroller 1144 } 1145 if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) { 1146 CPU = "bdver2"; 1147 *Subtype = X86::AMDFAM15H_BDVER2; 1148 break; // 02h, 10h-1Fh: Piledriver 1149 } 1150 if (Model <= 0x0f) { 1151 *Subtype = X86::AMDFAM15H_BDVER1; 1152 break; // 00h-0Fh: Bulldozer 1153 } 1154 break; 1155 case 22: 1156 CPU = "btver2"; 1157 *Type = X86::AMD_BTVER2; 1158 break; 1159 case 23: 1160 CPU = "znver1"; 1161 *Type = X86::AMDFAM17H; 1162 if ((Model >= 0x30 && Model <= 0x3f) || (Model == 0x47) || 1163 (Model >= 0x60 && Model <= 0x67) || (Model >= 0x68 && Model <= 0x6f) || 1164 (Model >= 0x70 && Model <= 0x7f) || (Model >= 0x84 && Model <= 0x87) || 1165 (Model >= 0x90 && Model <= 0x97) || (Model >= 0x98 && Model <= 0x9f) || 1166 (Model >= 0xa0 && Model <= 0xaf)) { 1167 // Family 17h Models 30h-3Fh (Starship) Zen 2 1168 // Family 17h Models 47h (Cardinal) Zen 2 1169 // Family 17h Models 60h-67h (Renoir) Zen 2 1170 // Family 17h Models 68h-6Fh (Lucienne) Zen 2 1171 // Family 17h Models 70h-7Fh (Matisse) Zen 2 1172 // Family 17h Models 84h-87h (ProjectX) Zen 2 1173 // Family 17h Models 90h-97h (VanGogh) Zen 2 1174 // Family 17h Models 98h-9Fh (Mero) Zen 2 1175 // Family 17h Models A0h-AFh (Mendocino) Zen 2 1176 CPU = "znver2"; 1177 *Subtype = X86::AMDFAM17H_ZNVER2; 1178 break; 1179 } 1180 if ((Model >= 0x10 && Model <= 0x1f) || (Model >= 0x20 && Model <= 0x2f)) { 1181 // Family 17h Models 10h-1Fh (Raven1) Zen 1182 // Family 17h Models 10h-1Fh (Picasso) Zen+ 1183 // Family 17h Models 20h-2Fh (Raven2 x86) Zen 1184 *Subtype = X86::AMDFAM17H_ZNVER1; 1185 break; 1186 } 1187 break; 1188 case 25: 1189 CPU = "znver3"; 1190 *Type = X86::AMDFAM19H; 1191 if (Model <= 0x0f || (Model >= 0x20 && Model <= 0x2f) || 1192 (Model >= 0x30 && Model <= 0x3f) || (Model >= 0x40 && Model <= 0x4f) || 1193 (Model >= 0x50 && Model <= 0x5f)) { 1194 // Family 19h Models 00h-0Fh (Genesis, Chagall) Zen 3 1195 // Family 19h Models 20h-2Fh (Vermeer) Zen 3 1196 // Family 19h Models 30h-3Fh (Badami) Zen 3 1197 // Family 19h Models 40h-4Fh (Rembrandt) Zen 3+ 1198 // Family 19h Models 50h-5Fh (Cezanne) Zen 3 1199 *Subtype = X86::AMDFAM19H_ZNVER3; 1200 break; 1201 } 1202 if ((Model >= 0x10 && Model <= 0x1f) || (Model >= 0x60 && Model <= 0x6f) || 1203 (Model >= 0x70 && Model <= 0x77) || (Model >= 0x78 && Model <= 0x7f) || 1204 (Model >= 0xa0 && Model <= 0xaf)) { 1205 // Family 19h Models 10h-1Fh (Stones; Storm Peak) Zen 4 1206 // Family 19h Models 60h-6Fh (Raphael) Zen 4 1207 // Family 19h Models 70h-77h (Phoenix, Hawkpoint1) Zen 4 1208 // Family 19h Models 78h-7Fh (Phoenix 2, Hawkpoint2) Zen 4 1209 // Family 19h Models A0h-AFh (Stones-Dense) Zen 4 1210 CPU = "znver4"; 1211 *Subtype = X86::AMDFAM19H_ZNVER4; 1212 break; // "znver4" 1213 } 1214 break; // family 19h 1215 default: 1216 break; // Unknown AMD CPU. 1217 } 1218 1219 return CPU; 1220 } 1221 1222 #undef testFeature 1223 1224 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf, 1225 unsigned *Features) { 1226 unsigned EAX, EBX; 1227 1228 auto setFeature = [&](unsigned F) { 1229 Features[F / 32] |= 1U << (F % 32); 1230 }; 1231 1232 if ((EDX >> 15) & 1) 1233 setFeature(X86::FEATURE_CMOV); 1234 if ((EDX >> 23) & 1) 1235 setFeature(X86::FEATURE_MMX); 1236 if ((EDX >> 25) & 1) 1237 setFeature(X86::FEATURE_SSE); 1238 if ((EDX >> 26) & 1) 1239 setFeature(X86::FEATURE_SSE2); 1240 1241 if ((ECX >> 0) & 1) 1242 setFeature(X86::FEATURE_SSE3); 1243 if ((ECX >> 1) & 1) 1244 setFeature(X86::FEATURE_PCLMUL); 1245 if ((ECX >> 9) & 1) 1246 setFeature(X86::FEATURE_SSSE3); 1247 if ((ECX >> 12) & 1) 1248 setFeature(X86::FEATURE_FMA); 1249 if ((ECX >> 19) & 1) 1250 setFeature(X86::FEATURE_SSE4_1); 1251 if ((ECX >> 20) & 1) { 1252 setFeature(X86::FEATURE_SSE4_2); 1253 setFeature(X86::FEATURE_CRC32); 1254 } 1255 if ((ECX >> 23) & 1) 1256 setFeature(X86::FEATURE_POPCNT); 1257 if ((ECX >> 25) & 1) 1258 setFeature(X86::FEATURE_AES); 1259 1260 if ((ECX >> 22) & 1) 1261 setFeature(X86::FEATURE_MOVBE); 1262 1263 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1264 // indicates that the AVX registers will be saved and restored on context 1265 // switch, then we have full AVX support. 1266 const unsigned AVXBits = (1 << 27) | (1 << 28); 1267 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && 1268 ((EAX & 0x6) == 0x6); 1269 #if defined(__APPLE__) 1270 // Darwin lazily saves the AVX512 context on first use: trust that the OS will 1271 // save the AVX512 context if we use AVX512 instructions, even the bit is not 1272 // set right now. 1273 bool HasAVX512Save = true; 1274 #else 1275 // AVX512 requires additional context to be saved by the OS. 1276 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); 1277 #endif 1278 1279 if (HasAVX) 1280 setFeature(X86::FEATURE_AVX); 1281 1282 bool HasLeaf7 = 1283 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1284 1285 if (HasLeaf7 && ((EBX >> 3) & 1)) 1286 setFeature(X86::FEATURE_BMI); 1287 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX) 1288 setFeature(X86::FEATURE_AVX2); 1289 if (HasLeaf7 && ((EBX >> 8) & 1)) 1290 setFeature(X86::FEATURE_BMI2); 1291 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save) { 1292 setFeature(X86::FEATURE_AVX512F); 1293 setFeature(X86::FEATURE_EVEX512); 1294 } 1295 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save) 1296 setFeature(X86::FEATURE_AVX512DQ); 1297 if (HasLeaf7 && ((EBX >> 19) & 1)) 1298 setFeature(X86::FEATURE_ADX); 1299 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save) 1300 setFeature(X86::FEATURE_AVX512IFMA); 1301 if (HasLeaf7 && ((EBX >> 23) & 1)) 1302 setFeature(X86::FEATURE_CLFLUSHOPT); 1303 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save) 1304 setFeature(X86::FEATURE_AVX512CD); 1305 if (HasLeaf7 && ((EBX >> 29) & 1)) 1306 setFeature(X86::FEATURE_SHA); 1307 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save) 1308 setFeature(X86::FEATURE_AVX512BW); 1309 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save) 1310 setFeature(X86::FEATURE_AVX512VL); 1311 1312 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save) 1313 setFeature(X86::FEATURE_AVX512VBMI); 1314 if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save) 1315 setFeature(X86::FEATURE_AVX512VBMI2); 1316 if (HasLeaf7 && ((ECX >> 8) & 1)) 1317 setFeature(X86::FEATURE_GFNI); 1318 if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX) 1319 setFeature(X86::FEATURE_VPCLMULQDQ); 1320 if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save) 1321 setFeature(X86::FEATURE_AVX512VNNI); 1322 if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save) 1323 setFeature(X86::FEATURE_AVX512BITALG); 1324 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save) 1325 setFeature(X86::FEATURE_AVX512VPOPCNTDQ); 1326 1327 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save) 1328 setFeature(X86::FEATURE_AVX5124VNNIW); 1329 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save) 1330 setFeature(X86::FEATURE_AVX5124FMAPS); 1331 if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save) 1332 setFeature(X86::FEATURE_AVX512VP2INTERSECT); 1333 1334 // EAX from subleaf 0 is the maximum subleaf supported. Some CPUs don't 1335 // return all 0s for invalid subleaves so check the limit. 1336 bool HasLeaf7Subleaf1 = 1337 HasLeaf7 && EAX >= 1 && 1338 !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); 1339 if (HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save) 1340 setFeature(X86::FEATURE_AVX512BF16); 1341 1342 unsigned MaxExtLevel; 1343 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1344 1345 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1346 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1347 if (HasExtLeaf1 && ((ECX >> 6) & 1)) 1348 setFeature(X86::FEATURE_SSE4_A); 1349 if (HasExtLeaf1 && ((ECX >> 11) & 1)) 1350 setFeature(X86::FEATURE_XOP); 1351 if (HasExtLeaf1 && ((ECX >> 16) & 1)) 1352 setFeature(X86::FEATURE_FMA4); 1353 1354 if (HasExtLeaf1 && ((EDX >> 29) & 1)) 1355 setFeature(X86::FEATURE_64BIT); 1356 } 1357 1358 StringRef sys::getHostCPUName() { 1359 unsigned MaxLeaf = 0; 1360 const VendorSignatures Vendor = getVendorSignature(&MaxLeaf); 1361 if (Vendor == VendorSignatures::UNKNOWN) 1362 return "generic"; 1363 1364 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1365 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); 1366 1367 unsigned Family = 0, Model = 0; 1368 unsigned Features[(X86::CPU_FEATURE_MAX + 31) / 32] = {0}; 1369 detectX86FamilyModel(EAX, &Family, &Model); 1370 getAvailableFeatures(ECX, EDX, MaxLeaf, Features); 1371 1372 // These aren't consumed in this file, but we try to keep some source code the 1373 // same or similar to compiler-rt. 1374 unsigned Type = 0; 1375 unsigned Subtype = 0; 1376 1377 StringRef CPU; 1378 1379 if (Vendor == VendorSignatures::GENUINE_INTEL) { 1380 CPU = getIntelProcessorTypeAndSubtype(Family, Model, Features, &Type, 1381 &Subtype); 1382 } else if (Vendor == VendorSignatures::AUTHENTIC_AMD) { 1383 CPU = getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, 1384 &Subtype); 1385 } 1386 1387 if (!CPU.empty()) 1388 return CPU; 1389 1390 return "generic"; 1391 } 1392 1393 #elif defined(__APPLE__) && defined(__powerpc__) 1394 StringRef sys::getHostCPUName() { 1395 host_basic_info_data_t hostInfo; 1396 mach_msg_type_number_t infoCount; 1397 1398 infoCount = HOST_BASIC_INFO_COUNT; 1399 mach_port_t hostPort = mach_host_self(); 1400 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo, 1401 &infoCount); 1402 mach_port_deallocate(mach_task_self(), hostPort); 1403 1404 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) 1405 return "generic"; 1406 1407 switch (hostInfo.cpu_subtype) { 1408 case CPU_SUBTYPE_POWERPC_601: 1409 return "601"; 1410 case CPU_SUBTYPE_POWERPC_602: 1411 return "602"; 1412 case CPU_SUBTYPE_POWERPC_603: 1413 return "603"; 1414 case CPU_SUBTYPE_POWERPC_603e: 1415 return "603e"; 1416 case CPU_SUBTYPE_POWERPC_603ev: 1417 return "603ev"; 1418 case CPU_SUBTYPE_POWERPC_604: 1419 return "604"; 1420 case CPU_SUBTYPE_POWERPC_604e: 1421 return "604e"; 1422 case CPU_SUBTYPE_POWERPC_620: 1423 return "620"; 1424 case CPU_SUBTYPE_POWERPC_750: 1425 return "750"; 1426 case CPU_SUBTYPE_POWERPC_7400: 1427 return "7400"; 1428 case CPU_SUBTYPE_POWERPC_7450: 1429 return "7450"; 1430 case CPU_SUBTYPE_POWERPC_970: 1431 return "970"; 1432 default:; 1433 } 1434 1435 return "generic"; 1436 } 1437 #elif defined(__linux__) && defined(__powerpc__) 1438 StringRef sys::getHostCPUName() { 1439 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1440 StringRef Content = P ? P->getBuffer() : ""; 1441 return detail::getHostCPUNameForPowerPC(Content); 1442 } 1443 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1444 StringRef sys::getHostCPUName() { 1445 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1446 StringRef Content = P ? P->getBuffer() : ""; 1447 return detail::getHostCPUNameForARM(Content); 1448 } 1449 #elif defined(__linux__) && defined(__s390x__) 1450 StringRef sys::getHostCPUName() { 1451 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1452 StringRef Content = P ? P->getBuffer() : ""; 1453 return detail::getHostCPUNameForS390x(Content); 1454 } 1455 #elif defined(__MVS__) 1456 StringRef sys::getHostCPUName() { 1457 // Get pointer to Communications Vector Table (CVT). 1458 // The pointer is located at offset 16 of the Prefixed Save Area (PSA). 1459 // It is stored as 31 bit pointer and will be zero-extended to 64 bit. 1460 int *StartToCVTOffset = reinterpret_cast<int *>(0x10); 1461 // Since its stored as a 31-bit pointer, get the 4 bytes from the start 1462 // of address. 1463 int ReadValue = *StartToCVTOffset; 1464 // Explicitly clear the high order bit. 1465 ReadValue = (ReadValue & 0x7FFFFFFF); 1466 char *CVT = reinterpret_cast<char *>(ReadValue); 1467 // The model number is located in the CVT prefix at offset -6 and stored as 1468 // signless packed decimal. 1469 uint16_t Id = *(uint16_t *)&CVT[-6]; 1470 // Convert number to integer. 1471 Id = decodePackedBCD<uint16_t>(Id, false); 1472 // Check for vector support. It's stored in field CVTFLAG5 (offset 244), 1473 // bit CVTVEF (X'80'). The facilities list is part of the PSA but the vector 1474 // extension can only be used if bit CVTVEF is on. 1475 bool HaveVectorSupport = CVT[244] & 0x80; 1476 return getCPUNameFromS390Model(Id, HaveVectorSupport); 1477 } 1478 #elif defined(__APPLE__) && (defined(__arm__) || defined(__aarch64__)) 1479 #define CPUFAMILY_ARM_SWIFT 0x1e2d6381 1480 #define CPUFAMILY_ARM_CYCLONE 0x37a09642 1481 #define CPUFAMILY_ARM_TYPHOON 0x2c91a47e 1482 #define CPUFAMILY_ARM_TWISTER 0x92fb37c8 1483 #define CPUFAMILY_ARM_HURRICANE 0x67ceee93 1484 #define CPUFAMILY_ARM_MONSOON_MISTRAL 0xe81e7ef6 1485 #define CPUFAMILY_ARM_VORTEX_TEMPEST 0x07d34b9f 1486 #define CPUFAMILY_ARM_LIGHTNING_THUNDER 0x462504d2 1487 #define CPUFAMILY_ARM_FIRESTORM_ICESTORM 0x1b588bb3 1488 #define CPUFAMILY_ARM_BLIZZARD_AVALANCHE 0xda33d83d 1489 #define CPUFAMILY_ARM_EVEREST_SAWTOOTH 0x8765edea 1490 1491 StringRef sys::getHostCPUName() { 1492 uint32_t Family; 1493 size_t Length = sizeof(Family); 1494 sysctlbyname("hw.cpufamily", &Family, &Length, NULL, 0); 1495 1496 switch (Family) { 1497 case CPUFAMILY_ARM_SWIFT: 1498 return "swift"; 1499 case CPUFAMILY_ARM_CYCLONE: 1500 return "apple-a7"; 1501 case CPUFAMILY_ARM_TYPHOON: 1502 return "apple-a8"; 1503 case CPUFAMILY_ARM_TWISTER: 1504 return "apple-a9"; 1505 case CPUFAMILY_ARM_HURRICANE: 1506 return "apple-a10"; 1507 case CPUFAMILY_ARM_MONSOON_MISTRAL: 1508 return "apple-a11"; 1509 case CPUFAMILY_ARM_VORTEX_TEMPEST: 1510 return "apple-a12"; 1511 case CPUFAMILY_ARM_LIGHTNING_THUNDER: 1512 return "apple-a13"; 1513 case CPUFAMILY_ARM_FIRESTORM_ICESTORM: 1514 return "apple-m1"; 1515 case CPUFAMILY_ARM_BLIZZARD_AVALANCHE: 1516 return "apple-m2"; 1517 case CPUFAMILY_ARM_EVEREST_SAWTOOTH: 1518 return "apple-m3"; 1519 default: 1520 // Default to the newest CPU we know about. 1521 return "apple-m3"; 1522 } 1523 } 1524 #elif defined(_AIX) 1525 StringRef sys::getHostCPUName() { 1526 switch (_system_configuration.implementation) { 1527 case POWER_4: 1528 if (_system_configuration.version == PV_4_3) 1529 return "970"; 1530 return "pwr4"; 1531 case POWER_5: 1532 if (_system_configuration.version == PV_5) 1533 return "pwr5"; 1534 return "pwr5x"; 1535 case POWER_6: 1536 if (_system_configuration.version == PV_6_Compat) 1537 return "pwr6"; 1538 return "pwr6x"; 1539 case POWER_7: 1540 return "pwr7"; 1541 case POWER_8: 1542 return "pwr8"; 1543 case POWER_9: 1544 return "pwr9"; 1545 // TODO: simplify this once the macro is available in all OS levels. 1546 #ifdef POWER_10 1547 case POWER_10: 1548 #else 1549 case 0x40000: 1550 #endif 1551 return "pwr10"; 1552 default: 1553 return "generic"; 1554 } 1555 } 1556 #elif defined(__loongarch__) 1557 StringRef sys::getHostCPUName() { 1558 // Use processor id to detect cpu name. 1559 uint32_t processor_id; 1560 __asm__("cpucfg %[prid], $zero\n\t" : [prid] "=r"(processor_id)); 1561 // Refer PRID_SERIES_MASK in linux kernel: arch/loongarch/include/asm/cpu.h. 1562 switch (processor_id & 0xf000) { 1563 case 0xc000: // Loongson 64bit, 4-issue 1564 return "la464"; 1565 case 0xd000: // Loongson 64bit, 6-issue 1566 return "la664"; 1567 // TODO: Others. 1568 default: 1569 break; 1570 } 1571 return "generic"; 1572 } 1573 #elif defined(__riscv) 1574 StringRef sys::getHostCPUName() { 1575 #if defined(__linux__) 1576 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1577 StringRef Content = P ? P->getBuffer() : ""; 1578 StringRef Name = detail::getHostCPUNameForRISCV(Content); 1579 if (!Name.empty()) 1580 return Name; 1581 #endif 1582 #if __riscv_xlen == 64 1583 return "generic-rv64"; 1584 #elif __riscv_xlen == 32 1585 return "generic-rv32"; 1586 #else 1587 #error "Unhandled value of __riscv_xlen" 1588 #endif 1589 } 1590 #elif defined(__sparc__) 1591 #if defined(__linux__) 1592 StringRef sys::detail::getHostCPUNameForSPARC(StringRef ProcCpuinfoContent) { 1593 SmallVector<StringRef> Lines; 1594 ProcCpuinfoContent.split(Lines, "\n"); 1595 1596 // Look for cpu line to determine cpu name 1597 StringRef Cpu; 1598 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 1599 if (Lines[I].starts_with("cpu")) { 1600 Cpu = Lines[I].substr(5).ltrim("\t :"); 1601 break; 1602 } 1603 } 1604 1605 return StringSwitch<const char *>(Cpu) 1606 .StartsWith("SuperSparc", "supersparc") 1607 .StartsWith("HyperSparc", "hypersparc") 1608 .StartsWith("SpitFire", "ultrasparc") 1609 .StartsWith("BlackBird", "ultrasparc") 1610 .StartsWith("Sabre", " ultrasparc") 1611 .StartsWith("Hummingbird", "ultrasparc") 1612 .StartsWith("Cheetah", "ultrasparc3") 1613 .StartsWith("Jalapeno", "ultrasparc3") 1614 .StartsWith("Jaguar", "ultrasparc3") 1615 .StartsWith("Panther", "ultrasparc3") 1616 .StartsWith("Serrano", "ultrasparc3") 1617 .StartsWith("UltraSparc T1", "niagara") 1618 .StartsWith("UltraSparc T2", "niagara2") 1619 .StartsWith("UltraSparc T3", "niagara3") 1620 .StartsWith("UltraSparc T4", "niagara4") 1621 .StartsWith("UltraSparc T5", "niagara4") 1622 .StartsWith("LEON", "leon3") 1623 // niagara7/m8 not supported by LLVM yet. 1624 .StartsWith("SPARC-M7", "niagara4" /* "niagara7" */) 1625 .StartsWith("SPARC-S7", "niagara4" /* "niagara7" */) 1626 .StartsWith("SPARC-M8", "niagara4" /* "m8" */) 1627 .Default("generic"); 1628 } 1629 #endif 1630 1631 StringRef sys::getHostCPUName() { 1632 #if defined(__linux__) 1633 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1634 StringRef Content = P ? P->getBuffer() : ""; 1635 return detail::getHostCPUNameForSPARC(Content); 1636 #elif defined(__sun__) && defined(__svr4__) 1637 char *buf = NULL; 1638 kstat_ctl_t *kc; 1639 kstat_t *ksp; 1640 kstat_named_t *brand = NULL; 1641 1642 kc = kstat_open(); 1643 if (kc != NULL) { 1644 ksp = kstat_lookup(kc, const_cast<char *>("cpu_info"), -1, NULL); 1645 if (ksp != NULL && kstat_read(kc, ksp, NULL) != -1 && 1646 ksp->ks_type == KSTAT_TYPE_NAMED) 1647 brand = 1648 (kstat_named_t *)kstat_data_lookup(ksp, const_cast<char *>("brand")); 1649 if (brand != NULL && brand->data_type == KSTAT_DATA_STRING) 1650 buf = KSTAT_NAMED_STR_PTR(brand); 1651 } 1652 kstat_close(kc); 1653 1654 return StringSwitch<const char *>(buf) 1655 .Case("TMS390S10", "supersparc") // Texas Instruments microSPARC I 1656 .Case("TMS390Z50", "supersparc") // Texas Instruments SuperSPARC I 1657 .Case("TMS390Z55", 1658 "supersparc") // Texas Instruments SuperSPARC I with SuperCache 1659 .Case("MB86904", "supersparc") // Fujitsu microSPARC II 1660 .Case("MB86907", "supersparc") // Fujitsu TurboSPARC 1661 .Case("RT623", "hypersparc") // Ross hyperSPARC 1662 .Case("RT625", "hypersparc") 1663 .Case("RT626", "hypersparc") 1664 .Case("UltraSPARC-I", "ultrasparc") 1665 .Case("UltraSPARC-II", "ultrasparc") 1666 .Case("UltraSPARC-IIe", "ultrasparc") 1667 .Case("UltraSPARC-IIi", "ultrasparc") 1668 .Case("SPARC64-III", "ultrasparc") 1669 .Case("SPARC64-IV", "ultrasparc") 1670 .Case("UltraSPARC-III", "ultrasparc3") 1671 .Case("UltraSPARC-III+", "ultrasparc3") 1672 .Case("UltraSPARC-IIIi", "ultrasparc3") 1673 .Case("UltraSPARC-IIIi+", "ultrasparc3") 1674 .Case("UltraSPARC-IV", "ultrasparc3") 1675 .Case("UltraSPARC-IV+", "ultrasparc3") 1676 .Case("SPARC64-V", "ultrasparc3") 1677 .Case("SPARC64-VI", "ultrasparc3") 1678 .Case("SPARC64-VII", "ultrasparc3") 1679 .Case("UltraSPARC-T1", "niagara") 1680 .Case("UltraSPARC-T2", "niagara2") 1681 .Case("UltraSPARC-T2", "niagara2") 1682 .Case("UltraSPARC-T2+", "niagara2") 1683 .Case("SPARC-T3", "niagara3") 1684 .Case("SPARC-T4", "niagara4") 1685 .Case("SPARC-T5", "niagara4") 1686 // niagara7/m8 not supported by LLVM yet. 1687 .Case("SPARC-M7", "niagara4" /* "niagara7" */) 1688 .Case("SPARC-S7", "niagara4" /* "niagara7" */) 1689 .Case("SPARC-M8", "niagara4" /* "m8" */) 1690 .Default("generic"); 1691 #else 1692 return "generic"; 1693 #endif 1694 } 1695 #else 1696 StringRef sys::getHostCPUName() { return "generic"; } 1697 namespace llvm { 1698 namespace sys { 1699 namespace detail { 1700 namespace x86 { 1701 1702 VendorSignatures getVendorSignature(unsigned *MaxLeaf) { 1703 return VendorSignatures::UNKNOWN; 1704 } 1705 1706 } // namespace x86 1707 } // namespace detail 1708 } // namespace sys 1709 } // namespace llvm 1710 #endif 1711 1712 #if defined(__i386__) || defined(_M_IX86) || \ 1713 defined(__x86_64__) || defined(_M_X64) 1714 const StringMap<bool> sys::getHostCPUFeatures() { 1715 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1716 unsigned MaxLevel; 1717 StringMap<bool> Features; 1718 1719 if (getX86CpuIDAndInfo(0, &MaxLevel, &EBX, &ECX, &EDX) || MaxLevel < 1) 1720 return Features; 1721 1722 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); 1723 1724 Features["cx8"] = (EDX >> 8) & 1; 1725 Features["cmov"] = (EDX >> 15) & 1; 1726 Features["mmx"] = (EDX >> 23) & 1; 1727 Features["fxsr"] = (EDX >> 24) & 1; 1728 Features["sse"] = (EDX >> 25) & 1; 1729 Features["sse2"] = (EDX >> 26) & 1; 1730 1731 Features["sse3"] = (ECX >> 0) & 1; 1732 Features["pclmul"] = (ECX >> 1) & 1; 1733 Features["ssse3"] = (ECX >> 9) & 1; 1734 Features["cx16"] = (ECX >> 13) & 1; 1735 Features["sse4.1"] = (ECX >> 19) & 1; 1736 Features["sse4.2"] = (ECX >> 20) & 1; 1737 Features["crc32"] = Features["sse4.2"]; 1738 Features["movbe"] = (ECX >> 22) & 1; 1739 Features["popcnt"] = (ECX >> 23) & 1; 1740 Features["aes"] = (ECX >> 25) & 1; 1741 Features["rdrnd"] = (ECX >> 30) & 1; 1742 1743 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1744 // indicates that the AVX registers will be saved and restored on context 1745 // switch, then we have full AVX support. 1746 bool HasXSave = ((ECX >> 27) & 1) && !getX86XCR0(&EAX, &EDX); 1747 bool HasAVXSave = HasXSave && ((ECX >> 28) & 1) && ((EAX & 0x6) == 0x6); 1748 #if defined(__APPLE__) 1749 // Darwin lazily saves the AVX512 context on first use: trust that the OS will 1750 // save the AVX512 context if we use AVX512 instructions, even the bit is not 1751 // set right now. 1752 bool HasAVX512Save = true; 1753 #else 1754 // AVX512 requires additional context to be saved by the OS. 1755 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); 1756 #endif 1757 // AMX requires additional context to be saved by the OS. 1758 const unsigned AMXBits = (1 << 17) | (1 << 18); 1759 bool HasAMXSave = HasXSave && ((EAX & AMXBits) == AMXBits); 1760 1761 Features["avx"] = HasAVXSave; 1762 Features["fma"] = ((ECX >> 12) & 1) && HasAVXSave; 1763 // Only enable XSAVE if OS has enabled support for saving YMM state. 1764 Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave; 1765 Features["f16c"] = ((ECX >> 29) & 1) && HasAVXSave; 1766 1767 unsigned MaxExtLevel; 1768 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1769 1770 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1771 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1772 Features["sahf"] = HasExtLeaf1 && ((ECX >> 0) & 1); 1773 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); 1774 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); 1775 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); 1776 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; 1777 Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1); 1778 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; 1779 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); 1780 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); 1781 1782 Features["64bit"] = HasExtLeaf1 && ((EDX >> 29) & 1); 1783 1784 // Miscellaneous memory related features, detected by 1785 // using the 0x80000008 leaf of the CPUID instruction 1786 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 && 1787 !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX); 1788 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1); 1789 Features["rdpru"] = HasExtLeaf8 && ((EBX >> 4) & 1); 1790 Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1); 1791 1792 bool HasLeaf7 = 1793 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1794 1795 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); 1796 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1); 1797 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); 1798 // AVX2 is only supported if we have the OS save support from AVX. 1799 Features["avx2"] = HasLeaf7 && ((EBX >> 5) & 1) && HasAVXSave; 1800 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); 1801 Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1); 1802 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); 1803 // AVX512 is only supported if the OS supports the context save for it. 1804 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; 1805 if (Features["avx512f"]) 1806 Features["evex512"] = true; 1807 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; 1808 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); 1809 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); 1810 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save; 1811 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); 1812 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); 1813 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save; 1814 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); 1815 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save; 1816 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; 1817 1818 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save; 1819 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); 1820 Features["waitpkg"] = HasLeaf7 && ((ECX >> 5) & 1); 1821 Features["avx512vbmi2"] = HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save; 1822 Features["shstk"] = HasLeaf7 && ((ECX >> 7) & 1); 1823 Features["gfni"] = HasLeaf7 && ((ECX >> 8) & 1); 1824 Features["vaes"] = HasLeaf7 && ((ECX >> 9) & 1) && HasAVXSave; 1825 Features["vpclmulqdq"] = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave; 1826 Features["avx512vnni"] = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save; 1827 Features["avx512bitalg"] = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save; 1828 Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save; 1829 Features["rdpid"] = HasLeaf7 && ((ECX >> 22) & 1); 1830 Features["kl"] = HasLeaf7 && ((ECX >> 23) & 1); // key locker 1831 Features["cldemote"] = HasLeaf7 && ((ECX >> 25) & 1); 1832 Features["movdiri"] = HasLeaf7 && ((ECX >> 27) & 1); 1833 Features["movdir64b"] = HasLeaf7 && ((ECX >> 28) & 1); 1834 Features["enqcmd"] = HasLeaf7 && ((ECX >> 29) & 1); 1835 1836 Features["uintr"] = HasLeaf7 && ((EDX >> 5) & 1); 1837 Features["avx512vp2intersect"] = 1838 HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save; 1839 Features["serialize"] = HasLeaf7 && ((EDX >> 14) & 1); 1840 Features["tsxldtrk"] = HasLeaf7 && ((EDX >> 16) & 1); 1841 // There are two CPUID leafs which information associated with the pconfig 1842 // instruction: 1843 // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th 1844 // bit of EDX), while the EAX=0x1b leaf returns information on the 1845 // availability of specific pconfig leafs. 1846 // The target feature here only refers to the the first of these two. 1847 // Users might need to check for the availability of specific pconfig 1848 // leaves using cpuid, since that information is ignored while 1849 // detecting features using the "-march=native" flag. 1850 // For more info, see X86 ISA docs. 1851 Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1); 1852 Features["amx-bf16"] = HasLeaf7 && ((EDX >> 22) & 1) && HasAMXSave; 1853 Features["avx512fp16"] = HasLeaf7 && ((EDX >> 23) & 1) && HasAVX512Save; 1854 Features["amx-tile"] = HasLeaf7 && ((EDX >> 24) & 1) && HasAMXSave; 1855 Features["amx-int8"] = HasLeaf7 && ((EDX >> 25) & 1) && HasAMXSave; 1856 // EAX from subleaf 0 is the maximum subleaf supported. Some CPUs don't 1857 // return all 0s for invalid subleaves so check the limit. 1858 bool HasLeaf7Subleaf1 = 1859 HasLeaf7 && EAX >= 1 && 1860 !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); 1861 Features["sha512"] = HasLeaf7Subleaf1 && ((EAX >> 0) & 1); 1862 Features["sm3"] = HasLeaf7Subleaf1 && ((EAX >> 1) & 1); 1863 Features["sm4"] = HasLeaf7Subleaf1 && ((EAX >> 2) & 1); 1864 Features["raoint"] = HasLeaf7Subleaf1 && ((EAX >> 3) & 1); 1865 Features["avxvnni"] = HasLeaf7Subleaf1 && ((EAX >> 4) & 1) && HasAVXSave; 1866 Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save; 1867 Features["amx-fp16"] = HasLeaf7Subleaf1 && ((EAX >> 21) & 1) && HasAMXSave; 1868 Features["cmpccxadd"] = HasLeaf7Subleaf1 && ((EAX >> 7) & 1); 1869 Features["hreset"] = HasLeaf7Subleaf1 && ((EAX >> 22) & 1); 1870 Features["avxifma"] = HasLeaf7Subleaf1 && ((EAX >> 23) & 1) && HasAVXSave; 1871 Features["avxvnniint8"] = HasLeaf7Subleaf1 && ((EDX >> 4) & 1) && HasAVXSave; 1872 Features["avxneconvert"] = HasLeaf7Subleaf1 && ((EDX >> 5) & 1) && HasAVXSave; 1873 Features["amx-complex"] = HasLeaf7Subleaf1 && ((EDX >> 8) & 1) && HasAMXSave; 1874 Features["avxvnniint16"] = HasLeaf7Subleaf1 && ((EDX >> 10) & 1) && HasAVXSave; 1875 Features["prefetchi"] = HasLeaf7Subleaf1 && ((EDX >> 14) & 1); 1876 Features["usermsr"] = HasLeaf7Subleaf1 && ((EDX >> 15) & 1); 1877 Features["avx10.1-256"] = HasLeaf7Subleaf1 && ((EDX >> 19) & 1); 1878 bool HasAPXF = HasLeaf7Subleaf1 && ((EDX >> 21) & 1); 1879 Features["egpr"] = HasAPXF; 1880 Features["push2pop2"] = HasAPXF; 1881 Features["ppx"] = HasAPXF; 1882 Features["ndd"] = HasAPXF; 1883 Features["ccmp"] = HasAPXF; 1884 Features["cf"] = HasAPXF; 1885 1886 bool HasLeafD = MaxLevel >= 0xd && 1887 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); 1888 1889 // Only enable XSAVE if OS has enabled support for saving YMM state. 1890 Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave; 1891 Features["xsavec"] = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave; 1892 Features["xsaves"] = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave; 1893 1894 bool HasLeaf14 = MaxLevel >= 0x14 && 1895 !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX); 1896 1897 Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1); 1898 1899 bool HasLeaf19 = 1900 MaxLevel >= 0x19 && !getX86CpuIDAndInfo(0x19, &EAX, &EBX, &ECX, &EDX); 1901 Features["widekl"] = HasLeaf7 && HasLeaf19 && ((EBX >> 2) & 1); 1902 1903 bool HasLeaf24 = 1904 MaxLevel >= 0x24 && !getX86CpuIDAndInfo(0x24, &EAX, &EBX, &ECX, &EDX); 1905 Features["avx10.1-512"] = 1906 Features["avx10.1-256"] && HasLeaf24 && ((EBX >> 18) & 1); 1907 1908 return Features; 1909 } 1910 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1911 const StringMap<bool> sys::getHostCPUFeatures() { 1912 StringMap<bool> Features; 1913 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1914 if (!P) 1915 return Features; 1916 1917 SmallVector<StringRef, 32> Lines; 1918 P->getBuffer().split(Lines, "\n"); 1919 1920 SmallVector<StringRef, 32> CPUFeatures; 1921 1922 // Look for the CPU features. 1923 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1924 if (Lines[I].starts_with("Features")) { 1925 Lines[I].split(CPUFeatures, ' '); 1926 break; 1927 } 1928 1929 #if defined(__aarch64__) 1930 // Keep track of which crypto features we have seen 1931 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 }; 1932 uint32_t crypto = 0; 1933 #endif 1934 1935 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 1936 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I]) 1937 #if defined(__aarch64__) 1938 .Case("asimd", "neon") 1939 .Case("fp", "fp-armv8") 1940 .Case("crc32", "crc") 1941 .Case("atomics", "lse") 1942 .Case("sve", "sve") 1943 .Case("sve2", "sve2") 1944 #else 1945 .Case("half", "fp16") 1946 .Case("neon", "neon") 1947 .Case("vfpv3", "vfp3") 1948 .Case("vfpv3d16", "vfp3d16") 1949 .Case("vfpv4", "vfp4") 1950 .Case("idiva", "hwdiv-arm") 1951 .Case("idivt", "hwdiv") 1952 #endif 1953 .Default(""); 1954 1955 #if defined(__aarch64__) 1956 // We need to check crypto separately since we need all of the crypto 1957 // extensions to enable the subtarget feature 1958 if (CPUFeatures[I] == "aes") 1959 crypto |= CAP_AES; 1960 else if (CPUFeatures[I] == "pmull") 1961 crypto |= CAP_PMULL; 1962 else if (CPUFeatures[I] == "sha1") 1963 crypto |= CAP_SHA1; 1964 else if (CPUFeatures[I] == "sha2") 1965 crypto |= CAP_SHA2; 1966 #endif 1967 1968 if (LLVMFeatureStr != "") 1969 Features[LLVMFeatureStr] = true; 1970 } 1971 1972 #if defined(__aarch64__) 1973 // If we have all crypto bits we can add the feature 1974 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2)) 1975 Features["crypto"] = true; 1976 #endif 1977 1978 return Features; 1979 } 1980 #elif defined(_WIN32) && (defined(__aarch64__) || defined(_M_ARM64)) 1981 const StringMap<bool> sys::getHostCPUFeatures() { 1982 StringMap<bool> Features; 1983 1984 if (IsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE)) 1985 Features["neon"] = true; 1986 if (IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE)) 1987 Features["crc"] = true; 1988 if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE)) 1989 Features["crypto"] = true; 1990 1991 return Features; 1992 } 1993 #elif defined(__linux__) && defined(__loongarch__) 1994 #include <sys/auxv.h> 1995 const StringMap<bool> sys::getHostCPUFeatures() { 1996 unsigned long hwcap = getauxval(AT_HWCAP); 1997 bool HasFPU = hwcap & (1UL << 3); // HWCAP_LOONGARCH_FPU 1998 uint32_t cpucfg2 = 0x2; 1999 __asm__("cpucfg %[cpucfg2], %[cpucfg2]\n\t" : [cpucfg2] "+r"(cpucfg2)); 2000 2001 StringMap<bool> Features; 2002 2003 Features["f"] = HasFPU && (cpucfg2 & (1U << 1)); // CPUCFG.2.FP_SP 2004 Features["d"] = HasFPU && (cpucfg2 & (1U << 2)); // CPUCFG.2.FP_DP 2005 2006 Features["lsx"] = hwcap & (1UL << 4); // HWCAP_LOONGARCH_LSX 2007 Features["lasx"] = hwcap & (1UL << 5); // HWCAP_LOONGARCH_LASX 2008 Features["lvz"] = hwcap & (1UL << 9); // HWCAP_LOONGARCH_LVZ 2009 2010 return Features; 2011 } 2012 #elif defined(__linux__) && defined(__riscv) 2013 // struct riscv_hwprobe 2014 struct RISCVHwProbe { 2015 int64_t Key; 2016 uint64_t Value; 2017 }; 2018 const StringMap<bool> sys::getHostCPUFeatures() { 2019 RISCVHwProbe Query[]{{/*RISCV_HWPROBE_KEY_BASE_BEHAVIOR=*/3, 0}, 2020 {/*RISCV_HWPROBE_KEY_IMA_EXT_0=*/4, 0}}; 2021 int Ret = syscall(/*__NR_riscv_hwprobe=*/258, /*pairs=*/Query, 2022 /*pair_count=*/std::size(Query), /*cpu_count=*/0, 2023 /*cpus=*/0, /*flags=*/0); 2024 if (Ret != 0) 2025 return {}; 2026 2027 StringMap<bool> Features; 2028 uint64_t BaseMask = Query[0].Value; 2029 // Check whether RISCV_HWPROBE_BASE_BEHAVIOR_IMA is set. 2030 if (BaseMask & 1) { 2031 Features["i"] = true; 2032 Features["m"] = true; 2033 Features["a"] = true; 2034 } 2035 2036 uint64_t ExtMask = Query[1].Value; 2037 Features["f"] = ExtMask & (1 << 0); // RISCV_HWPROBE_IMA_FD 2038 Features["d"] = ExtMask & (1 << 0); // RISCV_HWPROBE_IMA_FD 2039 Features["c"] = ExtMask & (1 << 1); // RISCV_HWPROBE_IMA_C 2040 Features["v"] = ExtMask & (1 << 2); // RISCV_HWPROBE_IMA_V 2041 Features["zba"] = ExtMask & (1 << 3); // RISCV_HWPROBE_EXT_ZBA 2042 Features["zbb"] = ExtMask & (1 << 4); // RISCV_HWPROBE_EXT_ZBB 2043 Features["zbs"] = ExtMask & (1 << 5); // RISCV_HWPROBE_EXT_ZBS 2044 Features["zicboz"] = ExtMask & (1 << 6); // RISCV_HWPROBE_EXT_ZICBOZ 2045 Features["zbc"] = ExtMask & (1 << 7); // RISCV_HWPROBE_EXT_ZBC 2046 Features["zbkb"] = ExtMask & (1 << 8); // RISCV_HWPROBE_EXT_ZBKB 2047 Features["zbkc"] = ExtMask & (1 << 9); // RISCV_HWPROBE_EXT_ZBKC 2048 Features["zbkx"] = ExtMask & (1 << 10); // RISCV_HWPROBE_EXT_ZBKX 2049 Features["zknd"] = ExtMask & (1 << 11); // RISCV_HWPROBE_EXT_ZKND 2050 Features["zkne"] = ExtMask & (1 << 12); // RISCV_HWPROBE_EXT_ZKNE 2051 Features["zknh"] = ExtMask & (1 << 13); // RISCV_HWPROBE_EXT_ZKNH 2052 Features["zksed"] = ExtMask & (1 << 14); // RISCV_HWPROBE_EXT_ZKSED 2053 Features["zksh"] = ExtMask & (1 << 15); // RISCV_HWPROBE_EXT_ZKSH 2054 Features["zkt"] = ExtMask & (1 << 16); // RISCV_HWPROBE_EXT_ZKT 2055 Features["zvbb"] = ExtMask & (1 << 17); // RISCV_HWPROBE_EXT_ZVBB 2056 Features["zvbc"] = ExtMask & (1 << 18); // RISCV_HWPROBE_EXT_ZVBC 2057 Features["zvkb"] = ExtMask & (1 << 19); // RISCV_HWPROBE_EXT_ZVKB 2058 Features["zvkg"] = ExtMask & (1 << 20); // RISCV_HWPROBE_EXT_ZVKG 2059 Features["zvkned"] = ExtMask & (1 << 21); // RISCV_HWPROBE_EXT_ZVKNED 2060 Features["zvknha"] = ExtMask & (1 << 22); // RISCV_HWPROBE_EXT_ZVKNHA 2061 Features["zvknhb"] = ExtMask & (1 << 23); // RISCV_HWPROBE_EXT_ZVKNHB 2062 Features["zvksed"] = ExtMask & (1 << 24); // RISCV_HWPROBE_EXT_ZVKSED 2063 Features["zvksh"] = ExtMask & (1 << 25); // RISCV_HWPROBE_EXT_ZVKSH 2064 Features["zvkt"] = ExtMask & (1 << 26); // RISCV_HWPROBE_EXT_ZVKT 2065 Features["zfh"] = ExtMask & (1 << 27); // RISCV_HWPROBE_EXT_ZFH 2066 Features["zfhmin"] = ExtMask & (1 << 28); // RISCV_HWPROBE_EXT_ZFHMIN 2067 Features["zihintntl"] = ExtMask & (1 << 29); // RISCV_HWPROBE_EXT_ZIHINTNTL 2068 Features["zvfh"] = ExtMask & (1 << 30); // RISCV_HWPROBE_EXT_ZVFH 2069 Features["zvfhmin"] = ExtMask & (1ULL << 31); // RISCV_HWPROBE_EXT_ZVFHMIN 2070 Features["zfa"] = ExtMask & (1ULL << 32); // RISCV_HWPROBE_EXT_ZFA 2071 Features["ztso"] = ExtMask & (1ULL << 33); // RISCV_HWPROBE_EXT_ZTSO 2072 // TODO: Re-enable zacas when it is marked non-experimental again. 2073 // Features["zacas"] = ExtMask & (1ULL << 34); // RISCV_HWPROBE_EXT_ZACAS 2074 Features["zicond"] = ExtMask & (1ULL << 35); // RISCV_HWPROBE_EXT_ZICOND 2075 Features["zihintpause"] = 2076 ExtMask & (1ULL << 36); // RISCV_HWPROBE_EXT_ZIHINTPAUSE 2077 2078 // TODO: set unaligned-scalar-mem if RISCV_HWPROBE_KEY_MISALIGNED_PERF returns 2079 // RISCV_HWPROBE_MISALIGNED_FAST. 2080 2081 return Features; 2082 } 2083 #else 2084 const StringMap<bool> sys::getHostCPUFeatures() { return {}; } 2085 #endif 2086 2087 #if __APPLE__ 2088 /// \returns the \p triple, but with the Host's arch spliced in. 2089 static Triple withHostArch(Triple T) { 2090 #if defined(__arm__) 2091 T.setArch(Triple::arm); 2092 T.setArchName("arm"); 2093 #elif defined(__arm64e__) 2094 T.setArch(Triple::aarch64, Triple::AArch64SubArch_arm64e); 2095 T.setArchName("arm64e"); 2096 #elif defined(__aarch64__) 2097 T.setArch(Triple::aarch64); 2098 T.setArchName("arm64"); 2099 #elif defined(__x86_64h__) 2100 T.setArch(Triple::x86_64); 2101 T.setArchName("x86_64h"); 2102 #elif defined(__x86_64__) 2103 T.setArch(Triple::x86_64); 2104 T.setArchName("x86_64"); 2105 #elif defined(__i386__) 2106 T.setArch(Triple::x86); 2107 T.setArchName("i386"); 2108 #elif defined(__powerpc__) 2109 T.setArch(Triple::ppc); 2110 T.setArchName("powerpc"); 2111 #else 2112 # error "Unimplemented host arch fixup" 2113 #endif 2114 return T; 2115 } 2116 #endif 2117 2118 std::string sys::getProcessTriple() { 2119 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE); 2120 Triple PT(Triple::normalize(TargetTripleString)); 2121 2122 #if __APPLE__ 2123 /// In Universal builds, LLVM_HOST_TRIPLE will have the wrong arch in one of 2124 /// the slices. This fixes that up. 2125 PT = withHostArch(PT); 2126 #endif 2127 2128 if (sizeof(void *) == 8 && PT.isArch32Bit()) 2129 PT = PT.get64BitArchVariant(); 2130 if (sizeof(void *) == 4 && PT.isArch64Bit()) 2131 PT = PT.get32BitArchVariant(); 2132 2133 return PT.str(); 2134 } 2135 2136 void sys::printDefaultTargetAndDetectedCPU(raw_ostream &OS) { 2137 #if LLVM_VERSION_PRINTER_SHOW_HOST_TARGET_INFO 2138 std::string CPU = std::string(sys::getHostCPUName()); 2139 if (CPU == "generic") 2140 CPU = "(unknown)"; 2141 OS << " Default target: " << sys::getDefaultTargetTriple() << '\n' 2142 << " Host CPU: " << CPU << '\n'; 2143 #endif 2144 } 2145