xref: /src/contrib/llvm-project/llvm/lib/Target/VE/VEInstrPatternsVec.td (revision 753f127f3ace09432b2baeffd71a308760641a62) 
1//===-- VEInstrPatternsVec.td - VEC_-type SDNodes and isel for VE Target --===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes the VEC_* prefixed intermediate SDNodes and their
10// isel patterns.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// Instruction format superclass
16//===----------------------------------------------------------------------===//
17
18// Sub-register replication for packed broadcast.
19def: Pat<(i64 (repl_f32 f32:$val)),
20            (ORrr
21              (SRLri (f2l $val), 32),
22              (zero_i32 (f2l $val)))>;
23def: Pat<(i64 (repl_i32 i32:$val)),
24            (ORrr
25              (zero_f32 (i2l $val)),
26              (SLLri (i2l $val), 32))>;
27
28
29multiclass vbrd_elem32<ValueType v32, ValueType s32, SDPatternOperator ImmOp,
30                       SDNodeXForm ImmCast, OutPatFrag SuperRegCast> {
31  // VBRDil
32  def : Pat<(v32 (vec_broadcast (s32 ImmOp:$sy), i32:$vl)),
33            (VBRDil (ImmCast $sy), i32:$vl)>;
34
35  // VBRDrl
36  def : Pat<(v32 (vec_broadcast s32:$sy, i32:$vl)),
37            (VBRDrl (SuperRegCast $sy), i32:$vl)>;
38}
39
40multiclass vbrd_elem64<ValueType v64, ValueType s64,
41                       SDPatternOperator ImmOp, SDNodeXForm ImmCast> {
42  // VBRDil
43  def : Pat<(v64 (vec_broadcast (s64 ImmOp:$sy), i32:$vl)),
44            (VBRDil (ImmCast $sy), i32:$vl)>;
45
46  // VBRDrl
47  def : Pat<(v64 (vec_broadcast s64:$sy, i32:$vl)),
48            (VBRDrl s64:$sy, i32:$vl)>;
49}
50
51multiclass extract_insert_elem32<ValueType v32, ValueType s32,
52                                 OutPatFrag SubRegCast,
53                                 OutPatFrag SuperRegCast> {
54  // LVSvi
55  def: Pat<(s32 (extractelt v32:$vec, uimm7:$idx)),
56           (SubRegCast (LVSvi v32:$vec, (ULO7 $idx)))>;
57  // LVSvr
58  def: Pat<(s32 (extractelt v32:$vec, i64:$idx)),
59           (SubRegCast (LVSvr v32:$vec, $idx))>;
60
61  // LSVir
62  def: Pat<(v32 (insertelt v32:$vec, s32:$val, uimm7:$idx)),
63           (LSVir_v (ULO7 $idx), (SuperRegCast $val), $vec)>;
64  // LSVrr
65  def: Pat<(v32 (insertelt v32:$vec, s32:$val, i64:$idx)),
66           (LSVrr_v $idx, (SuperRegCast $val), $vec)>;
67}
68
69multiclass extract_insert_elem64<ValueType v64, ValueType s64> {
70  // LVSvi
71  def: Pat<(s64 (extractelt v64:$vec, uimm7:$idx)),
72           (LVSvi v64:$vec, (ULO7 $idx))>;
73  // LVSvr
74  def: Pat<(s64 (extractelt v64:$vec, i64:$idx)),
75           (LVSvr v64:$vec, $idx)>;
76
77  // LSVir
78  def: Pat<(v64 (insertelt v64:$vec, s64:$val, uimm7:$idx)),
79           (LSVir_v (ULO7 $idx), $val, $vec)>;
80  // LSVrr
81  def: Pat<(v64 (insertelt v64:$vec, s64:$val, i64:$idx)),
82           (LSVrr_v $idx, $val, $vec)>;
83}
84
85multiclass patterns_elem32<ValueType v32, ValueType s32,
86                           SDPatternOperator ImmOp, SDNodeXForm ImmCast,
87                           OutPatFrag SubRegCast, OutPatFrag SuperRegCast> {
88  defm : vbrd_elem32<v32, s32, ImmOp, ImmCast, SuperRegCast>;
89  defm : extract_insert_elem32<v32, s32, SubRegCast, SuperRegCast>;
90}
91
92multiclass patterns_elem64<ValueType v64, ValueType s64,
93                           SDPatternOperator ImmOp, SDNodeXForm ImmCast> {
94  defm : vbrd_elem64<v64, s64, ImmOp, ImmCast>;
95  defm : extract_insert_elem64<v64, s64>;
96}
97
98defm : patterns_elem32<v256i32, i32, simm7, LO7, l2i, i2l>;
99defm : patterns_elem32<v256f32, f32, simm7fp, LO7FP, l2f, f2l>;
100
101defm : patterns_elem64<v256i64, i64, simm7, LO7>;
102defm : patterns_elem64<v256f64, f64, simm7fp, LO7FP>;
103
104defm : vbrd_elem64<v512i32, i64, simm7, LO7>;
105defm : vbrd_elem64<v512f32, i64, simm7, LO7>;
106defm : vbrd_elem64<v512i32, f64, simm7fp, LO7FP>;
107defm : vbrd_elem64<v512f32, f64, simm7fp, LO7FP>;
108
109class Mask_Binary<ValueType MaskVT, SDPatternOperator MaskOp, string InstName> :
110  Pat<(MaskVT (MaskOp MaskVT:$ma, MaskVT:$mb)), (!cast<Instruction>(InstName#"mm") $ma, $mb)>;
111
112def: Mask_Binary<v256i1, and, "ANDM">;
113def: Mask_Binary<v256i1, or,  "ORM">;
114def: Mask_Binary<v256i1, xor, "XORM">;
115
116///// Packing support /////
117
118// v256i1 <> v512i1
119def : Pat<(v256i1 (vec_unpack_lo v512i1:$vm, (i32 srcvalue))),
120          (EXTRACT_SUBREG $vm, sub_vm_odd)>;
121def : Pat<(v256i1 (vec_unpack_hi v512i1:$vm, (i32 srcvalue))),
122          (EXTRACT_SUBREG $vm, sub_vm_even)>;
123def : Pat<(v512i1 (vec_pack v256i1:$vlo, v256i1:$vhi, (i32 srcvalue))),
124          (INSERT_SUBREG (INSERT_SUBREG
125                         (v512i1 (IMPLICIT_DEF)),
126                         $vlo, sub_vm_odd),
127                         $vhi, sub_vm_even)>;
128
129// v256.32 <> v512.32
130multiclass Packing<ValueType PackVT> {
131  // no-op unpacks
132  def : Pat<(v256i32 (vec_unpack_lo PackVT:$vp, (i32 srcvalue))),
133            (COPY_TO_REGCLASS $vp, V64)>;
134  def : Pat<(v256f32 (vec_unpack_hi PackVT:$vp, (i32 srcvalue))),
135            (COPY_TO_REGCLASS $vp, V64)>;
136
137  // shuffle unpacks
138  def : Pat<(v256f32 (vec_unpack_lo PackVT:$vp, i32:$avl)),
139            (VSHFvvil $vp, $vp, 4, $avl)>; // always pick lo
140  def : Pat<(v256i32 (vec_unpack_hi PackVT:$vp, i32:$avl)),
141            (VSHFvvil $vp, $vp, 0, $avl)>; // always pick hi
142}
143
144defm : Packing<v512i32>;
145defm : Packing<v512f32>;
146
147def : Pat<(v512i32 (vec_pack v256i32:$vlo, v256i32:$vhi, i32:$avl)),
148          (VSHFvvil $vlo, $vhi, 13, $avl)>;
149def : Pat<(v512f32 (vec_pack v256f32:$vlo, v256f32:$vhi, i32:$avl)),
150          (VSHFvvil $vlo, $vhi, 8, $avl)>;
151