1//=- Mips64r6InstrInfo.td - Mips64r6 Instruction Information -*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes Mips64r6 instructions. 10// 11//===----------------------------------------------------------------------===// 12 13// Notes about removals/changes from MIPS32r6: 14// Reencoded: dclo, dclz 15 16//===----------------------------------------------------------------------===// 17// 18// Instruction Encodings 19// 20//===----------------------------------------------------------------------===// 21 22class DALIGN_ENC : SPECIAL3_DALIGN_FM<OPCODE6_DALIGN>; 23class DAUI_ENC : DAUI_FM; 24class DAHI_ENC : REGIMM_FM<OPCODE5_DAHI>; 25class DATI_ENC : REGIMM_FM<OPCODE5_DATI>; 26class DBITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_DBITSWAP>; 27class DCLO_R6_ENC : SPECIAL_2R_FM<OPCODE6_DCLO>; 28class DCLZ_R6_ENC : SPECIAL_2R_FM<OPCODE6_DCLZ>; 29class DDIV_ENC : SPECIAL_3R_FM<0b00010, 0b011110>; 30class DDIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011111>; 31class DLSA_R6_ENC : SPECIAL_LSA_FM<OPCODE6_DLSA>; 32class DMOD_ENC : SPECIAL_3R_FM<0b00011, 0b011110>; 33class DMODU_ENC : SPECIAL_3R_FM<0b00011, 0b011111>; 34class DMUH_ENC : SPECIAL_3R_FM<0b00011, 0b011100>; 35class DMUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011101>; 36class DMUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011100>; 37class DMULU_ENC : SPECIAL_3R_FM<0b00010, 0b011101>; 38class LDPC_ENC : PCREL18_FM<OPCODE3_LDPC>; 39class LWUPC_ENC : PCREL19_FM<OPCODE2_LWUPC>; 40class LLD_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_LLD>; 41class SCD_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_SCD>; 42class CRC32D_ENC : SPECIAL3_2R_SZ_CRC<3,0>; 43class CRC32CD_ENC : SPECIAL3_2R_SZ_CRC<3,1>; 44 45//===----------------------------------------------------------------------===// 46// 47// Instruction Descriptions 48// 49//===----------------------------------------------------------------------===// 50 51class AHI_ATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, InstrItinClass itin> { 52 dag OutOperandList = (outs GPROpnd:$rs); 53 dag InOperandList = (ins GPROpnd:$rt, uimm16_altrelaxed:$imm); 54 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm"); 55 string Constraints = "$rs = $rt"; 56 InstrItinClass Itinerary = itin; 57} 58 59class DALIGN_DESC : ALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3, II_DALIGN>; 60class DAHI_DESC : AHI_ATI_DESC_BASE<"dahi", GPR64Opnd, II_DAHI>; 61class DATI_DESC : AHI_ATI_DESC_BASE<"dati", GPR64Opnd, II_DATI>; 62class DAUI_DESC : AUI_DESC_BASE<"daui", GPR64Opnd, II_DAUI>; 63class DBITSWAP_DESC : BITSWAP_DESC_BASE<"dbitswap", GPR64Opnd, II_DBITSWAP>; 64class DCLO_R6_DESC : CLO_R6_DESC_BASE<"dclo", GPR64Opnd, II_DCLO>; 65class DCLZ_R6_DESC : CLZ_R6_DESC_BASE<"dclz", GPR64Opnd, II_DCLZ>; 66class DDIV_DESC : DIVMOD_DESC_BASE<"ddiv", GPR64Opnd, II_DDIV, sdiv>; 67class DDIVU_DESC : DIVMOD_DESC_BASE<"ddivu", GPR64Opnd, II_DDIVU, udiv>; 68class DLSA_R6_DESC : LSA_R6_DESC_BASE<"dlsa", GPR64Opnd, uimm2_plus1, II_DLSA>; 69class DMOD_DESC : DIVMOD_DESC_BASE<"dmod", GPR64Opnd, II_DMOD, srem>; 70class DMODU_DESC : DIVMOD_DESC_BASE<"dmodu", GPR64Opnd, II_DMODU, urem>; 71class DMUH_DESC : MUL_R6_DESC_BASE<"dmuh", GPR64Opnd, II_DMUH, mulhs>; 72class DMUHU_DESC : MUL_R6_DESC_BASE<"dmuhu", GPR64Opnd, II_DMUHU, mulhu>; 73class DMUL_R6_DESC : MUL_R6_DESC_BASE<"dmul", GPR64Opnd, II_DMUL, mul>; 74class DMULU_DESC : MUL_R6_DESC_BASE<"dmulu", GPR64Opnd, II_DMUL>; 75class LDPC_DESC : PCREL_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3, II_LDPC>; 76class LWUPC_DESC : PCREL_DESC_BASE<"lwupc", GPR32Opnd, simm19_lsl2, II_LWUPC>; 77class LLD_R6_DESC : LL_R6_DESC_BASE<"lld", GPR64Opnd, mem_simmptr, II_LLD>; 78class SCD_R6_DESC : SC_R6_DESC_BASE<"scd", GPR64Opnd, II_SCD>; 79class SELEQZ64_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR64Opnd>; 80class SELNEZ64_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR64Opnd>; 81 82class BGEC64_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR64Opnd>; 83class BGEUC64_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR64Opnd>; 84class BEQC64_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR64Opnd>; 85class BNEC64_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR64Opnd>; 86class BLTC64_DESC : CMP_BC_DESC_BASE<"bltc", brtarget, GPR64Opnd>; 87class BLTUC64_DESC : CMP_BC_DESC_BASE<"bltuc", brtarget, GPR64Opnd>; 88class BLTZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR64Opnd>; 89class BGEZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR64Opnd>; 90class BLEZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR64Opnd>; 91class BGTZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR64Opnd>; 92class BEQZC64_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR64Opnd>; 93class BNEZC64_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR64Opnd>; 94 95class JIALC64_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16, 96 GPR64Opnd, II_JIALC> { 97 bit isCall = 1; 98 list<Register> Defs = [RA]; 99} 100 101class JIC64_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR64Opnd, 102 II_JIC> { 103 bit isBarrier = 1; 104 bit isTerminator = 1; 105 list<Register> Defs = [AT]; 106} 107 108class LL64_R6_DESC : LL_R6_DESC_BASE<"ll", GPR32Opnd, mem_simm9, II_LL>; 109class SC64_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd, II_SC>; 110 111class JR_HB64_R6_DESC : JR_HB_DESC_BASE<"jr.hb", GPR64Opnd> { 112 bit isBranch = 1; 113 bit isIndirectBranch = 1; 114 bit hasDelaySlot = 1; 115 bit isTerminator=1; 116 bit isBarrier=1; 117 bit isCTI = 1; 118 InstrItinClass Itinerary = II_JR_HB; 119} 120 121class CRC32D_DESC : CRC_DESC_BASE<"crc32d", GPR32Opnd, II_CRC32D>; 122class CRC32CD_DESC : CRC_DESC_BASE<"crc32cd", GPR32Opnd, II_CRC32CD>; 123 124//===----------------------------------------------------------------------===// 125// 126// Instruction Definitions 127// 128//===----------------------------------------------------------------------===// 129 130let AdditionalPredicates = [NotInMicroMips] in { 131 let DecoderMethod = "DecodeDAHIDATI" in { 132 def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6; 133 def DAHI : DAHI_ENC, DAHI_DESC, ISA_MIPS64R6; 134 } 135 def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6; 136 def DALIGN : DALIGN_ENC, DALIGN_DESC, ISA_MIPS64R6; 137 def DBITSWAP : DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6; 138 def DCLO_R6 : DCLO_R6_ENC, DCLO_R6_DESC, ISA_MIPS64R6; 139 def DCLZ_R6 : DCLZ_R6_ENC, DCLZ_R6_DESC, ISA_MIPS64R6; 140 def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6; 141 def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6; 142 def DMOD : DMOD_ENC, DMOD_DESC, ISA_MIPS64R6; 143 def DMODU : DMODU_ENC, DMODU_DESC, ISA_MIPS64R6; 144 def DLSA_R6 : DLSA_R6_ENC, DLSA_R6_DESC, ISA_MIPS64R6; 145 def DMUH: DMUH_ENC, DMUH_DESC, ISA_MIPS64R6; 146 def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6; 147 def DMUL_R6: DMUL_R6_ENC, DMUL_R6_DESC, ISA_MIPS64R6; 148 def DMULU: DMULU_ENC, DMULU_DESC, ISA_MIPS64R6; 149 def LLD_R6 : LLD_R6_ENC, LLD_R6_DESC, ISA_MIPS64R6; 150} 151def LDPC: LDPC_ENC, LDPC_DESC, ISA_MIPS64R6; 152def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS64R6; 153def SCD_R6 : SCD_R6_ENC, SCD_R6_DESC, ISA_MIPS32R6; 154let DecoderNamespace = "Mips32r6_64r6_GP64" in { 155 def SELEQZ64 : SELEQZ_ENC, SELEQZ64_DESC, ISA_MIPS32R6, GPR_64; 156 def SELNEZ64 : SELNEZ_ENC, SELNEZ64_DESC, ISA_MIPS32R6, GPR_64; 157 def JR_HB64_R6 : JR_HB_R6_ENC, JR_HB64_R6_DESC, ISA_MIPS32R6; 158} 159let AdditionalPredicates = [NotInMicroMips], 160 DecoderNamespace = "Mips32r6_64r6_PTR64" in { 161 def LL64_R6 : LL_R6_ENC, LL64_R6_DESC, PTR_64, ISA_MIPS64R6; 162 def SC64_R6 : SC_R6_ENC, SC64_R6_DESC, PTR_64, ISA_MIPS64R6; 163} 164 165let DecoderNamespace = "Mips32r6_64r6_GP64" in { 166// Jump and Branch Instructions 167def JIALC64 : JIALC_ENC, JIALC64_DESC, ISA_MIPS64R6, GPR_64; 168def JIC64 : JIC_ENC, JIC64_DESC, ISA_MIPS64R6, GPR_64; 169 170def BEQC64 : BEQC_ENC, BEQC64_DESC, ISA_MIPS64R6, GPR_64; 171def BEQZC64 : BEQZC_ENC, BEQZC64_DESC, ISA_MIPS64R6, GPR_64; 172def BGEC64 : BGEC_ENC, BGEC64_DESC, ISA_MIPS64R6, GPR_64; 173def BGEUC64 : BGEUC_ENC, BGEUC64_DESC, ISA_MIPS64R6, GPR_64; 174def BGTZC64 : BGTZC_ENC, BGTZC64_DESC, ISA_MIPS64R6, GPR_64; 175def BLEZC64 : BLEZC_ENC, BLEZC64_DESC, ISA_MIPS64R6, GPR_64; 176def BLTC64 : BLTC_ENC, BLTC64_DESC, ISA_MIPS64R6, GPR_64; 177def BLTUC64 : BLTUC_ENC, BLTUC64_DESC, ISA_MIPS64R6, GPR_64; 178def BNEC64 : BNEC_ENC, BNEC64_DESC, ISA_MIPS64R6, GPR_64; 179def BNEZC64 : BNEZC_ENC, BNEZC64_DESC, ISA_MIPS64R6, GPR_64; 180} 181let DecoderNamespace = "Mips32r6_64r6_BranchZero" in { 182def BLTZC64 : BLTZC_ENC, BLTZC64_DESC, ISA_MIPS64R6, GPR_64; 183def BGEZC64 : BGEZC_ENC, BGEZC64_DESC, ISA_MIPS64R6, GPR_64; 184} 185let AdditionalPredicates = [NotInMicroMips] in { 186 def CRC32D : R6MMR6Rel, CRC32D_ENC, CRC32D_DESC, ISA_MIPS64R6, ASE_CRC; 187 def CRC32CD : R6MMR6Rel, CRC32CD_ENC, CRC32CD_DESC, ISA_MIPS64R6, ASE_CRC; 188} 189 190//===----------------------------------------------------------------------===// 191// 192// Instruction Aliases 193// 194//===----------------------------------------------------------------------===// 195 196def : MipsInstAlias<"jr $rs", (JALR64 ZERO_64, GPR64Opnd:$rs), 1>, ISA_MIPS64R6; 197 198def : MipsInstAlias<"jrc $rs", (JIC64 GPR64Opnd:$rs, 0), 1>, ISA_MIPS64R6; 199 200def : MipsInstAlias<"jalrc $rs", (JIALC64 GPR64Opnd:$rs, 0), 1>, ISA_MIPS64R6; 201//===----------------------------------------------------------------------===// 202// 203// Patterns and Pseudo Instructions 204// 205//===----------------------------------------------------------------------===// 206 207// i64 selects 208def : MipsPat<(select i64:$cond, i64:$t, i64:$f), 209 (OR64 (SELNEZ64 i64:$t, i64:$cond), 210 (SELEQZ64 i64:$f, i64:$cond))>, 211 ISA_MIPS64R6; 212def : MipsPat<(select (i32 (seteq i64:$cond, immz)), i64:$t, i64:$f), 213 (OR64 (SELEQZ64 i64:$t, i64:$cond), 214 (SELNEZ64 i64:$f, i64:$cond))>, 215 ISA_MIPS64R6; 216def : MipsPat<(select (i32 (setne i64:$cond, immz)), i64:$t, i64:$f), 217 (OR64 (SELNEZ64 i64:$t, i64:$cond), 218 (SELEQZ64 i64:$f, i64:$cond))>, 219 ISA_MIPS64R6; 220def : MipsPat<(select (i32 (seteq i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f), 221 (OR64 (SELEQZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)), 222 (SELNEZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)))>, 223 ISA_MIPS64R6; 224def : MipsPat<(select (i32 (setne i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f), 225 (OR64 (SELNEZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)), 226 (SELEQZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)))>, 227 ISA_MIPS64R6; 228def : MipsPat< 229 (select (i32 (setgt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f), 230 (OR64 (SELEQZ64 i64:$t, 231 (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)), 232 sub_32)), 233 (SELNEZ64 i64:$f, 234 (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)), 235 sub_32)))>, 236 ISA_MIPS64R6; 237def : MipsPat< 238 (select (i32 (setugt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f), 239 (OR64 (SELEQZ64 i64:$t, 240 (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)), 241 sub_32)), 242 (SELNEZ64 i64:$f, 243 (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)), 244 sub_32)))>, 245 ISA_MIPS64R6; 246 247def : MipsPat<(select (i32 (setne i64:$cond, immz)), i64:$t, immz), 248 (SELNEZ64 i64:$t, i64:$cond)>, ISA_MIPS64R6; 249def : MipsPat<(select (i32 (seteq i64:$cond, immz)), i64:$t, immz), 250 (SELEQZ64 i64:$t, i64:$cond)>, ISA_MIPS64R6; 251def : MipsPat<(select (i32 (setne i64:$cond, immz)), immz, i64:$f), 252 (SELEQZ64 i64:$f, i64:$cond)>, ISA_MIPS64R6; 253def : MipsPat<(select (i32 (seteq i64:$cond, immz)), immz, i64:$f), 254 (SELNEZ64 i64:$f, i64:$cond)>, ISA_MIPS64R6; 255 256// i64 selects from an i32 comparison 257// One complicating factor here is that bits 32-63 of an i32 are undefined. 258// FIXME: Ideally, setcc would always produce an i64 on MIPS64 targets. 259// This would allow us to remove the sign-extensions here. 260def : MipsPat<(select i32:$cond, i64:$t, i64:$f), 261 (OR64 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond)), 262 (SELEQZ64 i64:$f, (SLL64_32 i32:$cond)))>, 263 ISA_MIPS64R6; 264def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i64:$t, i64:$f), 265 (OR64 (SELEQZ64 i64:$t, (SLL64_32 i32:$cond)), 266 (SELNEZ64 i64:$f, (SLL64_32 i32:$cond)))>, 267 ISA_MIPS64R6; 268def : MipsPat<(select (i32 (setne i32:$cond, immz)), i64:$t, i64:$f), 269 (OR64 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond)), 270 (SELEQZ64 i64:$f, (SLL64_32 i32:$cond)))>, 271 ISA_MIPS64R6; 272def : MipsPat<(select (i32 (seteq i32:$cond, immZExt16:$imm)), i64:$t, i64:$f), 273 (OR64 (SELEQZ64 i64:$t, (SLL64_32 (XORi i32:$cond, 274 immZExt16:$imm))), 275 (SELNEZ64 i64:$f, (SLL64_32 (XORi i32:$cond, 276 immZExt16:$imm))))>, 277 ISA_MIPS64R6; 278def : MipsPat<(select (i32 (setne i32:$cond, immZExt16:$imm)), i64:$t, i64:$f), 279 (OR64 (SELNEZ64 i64:$t, (SLL64_32 (XORi i32:$cond, 280 immZExt16:$imm))), 281 (SELEQZ64 i64:$f, (SLL64_32 (XORi i32:$cond, 282 immZExt16:$imm))))>, 283 ISA_MIPS64R6; 284 285def : MipsPat<(select i32:$cond, i64:$t, immz), 286 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond))>, 287 ISA_MIPS64R6; 288def : MipsPat<(select (i32 (setne i32:$cond, immz)), i64:$t, immz), 289 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond))>, 290 ISA_MIPS64R6; 291def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i64:$t, immz), 292 (SELEQZ64 i64:$t, (SLL64_32 i32:$cond))>, 293 ISA_MIPS64R6; 294def : MipsPat<(select i32:$cond, immz, i64:$f), 295 (SELEQZ64 i64:$f, (SLL64_32 i32:$cond))>, 296 ISA_MIPS64R6; 297def : MipsPat<(select (i32 (setne i32:$cond, immz)), immz, i64:$f), 298 (SELEQZ64 i64:$f, (SLL64_32 i32:$cond))>, 299 ISA_MIPS64R6; 300def : MipsPat<(select (i32 (seteq i32:$cond, immz)), immz, i64:$f), 301 (SELNEZ64 i64:$f, (SLL64_32 i32:$cond))>, 302 ISA_MIPS64R6; 303 304// Patterns used for matching away redundant sign extensions. 305// MIPS32 arithmetic instructions sign extend their result implicitly. 306def : MipsPat<(i64 (sext (i32 (mul GPR32:$src, GPR32:$src2)))), 307 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 308 (MUL_R6 GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS64R6; 309def : MipsPat<(i64 (sext (i32 (sdiv GPR32:$src, GPR32:$src2)))), 310 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 311 (DIV GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS64R6; 312def : MipsPat<(i64 (sext (i32 (udiv GPR32:$src, GPR32:$src2)))), 313 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 314 (DIVU GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS64R6; 315def : MipsPat<(i64 (sext (i32 (srem GPR32:$src, GPR32:$src2)))), 316 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 317 (MOD GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS64R6; 318def : MipsPat<(i64 (sext (i32 (urem GPR32:$src, GPR32:$src2)))), 319 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 320 (MODU GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS64R6; 321 322// Pseudo instructions 323 324let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips, 325 NoIndirectJumpGuards] in { 326 def TAILCALL64R6REG : TailCallRegR6<JALR64, ZERO_64, GPR64Opnd>, ISA_MIPS64R6; 327 def PseudoIndirectBranch64R6 : PseudoIndirectBranchBaseR6<JALR64, ZERO_64, 328 GPR64Opnd>, 329 ISA_MIPS64R6; 330} 331 332let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips, 333 UseIndirectJumpsHazard] in { 334 def TAILCALLHB64R6REG : TailCallReg<JR_HB64_R6, GPR64Opnd>, 335 ISA_MIPS64R6; 336 def PseudoIndrectHazardBranch64R6 : PseudoIndirectBranchBase<JR_HB64_R6, 337 GPR64Opnd>, 338 ISA_MIPS64R6; 339} 340