1//=- MicroMips32r6InstrFormats.td - Mips32r6 Instruction Formats -*- tablegen -*-==// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes microMIPS32r6 instruction formats. 10// 11//===----------------------------------------------------------------------===// 12 13class MMR6Arch<string opstr> { 14 string Arch = "micromipsr6"; 15 string BaseOpcode = opstr; 16 string DecoderNamespace = "MicroMipsR6"; 17} 18 19//===----------------------------------------------------------------------===// 20// 21// Disambiguators 22// 23//===----------------------------------------------------------------------===// 24// 25// Some encodings are ambiguous except by comparing field values. 26 27class MMDecodeDisambiguatedBy<string Name> : DecodeDisambiguates<Name> { 28 string DecoderNamespace = "MicroMipsR6_Ambiguous"; 29} 30 31//===----------------------------------------------------------------------===// 32// 33// Encoding Formats 34// 35//===----------------------------------------------------------------------===// 36 37class BC16_FM_MM16R6 { 38 bits<10> offset; 39 40 bits<16> Inst; 41 42 let Inst{15-10} = 0x33; 43 let Inst{9-0} = offset; 44} 45 46class BEQZC_BNEZC_FM_MM16R6<bits<6> op> { 47 bits<3> rs; 48 bits<7> offset; 49 50 bits<16> Inst; 51 52 let Inst{15-10} = op; 53 let Inst{9-7} = rs; 54 let Inst{6-0} = offset; 55} 56 57class POOL16C_JALRC_FM_MM16R6<bits<5> op> { 58 bits<5> rs; 59 60 bits<16> Inst; 61 62 let Inst{15-10} = 0x11; 63 let Inst{9-5} = rs; 64 let Inst{4-0} = op; 65} 66 67class POP35_BOVC_FM_MMR6<string instr_asm> : MipsR6Inst, MMR6Arch<instr_asm> { 68 bits<5> rt; 69 bits<5> rs; 70 bits<16> offset; 71 72 bits<32> Inst; 73 74 let Inst{31-26} = 0b011101; 75 let Inst{25-21} = rt; 76 let Inst{20-16} = rs; 77 let Inst{15-0} = offset; 78} 79 80class POP37_BNVC_FM_MMR6<string instr_asm> : MipsR6Inst, MMR6Arch<instr_asm> { 81 bits<5> rt; 82 bits<5> rs; 83 bits<16> offset; 84 85 bits<32> Inst; 86 87 let Inst{31-26} = 0b011111; 88 let Inst{25-21} = rt; 89 let Inst{20-16} = rs; 90 let Inst{15-0} = offset; 91} 92 93class POOL16C_JRCADDIUSP_FM_MM16R6<bits<5> op> { 94 bits<5> imm; 95 96 bits<16> Inst; 97 98 let Inst{15-10} = 0x11; 99 let Inst{9-5} = imm; 100 let Inst{4-0} = op; 101} 102 103class POOL16C_LWM_SWM_FM_MM16R6<bits<4> funct> { 104 bits<2> rt; 105 bits<4> addr; 106 107 bits<16> Inst; 108 109 let Inst{15-10} = 0x11; 110 let Inst{9-8} = rt; 111 let Inst{7-4} = addr; 112 let Inst{3-0} = funct; 113} 114 115class POOL32A_BITSWAP_FM_MMR6<bits<6> funct> : MipsR6Inst { 116 bits<5> rd; 117 bits<5> rt; 118 119 bits<32> Inst; 120 121 let Inst{31-26} = 0b000000; 122 let Inst{25-21} = rt; 123 let Inst{20-16} = rd; 124 let Inst{15-12} = 0b0000; 125 let Inst{11-6} = funct; 126 let Inst{5-0} = 0b111100; 127} 128 129class CACHE_PREF_FM_MMR6<bits<6> opgroup, bits<4> funct> : MipsR6Inst { 130 bits<21> addr; 131 bits<5> hint; 132 133 bits<32> Inst; 134 135 let Inst{31-26} = opgroup; 136 let Inst{25-21} = hint; 137 let Inst{20-16} = addr{20-16}; 138 let Inst{15-12} = funct; 139 let Inst{11-0} = addr{11-0}; 140} 141 142class ARITH_FM_MMR6<string instr_asm, bits<10> funct> : MMR6Arch<instr_asm> { 143 bits<5> rd; 144 bits<5> rt; 145 bits<5> rs; 146 147 bits<32> Inst; 148 149 let Inst{31-26} = 0; 150 let Inst{25-21} = rt; 151 let Inst{20-16} = rs; 152 let Inst{15-11} = rd; 153 let Inst{10} = 0; 154 let Inst{9-0} = funct; 155} 156 157class ADDI_FM_MMR6<string instr_asm, bits<6> op> : MMR6Arch<instr_asm> { 158 bits<5> rt; 159 bits<5> rs; 160 bits<16> imm16; 161 162 bits<32> Inst; 163 164 let Inst{31-26} = op; 165 let Inst{25-21} = rt; 166 let Inst{20-16} = rs; 167 let Inst{15-0} = imm16; 168} 169 170class LB32_FM_MMR6 : MipsR6Inst { 171 bits<21> addr; 172 bits<5> rt; 173 bits<5> base = addr{20-16}; 174 bits<16> offset = addr{15-0}; 175 176 bits<32> Inst; 177 178 let Inst{31-26} = 0b000111; 179 let Inst{25-21} = rt; 180 let Inst{20-16} = base; 181 let Inst{15-0} = offset; 182} 183 184class LBU32_FM_MMR6 : MipsR6Inst { 185 bits<21> addr; 186 bits<5> rt; 187 bits<5> base = addr{20-16}; 188 bits<16> offset = addr{15-0}; 189 190 bits<32> Inst; 191 192 let Inst{31-26} = 0b000101; 193 let Inst{25-21} = rt; 194 let Inst{20-16} = base; 195 let Inst{15-0} = offset; 196} 197 198class PCREL19_FM_MMR6<bits<2> funct> : MipsR6Inst { 199 bits<5> rt; 200 bits<19> imm; 201 202 bits<32> Inst; 203 204 let Inst{31-26} = 0b011110; 205 let Inst{25-21} = rt; 206 let Inst{20-19} = funct; 207 let Inst{18-0} = imm; 208} 209 210class PCREL16_FM_MMR6<bits<5> funct> : MipsR6Inst { 211 bits<5> rt; 212 bits<16> imm; 213 214 bits<32> Inst; 215 216 let Inst{31-26} = 0b011110; 217 let Inst{25-21} = rt; 218 let Inst{20-16} = funct; 219 let Inst{15-0} = imm; 220} 221 222class POOL32A_FM_MMR6<bits<10> funct> : MipsR6Inst { 223 bits<5> rd; 224 bits<5> rs; 225 bits<5> rt; 226 227 bits<32> Inst; 228 229 let Inst{31-26} = 0b000000; 230 let Inst{25-21} = rt; 231 let Inst{20-16} = rs; 232 let Inst{15-11} = rd; 233 let Inst{10} = 0; 234 let Inst{9-0} = funct; 235} 236 237class POOL32A_PAUSE_FM_MMR6<string instr_asm, bits<5> op> : MMR6Arch<instr_asm> { 238 bits<32> Inst; 239 240 let Inst{31-26} = 0; 241 let Inst{25-21} = 0; 242 let Inst{20-16} = 0; 243 let Inst{15-11} = op; 244 let Inst{10-6} = 0; 245 let Inst{5-0} = 0; 246} 247 248class POOL32A_RDPGPR_FM_MMR6<bits<10> funct> { 249 bits<5> rt; 250 bits<5> rd; 251 bits<32> Inst; 252 253 let Inst{31-26} = 0; 254 let Inst{25-21} = rt; 255 let Inst{20-16} = rd; 256 let Inst{15-6} = funct; 257 let Inst{5-0} = 0b111100; 258} 259 260class POOL32A_RDHWR_FM_MMR6 { 261 bits<5> rt; 262 bits<5> rs; 263 bits<3> sel; 264 bits<32> Inst; 265 266 let Inst{31-26} = 0; 267 let Inst{25-21} = rt; 268 let Inst{20-16} = rs; 269 let Inst{15-14} = 0; 270 let Inst{13-11} = sel; 271 let Inst{10} = 0; 272 let Inst{9-0} = 0b0111000000; 273} 274 275class POOL32A_SYNC_FM_MMR6 { 276 bits<5> stype; 277 278 bits<32> Inst; 279 280 let Inst{31-26} = 0; 281 let Inst{25-21} = 0; 282 let Inst{20-16} = stype; 283 let Inst{15-6} = 0b0110101101; 284 let Inst{5-0} = 0b111100; 285} 286 287class POOL32I_SYNCI_FM_MMR6 { 288 bits<21> addr; 289 bits<5> base = addr{20-16}; 290 bits<16> immediate = addr{15-0}; 291 292 bits<32> Inst; 293 294 let Inst{31-26} = 0b010000; 295 let Inst{25-21} = 0b01100; 296 let Inst{20-16} = base; 297 let Inst{15-0} = immediate; 298} 299 300class POOL32A_2R_FM_MMR6<bits<10> funct> : MipsR6Inst { 301 bits<5> rs; 302 bits<5> rt; 303 304 bits<32> Inst; 305 306 let Inst{31-26} = 0b000000; 307 let Inst{25-21} = rt; 308 let Inst{20-16} = rs; 309 let Inst{15-6} = funct; 310 let Inst{5-0} = 0b111100; 311} 312 313class SPECIAL_2R_FM_MMR6<bits<6> funct> : MipsR6Inst { 314 bits<5> rs; 315 bits<5> rt; 316 317 bits<32> Inst; 318 319 let Inst{31-26} = 0b000000; 320 let Inst{25-21} = rs; 321 let Inst{20-16} = 0b00000; 322 let Inst{15-11} = rt; 323 let Inst{10-6} = 0b00001; 324 let Inst{5-0} = funct; 325} 326 327class POOL32A_ALIGN_FM_MMR6<bits<6> funct> : MipsR6Inst { 328 bits<5> rd; 329 bits<5> rs; 330 bits<5> rt; 331 bits<2> bp; 332 333 bits<32> Inst; 334 335 let Inst{31-26} = 0b000000; 336 let Inst{25-21} = rs; 337 let Inst{20-16} = rt; 338 let Inst{15-11} = rd; 339 let Inst{10-9} = bp; 340 let Inst{8-6} = 0b000; 341 let Inst{5-0} = funct; 342} 343 344class AUI_FM_MMR6 : MipsR6Inst { 345 bits<5> rs; 346 bits<5> rt; 347 bits<16> imm; 348 349 bits<32> Inst; 350 351 let Inst{31-26} = 0b000100; 352 let Inst{25-21} = rt; 353 let Inst{20-16} = rs; 354 let Inst{15-0} = imm; 355} 356 357class POOL32A_LSA_FM<bits<6> funct> : MipsR6Inst { 358 bits<5> rd; 359 bits<5> rs; 360 bits<5> rt; 361 bits<2> imm2; 362 363 bits<32> Inst; 364 365 let Inst{31-26} = 0b000000; 366 let Inst{25-21} = rt; 367 let Inst{20-16} = rs; 368 let Inst{15-11} = rd; 369 let Inst{10-9} = imm2; 370 let Inst{8-6} = 0b000; 371 let Inst{5-0} = funct; 372} 373 374class SB32_SH32_STORE_FM_MMR6<bits<6> op> { 375 bits<5> rt; 376 bits<21> addr; 377 bits<5> base = addr{20-16}; 378 bits<16> offset = addr{15-0}; 379 380 bits<32> Inst; 381 382 let Inst{31-26} = op; 383 let Inst{25-21} = rt; 384 let Inst{20-16} = base; 385 let Inst{15-0} = offset; 386} 387 388class LOAD_WORD_FM_MMR6 { 389 bits<5> rt; 390 bits<21> addr; 391 bits<5> base = addr{20-16}; 392 bits<16> offset = addr{15-0}; 393 394 bits<32> Inst; 395 396 let Inst{31-26} = 0b111111; 397 let Inst{25-21} = rt; 398 let Inst{20-16} = base; 399 let Inst{15-0} = offset; 400} 401 402class LOAD_UPPER_IMM_FM_MMR6 { 403 bits<5> rt; 404 bits<16> imm16; 405 406 bits<32> Inst; 407 408 let Inst{31-26} = 0b000100; 409 let Inst{25-21} = rt; 410 let Inst{20-16} = 0; 411 let Inst{15-0} = imm16; 412} 413 414class CMP_BRANCH_1R_RT_OFF16_FM_MMR6<string instr_asm, bits<6> funct> 415 : MMR6Arch<instr_asm>, MipsR6Inst { 416 bits<5> rt; 417 bits<16> offset; 418 419 bits<32> Inst; 420 421 let Inst{31-26} = funct; 422 let Inst{25-21} = rt; 423 let Inst{20-16} = 0b00000; 424 let Inst{15-0} = offset; 425} 426 427class CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<string instr_asm, bits<6> funct> 428 : MMR6Arch<instr_asm>, MipsR6Inst { 429 bits<5> rt; 430 bits<16> offset; 431 432 bits<32> Inst; 433 434 let Inst{31-26} = funct; 435 let Inst{25-21} = rt; 436 let Inst{20-16} = rt; 437 let Inst{15-0} = offset; 438} 439 440class POOL32A_JALRC_FM_MMR6<string instr_asm, bits<10> funct> 441 : MipsR6Inst, MMR6Arch<instr_asm> { 442 bits<5> rt; 443 bits<5> rs; 444 445 bits<32> Inst; 446 447 let Inst{31-26} = 0; 448 let Inst{25-21} = rt; 449 let Inst{20-16} = rs; 450 let Inst{15-6} = funct; 451 let Inst{5-0} = 0b111100; 452} 453 454class POOL32A_EXT_INS_FM_MMR6<string instr_asm, bits<6> funct> 455 : MMR6Arch<instr_asm>, MipsR6Inst { 456 bits<5> rt; 457 bits<5> rs; 458 bits<5> size; 459 bits<5> pos; 460 461 bits<32> Inst; 462 463 let Inst{31-26} = 0; 464 let Inst{25-21} = rt; 465 let Inst{20-16} = rs; 466 let Inst{15-11} = size; 467 let Inst{10-6} = pos; 468 let Inst{5-0} = funct; 469} 470 471class POOL32A_ERET_FM_MMR6<string instr_asm, bits<10> funct> 472 : MMR6Arch<instr_asm> { 473 bits<32> Inst; 474 475 let Inst{31-26} = 0x00; 476 let Inst{25-16} = 0x00; 477 let Inst{15-6} = funct; 478 let Inst{5-0} = 0x3c; 479} 480 481class ERETNC_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm> { 482 bits<32> Inst; 483 484 let Inst{31-26} = 0x00; 485 let Inst{25-17} = 0x00; 486 let Inst{16-16} = 0x01; 487 let Inst{15-6} = 0x3cd; 488 let Inst{5-0} = 0x3c; 489} 490 491class BREAK_MMR6_ENC<string instr_asm> : MMR6Arch<instr_asm> { 492 bits<10> code_1; 493 bits<10> code_2; 494 bits<32> Inst; 495 let Inst{31-26} = 0x0; 496 let Inst{25-16} = code_1; 497 let Inst{15-6} = code_2; 498 let Inst{5-0} = 0x07; 499} 500 501class BARRIER_MMR6_ENC<string instr_asm, bits<5> op> : MMR6Arch<instr_asm> { 502 bits<32> Inst; 503 504 let Inst{31-26} = 0x0; 505 let Inst{25-21} = 0x0; 506 let Inst{20-16} = 0x0; 507 let Inst{15-11} = op; 508 let Inst{10-6} = 0x0; 509 let Inst{5-0} = 0x0; 510} 511 512class POOL32A_EIDI_MMR6_ENC<string instr_asm, bits<10> funct> 513 : MMR6Arch<instr_asm> { 514 bits<32> Inst; 515 bits<5> rt; // Actually rs but we're sharing code with the standard encodings which call it rt 516 517 let Inst{31-26} = 0x00; 518 let Inst{25-21} = 0x00; 519 let Inst{20-16} = rt; 520 let Inst{15-6} = funct; 521 let Inst{5-0} = 0x3c; 522} 523 524class SHIFT_MMR6_ENC<string instr_asm, bits<10> funct, bit rotate> : MMR6Arch<instr_asm> { 525 bits<5> rd; 526 bits<5> rt; 527 bits<5> shamt; 528 529 bits<32> Inst; 530 531 let Inst{31-26} = 0; 532 let Inst{25-21} = rd; 533 let Inst{20-16} = rt; 534 let Inst{15-11} = shamt; 535 let Inst{10} = rotate; 536 let Inst{9-0} = funct; 537} 538 539class SW32_FM_MMR6<string instr_asm, bits<6> op> : MMR6Arch<instr_asm> { 540 bits<5> rt; 541 bits<21> addr; 542 543 bits<32> Inst; 544 545 let Inst{31-26} = op; 546 let Inst{25-21} = rt; 547 let Inst{20-16} = addr{20-16}; 548 let Inst{15-0} = addr{15-0}; 549} 550 551class POOL32F_ARITH_FM_MMR6<string instr_asm, bits<2> fmt, bits<8> funct> 552 : MMR6Arch<instr_asm>, MipsR6Inst { 553 bits<5> ft; 554 bits<5> fs; 555 bits<5> fd; 556 557 bits<32> Inst; 558 559 let Inst{31-26} = 0b010101; 560 let Inst{25-21} = ft; 561 let Inst{20-16} = fs; 562 let Inst{15-11} = fd; 563 let Inst{10} = 0; 564 let Inst{9-8} = fmt; 565 let Inst{7-0} = funct; 566} 567 568class POOL32F_ARITHF_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct> 569 : MMR6Arch<instr_asm>, MipsR6Inst { 570 bits<5> ft; 571 bits<5> fs; 572 bits<5> fd; 573 574 bits<32> Inst; 575 576 let Inst{31-26} = 0b010101; 577 let Inst{25-21} = ft; 578 let Inst{20-16} = fs; 579 let Inst{15-11} = fd; 580 let Inst{10-9} = fmt; 581 let Inst{8-0} = funct; 582} 583 584class POOL32F_MOV_NEG_FM_MMR6<string instr_asm, bits<2> fmt, bits<7> funct> 585 : MMR6Arch<instr_asm>, MipsR6Inst { 586 bits<5> ft; 587 bits<5> fs; 588 589 bits<32> Inst; 590 591 let Inst{31-26} = 0b010101; 592 let Inst{25-21} = ft; 593 let Inst{20-16} = fs; 594 let Inst{15} = 0; 595 let Inst{14-13} = fmt; 596 let Inst{12-6} = funct; 597 let Inst{5-0} = 0b111011; 598} 599 600class POOL32F_MINMAX_FM<string instr_asm, bits<2> fmt, bits<9> funct> 601 : MMR6Arch<instr_asm>, MipsR6Inst { 602 bits<5> ft; 603 bits<5> fs; 604 bits<5> fd; 605 606 bits<32> Inst; 607 608 let Inst{31-26} = 0b010101; 609 let Inst{25-21} = ft; 610 let Inst{20-16} = fs; 611 let Inst{15-11} = fd; 612 let Inst{10-9} = fmt; 613 let Inst{8-0} = funct; 614} 615 616class POOL32F_CMP_FM<string instr_asm, bits<6> format, FIELD_CMP_COND Cond> 617 : MMR6Arch<instr_asm>, MipsR6Inst { 618 bits<5> ft; 619 bits<5> fs; 620 bits<5> fd; 621 622 bits<32> Inst; 623 624 let Inst{31-26} = 0b010101; 625 let Inst{25-21} = ft; 626 let Inst{20-16} = fs; 627 let Inst{15-11} = fd; 628 let Inst{10-6} = Cond.Value; 629 let Inst{5-0} = format; 630} 631 632class POOL32F_CVT_LW_FM<string instr_asm, bit fmt, bits<8> funct> 633 : MMR6Arch<instr_asm>, MipsR6Inst { 634 bits<5> ft; 635 bits<5> fs; 636 637 bits<32> Inst; 638 let Inst{31-26} = 0b010101; 639 let Inst{25-21} = ft; 640 let Inst{20-16} = fs; 641 let Inst{15} = 0; 642 let Inst{14} = fmt; 643 let Inst{13-6} = funct; 644 let Inst{5-0} = 0b111011; 645} 646 647class POOL32F_CVT_DS_FM<string instr_asm, bits<2> fmt, bits<7> funct> 648 : MMR6Arch<instr_asm>, MipsR6Inst { 649 bits<5> ft; 650 bits<5> fs; 651 652 bits<32> Inst; 653 let Inst{31-26} = 0b010101; 654 let Inst{25-21} = ft; 655 let Inst{20-16} = fs; 656 let Inst{15} = 0; 657 let Inst{14-13} = fmt; 658 let Inst{12-6} = funct; 659 let Inst{5-0} = 0b111011; 660} 661 662class POOL32F_ABS_FM_MMR6<string instr_asm, bits<2> fmt, bits<7> funct> 663 : MMR6Arch<instr_asm>, MipsR6Inst { 664 bits<5> ft; 665 bits<5> fs; 666 667 bits<32> Inst; 668 669 let Inst{31-26} = 0b010101; 670 let Inst{25-21} = ft; 671 let Inst{20-16} = fs; 672 let Inst{15} = 0; 673 let Inst{14-13} = fmt; 674 let Inst{12-6} = funct; 675 let Inst{5-0} = 0b111011; 676} 677 678class POOL32F_MATH_FM_MMR6<string instr_asm, bits<1> fmt, bits<8> funct> 679 : MMR6Arch<instr_asm>, MipsR6Inst { 680 bits<5> ft; 681 bits<5> fs; 682 683 bits<32> Inst; 684 685 let Inst{31-26} = 0b010101; 686 let Inst{25-21} = ft; 687 let Inst{20-16} = fs; 688 let Inst{15} = 0; 689 let Inst{14} = fmt; 690 let Inst{13-6} = funct; 691 let Inst{5-0} = 0b111011; 692} 693 694class POOL16A_ADDU16_FM_MMR6 { 695 bits<3> rs; 696 bits<3> rt; 697 bits<3> rd; 698 699 bits<16> Inst; 700 701 let Inst{15-10} = 0b000001; 702 let Inst{9-7} = rs; 703 let Inst{6-4} = rt; 704 let Inst{3-1} = rd; 705 let Inst{0} = 0; 706} 707 708class POOL16C_AND16_FM_MMR6 { 709 bits<3> rt; 710 bits<3> rs; 711 712 bits<16> Inst; 713 714 let Inst{15-10} = 0b010001; 715 let Inst{9-7} = rt; 716 let Inst{6-4} = rs; 717 let Inst{3-0} = 0b0001; 718} 719 720class POOL16C_NOT16_FM_MMR6 { 721 bits<3> rt; 722 bits<3> rs; 723 724 bits<16> Inst; 725 726 let Inst{15-10} = 0x11; 727 let Inst{9-7} = rt; 728 let Inst{6-4} = rs; 729 let Inst{3-0} = 0b0000; 730} 731 732class POOL16C_MOVEP16_FM_MMR6 { 733 bits<3> dst_regs; 734 bits<3> rt; 735 bits<3> rs; 736 737 bits<16> Inst; 738 739 let Inst{15-10} = 0b010001; 740 let Inst{9-7} = dst_regs; 741 let Inst{6-4} = rt; 742 let Inst{3} = rs{2}; 743 let Inst{2} = 0b1; 744 let Inst{1-0} = rs{1-0}; 745} 746 747class POOL16C_OR16_XOR16_FM_MMR6<bits<4> op> { 748 bits<3> rt; 749 bits<3> rs; 750 751 bits<16> Inst; 752 753 let Inst{15-10} = 0b010001; 754 let Inst{9-7} = rt; 755 let Inst{6-4} = rs; 756 let Inst{3-0} = op; 757} 758 759class POOL16C_BREAKPOINT_FM_MMR6<bits<6> op> { 760 bits<4> code_; 761 bits<16> Inst; 762 763 let Inst{15-10} = 0b010001; 764 let Inst{9-6} = code_; 765 let Inst{5-0} = op; 766} 767 768class POOL16A_SUBU16_FM_MMR6 { 769 bits<3> rs; 770 bits<3> rt; 771 bits<3> rd; 772 773 bits<16> Inst; 774 775 let Inst{15-10} = 0b000001; 776 let Inst{9-7} = rs; 777 let Inst{6-4} = rt; 778 let Inst{3-1} = rd; 779 let Inst{0} = 0b1; 780} 781 782class POOL32A_WRPGPR_WSBH_FM_MMR6<string instr_asm, bits<10> funct> 783 : MMR6Arch<instr_asm>, MipsR6Inst { 784 bits<5> rt; 785 bits<5> rs; 786 787 bits<32> Inst; 788 789 let Inst{31-26} = 0x00; 790 let Inst{25-21} = rt; 791 let Inst{20-16} = rs; 792 let Inst{15-6} = funct; 793 let Inst{5-0} = 0x3c; 794} 795 796class POOL32F_RECIP_ROUND_FM_MMR6<string instr_asm, bits<1> fmt, bits<8> funct> 797 : MMR6Arch<instr_asm>, MipsR6Inst { 798 bits<5> ft; 799 bits<5> fs; 800 801 bits<32> Inst; 802 803 let Inst{31-26} = 0b010101; 804 let Inst{25-21} = ft; 805 let Inst{20-16} = fs; 806 let Inst{15} = 0; 807 let Inst{14} = fmt; 808 let Inst{13-6} = funct; 809 let Inst{5-0} = 0b111011; 810} 811 812class POOL32F_RINT_FM_MMR6<string instr_asm, bits<2> fmt> 813 : MMR6Arch<instr_asm>, MipsR6Inst { 814 bits<5> fs; 815 bits<5> fd; 816 817 bits<32> Inst; 818 819 let Inst{31-26} = 0b010101; 820 let Inst{25-21} = fs; 821 let Inst{20-16} = fd; 822 let Inst{15-11} = 0; 823 let Inst{10-9} = fmt; 824 let Inst{8-0} = 0b000100000; 825} 826 827class POOL32F_SEL_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct> 828 : MMR6Arch<instr_asm>, MipsR6Inst { 829 bits<5> ft; 830 bits<5> fs; 831 bits<5> fd; 832 833 bits<32> Inst; 834 835 let Inst{31-26} = 0b010101; 836 let Inst{25-21} = ft; 837 let Inst{20-16} = fs; 838 let Inst{15-11} = fd; 839 let Inst{10-9} = fmt; 840 let Inst{8-0} = funct; 841} 842 843class POOL32F_CLASS_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct> 844 : MMR6Arch<instr_asm>, MipsR6Inst { 845 bits<5> fs; 846 bits<5> fd; 847 848 bits<32> Inst; 849 850 let Inst{31-26} = 0b010101; 851 let Inst{25-21} = fs; 852 let Inst{20-16} = fd; 853 let Inst{15-11} = 0b00000; 854 let Inst{10-9} = fmt; 855 let Inst{8-0} = funct; 856} 857 858class POOL32A_TLBINV_FM_MMR6<string instr_asm, bits<10> funct> 859 : MMR6Arch<instr_asm>, MipsR6Inst { 860 bits<32> Inst; 861 862 let Inst{31-26} = 0x0; 863 let Inst{25-16} = 0x0; 864 let Inst{15-6} = funct; 865 let Inst{5-0} = 0b111100; 866} 867 868class POOL32A_MFTC0_FM_MMR6<string instr_asm, bits<5> funct, bits<6> opcode> 869 : MMR6Arch<instr_asm>, MipsR6Inst { 870 bits<5> rt; 871 bits<5> rs; 872 bits<3> sel; 873 874 bits<32> Inst; 875 876 let Inst{31-26} = 0b000000; 877 let Inst{25-21} = rt; 878 let Inst{20-16} = rs; 879 let Inst{15-14} = 0; 880 let Inst{13-11} = sel; 881 let Inst{10-6} = funct; 882 let Inst{5-0} = opcode; 883} 884 885class POOL32A_GINV_FM_MMR6<string instr_asm, bits<2> ginv> 886 : MMR6Arch<instr_asm>, MipsR6Inst { 887 bits<5> rs; 888 bits<2> type; 889 890 bits<32> Inst; 891 892 let Inst{31-26} = 0x0; 893 let Inst{25-21} = 0x0; 894 let Inst{20-16} = rs; 895 let Inst{15-13} = 0b011; 896 let Inst{12-11} = ginv; 897 let Inst{10-9} = type; 898 let Inst{8-6} = 0b101; 899 let Inst{5-0} = 0b111100; 900} 901 902class POOL32F_MFTC1_FM_MMR6<string instr_asm, bits<8> funct> 903 : MMR6Arch<instr_asm> { 904 bits<5> rt; 905 bits<5> fs; 906 907 bits<32> Inst; 908 909 let Inst{31-26} = 0b010101; 910 let Inst{25-21} = rt; 911 let Inst{20-16} = fs; 912 let Inst{15-14} = 0; 913 let Inst{13-6} = funct; 914 let Inst{5-0} = 0b111011; 915} 916 917class POOL32A_MFTC2_FM_MMR6<string instr_asm, bits<10> funct> 918 : MMR6Arch<instr_asm>, MipsR6Inst { 919 bits<5> rt; 920 bits<5> impl; 921 922 bits<32> Inst; 923 924 let Inst{31-26} = 0b000000; 925 let Inst{25-21} = rt; 926 let Inst{20-16} = impl; 927 let Inst{15-6} = funct; 928 let Inst{5-0} = 0b111100; 929} 930 931class CMP_BRANCH_2R_OFF16_FM_MMR6<string opstr, bits<6> funct> 932 : MipsR6Inst, MMR6Arch<opstr> { 933 bits<5> rt; 934 bits<5> rs; 935 bits<16> offset; 936 937 bits<32> Inst; 938 939 let Inst{31-26} = funct; 940 let Inst{25-21} = rt; 941 let Inst{20-16} = rs; 942 let Inst{15-0} = offset; 943} 944 945class POOL32A_DVPEVP_FM_MMR6<string instr_asm, bits<10> funct> 946 : MMR6Arch<instr_asm>, MipsR6Inst { 947 bits<5> rs; 948 949 bits<32> Inst; 950 951 let Inst{31-26} = 0b000000; 952 let Inst{25-21} = 0b00000; 953 let Inst{20-16} = rs; 954 let Inst{15-6} = funct; 955 let Inst{5-0} = 0b111100; 956} 957 958class CMP_BRANCH_OFF21_FM_MMR6<string opstr, bits<6> funct> : MipsR6Inst { 959 bits<5> rs; 960 bits<21> offset; 961 962 bits<32> Inst; 963 964 let Inst{31-26} = funct; 965 let Inst{25-21} = rs; 966 let Inst{20-0} = offset; 967} 968 969class POOL32I_BRANCH_COP_1_2_FM_MMR6<string instr_asm, bits<5> funct> 970 : MMR6Arch<instr_asm> { 971 bits<5> rt; 972 bits<16> offset; 973 974 bits<32> Inst; 975 976 let Inst{31-26} = 0b010000; 977 let Inst{25-21} = funct; 978 let Inst{20-16} = rt; 979 let Inst{15-0} = offset; 980} 981 982class LDWC1_SDWC1_FM_MMR6<string instr_asm, bits<6> funct> 983 : MMR6Arch<instr_asm> { 984 bits<5> ft; 985 bits<21> addr; 986 bits<5> base = addr{20-16}; 987 bits<16> offset = addr{15-0}; 988 989 bits<32> Inst; 990 991 let Inst{31-26} = funct; 992 let Inst{25-21} = ft; 993 let Inst{20-16} = base; 994 let Inst{15-0} = offset; 995} 996 997class POOL32B_LDWC2_SDWC2_FM_MMR6<string instr_asm, bits<4> funct> 998 : MMR6Arch<instr_asm>, MipsR6Inst { 999 bits<5> rt; 1000 bits<21> addr; 1001 bits<5> base = addr{20-16}; 1002 bits<11> offset = addr{10-0}; 1003 1004 bits<32> Inst; 1005 1006 let Inst{31-26} = 0b001000; 1007 let Inst{25-21} = rt; 1008 let Inst{20-16} = base; 1009 let Inst{15-12} = funct; 1010 let Inst{11} = 0; 1011 let Inst{10-0} = offset; 1012} 1013 1014class POOL32C_LL_E_SC_E_FM_MMR6<string instr_asm, bits<4> majorFunc, 1015 bits<3> minorFunc> 1016 : MMR6Arch<instr_asm>, MipsR6Inst { 1017 bits<5> rt; 1018 bits<21> addr; 1019 bits<5> base = addr{20-16}; 1020 bits<9> offset = addr{8-0}; 1021 1022 bits<32> Inst; 1023 1024 let Inst{31-26} = 0b011000; 1025 let Inst{25-21} = rt; 1026 let Inst{20-16} = base; 1027 let Inst{15-12} = majorFunc; 1028 let Inst{11-9} = minorFunc; 1029 let Inst{8-0} = offset; 1030} 1031