194a420b1SStefan Hajnoczi# Trace events for debugging and performance instrumentation 294a420b1SStefan Hajnoczi# 394a420b1SStefan Hajnoczi# This file is processed by the tracetool script during the build. 494a420b1SStefan Hajnoczi# 594a420b1SStefan Hajnoczi# To add a new trace event: 694a420b1SStefan Hajnoczi# 794a420b1SStefan Hajnoczi# 1. Choose a name for the trace event. Declare its arguments and format 894a420b1SStefan Hajnoczi# string. 994a420b1SStefan Hajnoczi# 1094a420b1SStefan Hajnoczi# 2. Call the trace event from code using trace_##name, e.g. multiwrite_cb() -> 1194a420b1SStefan Hajnoczi# trace_multiwrite_cb(). The source file must #include "trace.h". 1294a420b1SStefan Hajnoczi# 1394a420b1SStefan Hajnoczi# Format of a trace event: 1494a420b1SStefan Hajnoczi# 151e2cf2bcSStefan Hajnoczi# [disable] <name>(<type1> <arg1>[, <type2> <arg2>] ...) "<format-string>" 1694a420b1SStefan Hajnoczi# 1794a420b1SStefan Hajnoczi# Example: qemu_malloc(size_t size) "size %zu" 1894a420b1SStefan Hajnoczi# 191e2cf2bcSStefan Hajnoczi# The "disable" keyword will build without the trace event. 201e2cf2bcSStefan Hajnoczi# In case of 'simple' trace backend, it will allow the trace event to be 211e2cf2bcSStefan Hajnoczi# compiled, but this would be turned off by default. It can be toggled on via 221e2cf2bcSStefan Hajnoczi# the monitor. 231e2cf2bcSStefan Hajnoczi# 2494a420b1SStefan Hajnoczi# The <name> must be a valid as a C function name. 2594a420b1SStefan Hajnoczi# 2694a420b1SStefan Hajnoczi# Types should be standard C types. Use void * for pointers because the trace 2794a420b1SStefan Hajnoczi# system may not have the necessary headers included. 2894a420b1SStefan Hajnoczi# 2994a420b1SStefan Hajnoczi# The <format-string> should be a sprintf()-compatible format string. 30cd245a19SStefan Hajnoczi 31cd245a19SStefan Hajnoczi# qemu-malloc.c 32cd245a19SStefan Hajnoczidisable qemu_malloc(size_t size, void *ptr) "size %zu ptr %p" 33cd245a19SStefan Hajnoczidisable qemu_realloc(void *ptr, size_t size, void *newptr) "ptr %p size %zu newptr %p" 34cd245a19SStefan Hajnoczidisable qemu_free(void *ptr) "ptr %p" 35cd245a19SStefan Hajnoczi 36cd245a19SStefan Hajnoczi# osdep.c 37cd245a19SStefan Hajnoczidisable qemu_memalign(size_t alignment, size_t size, void *ptr) "alignment %zu size %zu ptr %p" 38dda85211SBlue Swirldisable qemu_vmalloc(size_t size, void *ptr) "size %zu ptr %p" 39cd245a19SStefan Hajnoczidisable qemu_vfree(void *ptr) "ptr %p" 406d519a5fSStefan Hajnoczi 4164979a4dSStefan Hajnoczi# hw/virtio.c 4264979a4dSStefan Hajnoczidisable virtqueue_fill(void *vq, const void *elem, unsigned int len, unsigned int idx) "vq %p elem %p len %u idx %u" 4364979a4dSStefan Hajnoczidisable virtqueue_flush(void *vq, unsigned int count) "vq %p count %u" 4464979a4dSStefan Hajnoczidisable virtqueue_pop(void *vq, void *elem, unsigned int in_num, unsigned int out_num) "vq %p elem %p in_num %u out_num %u" 4564979a4dSStefan Hajnoczidisable virtio_queue_notify(void *vdev, int n, void *vq) "vdev %p n %d vq %p" 4664979a4dSStefan Hajnoczidisable virtio_irq(void *vq) "vq %p" 4764979a4dSStefan Hajnoczidisable virtio_notify(void *vdev, void *vq) "vdev %p vq %p" 4864979a4dSStefan Hajnoczi 496d519a5fSStefan Hajnoczi# block.c 506d519a5fSStefan Hajnoczidisable multiwrite_cb(void *mcb, int ret) "mcb %p ret %d" 516d519a5fSStefan Hajnoczidisable bdrv_aio_multiwrite(void *mcb, int num_callbacks, int num_reqs) "mcb %p num_callbacks %d num_reqs %d" 526d519a5fSStefan Hajnoczidisable bdrv_aio_multiwrite_earlyfail(void *mcb) "mcb %p" 536d519a5fSStefan Hajnoczidisable bdrv_aio_multiwrite_latefail(void *mcb, int i) "mcb %p i %d" 54bbf0a440SStefan Hajnoczidisable bdrv_aio_readv(void *bs, int64_t sector_num, int nb_sectors, void *opaque) "bs %p sector_num %"PRId64" nb_sectors %d opaque %p" 55bbf0a440SStefan Hajnoczidisable bdrv_aio_writev(void *bs, int64_t sector_num, int nb_sectors, void *opaque) "bs %p sector_num %"PRId64" nb_sectors %d opaque %p" 566d519a5fSStefan Hajnoczi 576d519a5fSStefan Hajnoczi# hw/virtio-blk.c 586d519a5fSStefan Hajnoczidisable virtio_blk_req_complete(void *req, int status) "req %p status %d" 596d519a5fSStefan Hajnoczidisable virtio_blk_rw_complete(void *req, int ret) "req %p ret %d" 609a85d394SStefan Hajnoczidisable virtio_blk_handle_write(void *req, uint64_t sector, size_t nsectors) "req %p sector %"PRIu64" nsectors %zu" 616d519a5fSStefan Hajnoczi 626d519a5fSStefan Hajnoczi# posix-aio-compat.c 639a85d394SStefan Hajnoczidisable paio_submit(void *acb, void *opaque, int64_t sector_num, int nb_sectors, int type) "acb %p opaque %p sector_num %"PRId64" nb_sectors %d type %d" 64bd3c9aa5SPrerna Saxena 65bd3c9aa5SPrerna Saxena# ioport.c 66bd3c9aa5SPrerna Saxenadisable cpu_in(unsigned int addr, unsigned int val) "addr %#x value %u" 67bd3c9aa5SPrerna Saxenadisable cpu_out(unsigned int addr, unsigned int val) "addr %#x value %u" 6862dd89deSPrerna Saxena 6962dd89deSPrerna Saxena# balloon.c 7062dd89deSPrerna Saxena# Since requests are raised via monitor, not many tracepoints are needed. 7162dd89deSPrerna Saxenadisable balloon_event(void *opaque, unsigned long addr) "opaque %p addr %lu" 72d8023f31SBlue Swirl 73d8023f31SBlue Swirl# hw/apic.c 74d8023f31SBlue Swirldisable apic_local_deliver(int vector, uint32_t lvt) "vector %d delivery mode %d" 75d8023f31SBlue Swirldisable apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode, uint8_t vector_num, uint8_t polarity, uint8_t trigger_mode) "dest %d dest_mode %d delivery_mode %d vector %d polarity %d trigger_mode %d" 76d8023f31SBlue Swirldisable cpu_set_apic_base(uint64_t val) "%016"PRIx64"" 77d8023f31SBlue Swirldisable cpu_get_apic_base(uint64_t val) "%016"PRIx64"" 78d8023f31SBlue Swirldisable apic_mem_readl(uint64_t addr, uint32_t val) "%"PRIx64" = %08x" 79d8023f31SBlue Swirldisable apic_mem_writel(uint64_t addr, uint32_t val) "%"PRIx64" = %08x" 80d8023f31SBlue Swirl# coalescing 81d8023f31SBlue Swirldisable apic_reset_irq_delivered(int apic_irq_delivered) "old coalescing %d" 82d8023f31SBlue Swirldisable apic_get_irq_delivered(int apic_irq_delivered) "returning coalescing %d" 83d8023f31SBlue Swirldisable apic_set_irq(int apic_irq_delivered) "coalescing %d" 84*97bf4851SBlue Swirl 85*97bf4851SBlue Swirl# hw/cs4231.c 86*97bf4851SBlue Swirldisable cs4231_mem_readl_dreg(uint32_t reg, uint32_t ret) "read dreg %d: 0x%02x" 87*97bf4851SBlue Swirldisable cs4231_mem_readl_reg(uint32_t reg, uint32_t ret) "read reg %d: 0x%08x" 88*97bf4851SBlue Swirldisable cs4231_mem_writel_reg(uint32_t reg, uint32_t old, uint32_t val) "write reg %d: 0x%08x -> 0x%08x" 89*97bf4851SBlue Swirldisable cs4231_mem_writel_dreg(uint32_t reg, uint32_t old, uint32_t val) "write dreg %d: 0x%02x -> 0x%02x" 90*97bf4851SBlue Swirl 91*97bf4851SBlue Swirl# hw/eccmemctl.c 92*97bf4851SBlue Swirldisable ecc_mem_writel_mer(uint32_t val) "Write memory enable %08x" 93*97bf4851SBlue Swirldisable ecc_mem_writel_mdr(uint32_t val) "Write memory delay %08x" 94*97bf4851SBlue Swirldisable ecc_mem_writel_mfsr(uint32_t val) "Write memory fault status %08x" 95*97bf4851SBlue Swirldisable ecc_mem_writel_vcr(uint32_t val) "Write slot configuration %08x" 96*97bf4851SBlue Swirldisable ecc_mem_writel_dr(uint32_t val) "Write diagnostic %08x" 97*97bf4851SBlue Swirldisable ecc_mem_writel_ecr0(uint32_t val) "Write event count 1 %08x" 98*97bf4851SBlue Swirldisable ecc_mem_writel_ecr1(uint32_t val) "Write event count 2 %08x" 99*97bf4851SBlue Swirldisable ecc_mem_readl_mer(uint32_t ret) "Read memory enable %08x" 100*97bf4851SBlue Swirldisable ecc_mem_readl_mdr(uint32_t ret) "Read memory delay %08x" 101*97bf4851SBlue Swirldisable ecc_mem_readl_mfsr(uint32_t ret) "Read memory fault status %08x" 102*97bf4851SBlue Swirldisable ecc_mem_readl_vcr(uint32_t ret) "Read slot configuration %08x" 103*97bf4851SBlue Swirldisable ecc_mem_readl_mfar0(uint32_t ret) "Read memory fault address 0 %08x" 104*97bf4851SBlue Swirldisable ecc_mem_readl_mfar1(uint32_t ret) "Read memory fault address 1 %08x" 105*97bf4851SBlue Swirldisable ecc_mem_readl_dr(uint32_t ret) "Read diagnostic %08x" 106*97bf4851SBlue Swirldisable ecc_mem_readl_ecr0(uint32_t ret) "Read event count 1 %08x" 107*97bf4851SBlue Swirldisable ecc_mem_readl_ecr1(uint32_t ret) "Read event count 2 %08x" 108*97bf4851SBlue Swirldisable ecc_diag_mem_writeb(uint64_t addr, uint32_t val) "Write diagnostic %"PRId64" = %02x" 109*97bf4851SBlue Swirldisable ecc_diag_mem_readb(uint64_t addr, uint32_t ret) "Read diagnostic %"PRId64"= %02x" 110*97bf4851SBlue Swirl 111*97bf4851SBlue Swirl# hw/lance.c 112*97bf4851SBlue Swirldisable lance_mem_readw(uint64_t addr, uint32_t ret) "addr=%"PRIx64"val=0x%04x" 113*97bf4851SBlue Swirldisable lance_mem_writew(uint64_t addr, uint32_t val) "addr=%"PRIx64"val=0x%04x" 114*97bf4851SBlue Swirl 115*97bf4851SBlue Swirl# hw/slavio_intctl.c 116*97bf4851SBlue Swirldisable slavio_intctl_mem_readl(uint32_t cpu, uint64_t addr, uint32_t ret) "read cpu %d reg 0x%"PRIx64" = %x" 117*97bf4851SBlue Swirldisable slavio_intctl_mem_writel(uint32_t cpu, uint64_t addr, uint32_t val) "write cpu %d reg 0x%"PRIx64" = %x" 118*97bf4851SBlue Swirldisable slavio_intctl_mem_writel_clear(uint32_t cpu, uint32_t val, uint32_t intreg_pending) "Cleared cpu %d irq mask %x, curmask %x" 119*97bf4851SBlue Swirldisable slavio_intctl_mem_writel_set(uint32_t cpu, uint32_t val, uint32_t intreg_pending) "Set cpu %d irq mask %x, curmask %x" 120*97bf4851SBlue Swirldisable slavio_intctlm_mem_readl(uint64_t addr, uint32_t ret) "read system reg 0x%"PRIx64" = %x" 121*97bf4851SBlue Swirldisable slavio_intctlm_mem_writel(uint64_t addr, uint32_t val) "write system reg 0x%"PRIx64" = %x" 122*97bf4851SBlue Swirldisable slavio_intctlm_mem_writel_enable(uint32_t val, uint32_t intregm_disabled) "Enabled master irq mask %x, curmask %x" 123*97bf4851SBlue Swirldisable slavio_intctlm_mem_writel_disable(uint32_t val, uint32_t intregm_disabled) "Disabled master irq mask %x, curmask %x" 124*97bf4851SBlue Swirldisable slavio_intctlm_mem_writel_target(uint32_t cpu) "Set master irq cpu %d" 125*97bf4851SBlue Swirldisable slavio_check_interrupts(uint32_t pending, uint32_t intregm_disabled) "pending %x disabled %x" 126*97bf4851SBlue Swirldisable slavio_set_irq(uint32_t target_cpu, int irq, uint32_t pil, int level) "Set cpu %d irq %d -> pil %d level %d" 127*97bf4851SBlue Swirldisable slavio_set_timer_irq_cpu(int cpu, int level) "Set cpu %d local timer level %d" 128*97bf4851SBlue Swirl 129*97bf4851SBlue Swirl# hw/slavio_misc.c 130*97bf4851SBlue Swirldisable slavio_misc_update_irq_raise(void) "Raise IRQ" 131*97bf4851SBlue Swirldisable slavio_misc_update_irq_lower(void) "Lower IRQ" 132*97bf4851SBlue Swirldisable slavio_set_power_fail(int power_failing, uint8_t config) "Power fail: %d, config: %d" 133*97bf4851SBlue Swirldisable slavio_cfg_mem_writeb(uint32_t val) "Write config %02x" 134*97bf4851SBlue Swirldisable slavio_cfg_mem_readb(uint32_t ret) "Read config %02x" 135*97bf4851SBlue Swirldisable slavio_diag_mem_writeb(uint32_t val) "Write diag %02x" 136*97bf4851SBlue Swirldisable slavio_diag_mem_readb(uint32_t ret) "Read diag %02x" 137*97bf4851SBlue Swirldisable slavio_mdm_mem_writeb(uint32_t val) "Write modem control %02x" 138*97bf4851SBlue Swirldisable slavio_mdm_mem_readb(uint32_t ret) "Read modem control %02x" 139*97bf4851SBlue Swirldisable slavio_aux1_mem_writeb(uint32_t val) "Write aux1 %02x" 140*97bf4851SBlue Swirldisable slavio_aux1_mem_readb(uint32_t ret) "Read aux1 %02x" 141*97bf4851SBlue Swirldisable slavio_aux2_mem_writeb(uint32_t val) "Write aux2 %02x" 142*97bf4851SBlue Swirldisable slavio_aux2_mem_readb(uint32_t ret) "Read aux2 %02x" 143*97bf4851SBlue Swirldisable apc_mem_writeb(uint32_t val) "Write power management %02x" 144*97bf4851SBlue Swirldisable apc_mem_readb(uint32_t ret) "Read power management %02x" 145*97bf4851SBlue Swirldisable slavio_sysctrl_mem_writel(uint32_t val) "Write system control %08x" 146*97bf4851SBlue Swirldisable slavio_sysctrl_mem_readl(uint32_t ret) "Read system control %08x" 147*97bf4851SBlue Swirldisable slavio_led_mem_writew(uint32_t val) "Write diagnostic LED %04x" 148*97bf4851SBlue Swirldisable slavio_led_mem_readw(uint32_t ret) "Read diagnostic LED %04x" 149*97bf4851SBlue Swirl 150*97bf4851SBlue Swirl# hw/slavio_timer.c 151*97bf4851SBlue Swirldisable slavio_timer_get_out(uint64_t limit, uint32_t counthigh, uint32_t count) "limit %"PRIx64" count %x%08x" 152*97bf4851SBlue Swirldisable slavio_timer_irq(uint32_t counthigh, uint32_t count) "callback: count %x%08x" 153*97bf4851SBlue Swirldisable slavio_timer_mem_readl_invalid(uint64_t addr) "invalid read address %"PRIx64"" 154*97bf4851SBlue Swirldisable slavio_timer_mem_readl(uint64_t addr, uint32_t ret) "read %"PRIx64" = %08x" 155*97bf4851SBlue Swirldisable slavio_timer_mem_writel(uint64_t addr, uint32_t val) "write %"PRIx64" = %08x" 156*97bf4851SBlue Swirldisable slavio_timer_mem_writel_limit(unsigned int timer_index, uint64_t count) "processor %d user timer set to %016"PRIx64"" 157*97bf4851SBlue Swirldisable slavio_timer_mem_writel_counter_invalid(void) "not user timer" 158*97bf4851SBlue Swirldisable slavio_timer_mem_writel_status_start(unsigned int timer_index) "processor %d user timer started" 159*97bf4851SBlue Swirldisable slavio_timer_mem_writel_status_stop(unsigned int timer_index) "processor %d user timer stopped" 160*97bf4851SBlue Swirldisable slavio_timer_mem_writel_mode_user(unsigned int timer_index) "processor %d changed from counter to user timer" 161*97bf4851SBlue Swirldisable slavio_timer_mem_writel_mode_counter(unsigned int timer_index) "processor %d changed from user timer to counter" 162*97bf4851SBlue Swirldisable slavio_timer_mem_writel_mode_invalid(void) "not system timer" 163*97bf4851SBlue Swirldisable slavio_timer_mem_writel_invalid(uint64_t addr) "invalid write address %"PRIx64"" 164*97bf4851SBlue Swirl 165*97bf4851SBlue Swirl# hw/sparc32_dma.c 166*97bf4851SBlue Swirldisable ledma_memory_read(uint64_t addr) "DMA read addr 0x%"PRIx64"" 167*97bf4851SBlue Swirldisable ledma_memory_write(uint64_t addr) "DMA write addr 0x%"PRIx64"" 168*97bf4851SBlue Swirldisable sparc32_dma_set_irq_raise(void) "Raise IRQ" 169*97bf4851SBlue Swirldisable sparc32_dma_set_irq_lower(void) "Lower IRQ" 170*97bf4851SBlue Swirldisable espdma_memory_read(uint32_t addr) "DMA read addr 0x%08x" 171*97bf4851SBlue Swirldisable espdma_memory_write(uint32_t addr) "DMA write addr 0x%08x" 172*97bf4851SBlue Swirldisable sparc32_dma_mem_readl(uint64_t addr, uint32_t ret) "read dmareg %"PRIx64": 0x%08x" 173*97bf4851SBlue Swirldisable sparc32_dma_mem_writel(uint64_t addr, uint32_t old, uint32_t val) "write dmareg %"PRIx64": 0x%08x -> 0x%08x" 174*97bf4851SBlue Swirldisable sparc32_dma_enable_raise(void) "Raise DMA enable" 175*97bf4851SBlue Swirldisable sparc32_dma_enable_lower(void) "Lower DMA enable" 176*97bf4851SBlue Swirl 177*97bf4851SBlue Swirl# hw/sun4m.c 178*97bf4851SBlue Swirldisable sun4m_cpu_interrupt(unsigned int level) "Set CPU IRQ %d" 179*97bf4851SBlue Swirldisable sun4m_cpu_reset_interrupt(unsigned int level) "Reset CPU IRQ %d" 180*97bf4851SBlue Swirldisable sun4m_cpu_set_irq_raise(int level) "Raise CPU IRQ %d" 181*97bf4851SBlue Swirldisable sun4m_cpu_set_irq_lower(int level) "Lower CPU IRQ %d" 182*97bf4851SBlue Swirl 183*97bf4851SBlue Swirl# hw/sun4m_iommu.c 184*97bf4851SBlue Swirldisable sun4m_iommu_mem_readl(uint64_t addr, uint32_t ret) "read reg[%"PRIx64"] = %x" 185*97bf4851SBlue Swirldisable sun4m_iommu_mem_writel(uint64_t addr, uint32_t val) "write reg[%"PRIx64"] = %x" 186*97bf4851SBlue Swirldisable sun4m_iommu_mem_writel_ctrl(uint64_t iostart) "iostart = %"PRIx64"" 187*97bf4851SBlue Swirldisable sun4m_iommu_mem_writel_tlbflush(uint32_t val) "tlb flush %x" 188*97bf4851SBlue Swirldisable sun4m_iommu_mem_writel_pgflush(uint32_t val) "page flush %x" 189*97bf4851SBlue Swirldisable sun4m_iommu_page_get_flags(uint64_t pa, uint64_t iopte, uint32_t ret) "get flags addr %"PRIx64" => pte %"PRIx64", *pte = %x" 190*97bf4851SBlue Swirldisable sun4m_iommu_translate_pa(uint64_t addr, uint64_t pa, uint32_t iopte) "xlate dva %"PRIx64" => pa %"PRIx64" iopte = %x" 191*97bf4851SBlue Swirldisable sun4m_iommu_bad_addr(uint64_t addr) "bad addr %"PRIx64"" 192