xref: /qemu/trace-events (revision 47f08d7a9ddced79d08aa9ad69fe2ddfadd4f791)
194a420b1SStefan Hajnoczi# Trace events for debugging and performance instrumentation
294a420b1SStefan Hajnoczi#
394a420b1SStefan Hajnoczi# This file is processed by the tracetool script during the build.
494a420b1SStefan Hajnoczi#
594a420b1SStefan Hajnoczi# To add a new trace event:
694a420b1SStefan Hajnoczi#
794a420b1SStefan Hajnoczi# 1. Choose a name for the trace event.  Declare its arguments and format
894a420b1SStefan Hajnoczi#    string.
994a420b1SStefan Hajnoczi#
1094a420b1SStefan Hajnoczi# 2. Call the trace event from code using trace_##name, e.g. multiwrite_cb() ->
1194a420b1SStefan Hajnoczi#    trace_multiwrite_cb().  The source file must #include "trace.h".
1294a420b1SStefan Hajnoczi#
1394a420b1SStefan Hajnoczi# Format of a trace event:
1494a420b1SStefan Hajnoczi#
151e2cf2bcSStefan Hajnoczi# [disable] <name>(<type1> <arg1>[, <type2> <arg2>] ...) "<format-string>"
1694a420b1SStefan Hajnoczi#
1794a420b1SStefan Hajnoczi# Example: qemu_malloc(size_t size) "size %zu"
1894a420b1SStefan Hajnoczi#
191e2cf2bcSStefan Hajnoczi# The "disable" keyword will build without the trace event.
201e2cf2bcSStefan Hajnoczi#
2194a420b1SStefan Hajnoczi# The <name> must be a valid as a C function name.
2294a420b1SStefan Hajnoczi#
2394a420b1SStefan Hajnoczi# Types should be standard C types.  Use void * for pointers because the trace
2494a420b1SStefan Hajnoczi# system may not have the necessary headers included.
2594a420b1SStefan Hajnoczi#
2694a420b1SStefan Hajnoczi# The <format-string> should be a sprintf()-compatible format string.
27cd245a19SStefan Hajnoczi
28cd245a19SStefan Hajnoczi# qemu-malloc.c
29*47f08d7aSLluísqemu_malloc(size_t size, void *ptr) "size %zu ptr %p"
30*47f08d7aSLluísqemu_realloc(void *ptr, size_t size, void *newptr) "ptr %p size %zu newptr %p"
31*47f08d7aSLluísqemu_free(void *ptr) "ptr %p"
32cd245a19SStefan Hajnoczi
33cd245a19SStefan Hajnoczi# osdep.c
34*47f08d7aSLluísqemu_memalign(size_t alignment, size_t size, void *ptr) "alignment %zu size %zu ptr %p"
35*47f08d7aSLluísqemu_vmalloc(size_t size, void *ptr) "size %zu ptr %p"
36*47f08d7aSLluísqemu_vfree(void *ptr) "ptr %p"
376d519a5fSStefan Hajnoczi
3864979a4dSStefan Hajnoczi# hw/virtio.c
39*47f08d7aSLluísvirtqueue_fill(void *vq, const void *elem, unsigned int len, unsigned int idx) "vq %p elem %p len %u idx %u"
40*47f08d7aSLluísvirtqueue_flush(void *vq, unsigned int count) "vq %p count %u"
41*47f08d7aSLluísvirtqueue_pop(void *vq, void *elem, unsigned int in_num, unsigned int out_num) "vq %p elem %p in_num %u out_num %u"
42*47f08d7aSLluísvirtio_queue_notify(void *vdev, int n, void *vq) "vdev %p n %d vq %p"
43*47f08d7aSLluísvirtio_irq(void *vq) "vq %p"
44*47f08d7aSLluísvirtio_notify(void *vdev, void *vq) "vdev %p vq %p"
4564979a4dSStefan Hajnoczi
4649e3fdd7SAmit Shah# hw/virtio-serial-bus.c
47*47f08d7aSLluísvirtio_serial_send_control_event(unsigned int port, uint16_t event, uint16_t value) "port %u, event %u, value %u"
48*47f08d7aSLluísvirtio_serial_throttle_port(unsigned int port, bool throttle) "port %u, throttle %d"
49*47f08d7aSLluísvirtio_serial_handle_control_message(uint16_t event, uint16_t value) "event %u, value %u"
50*47f08d7aSLluísvirtio_serial_handle_control_message_port(unsigned int port) "port %u"
5149e3fdd7SAmit Shah
52d02e4fa4SAmit Shah# hw/virtio-console.c
53*47f08d7aSLluísvirtio_console_flush_buf(unsigned int port, size_t len, ssize_t ret) "port %u, in_len %zu, out_len %zd"
54*47f08d7aSLluísvirtio_console_chr_read(unsigned int port, int size) "port %u, size %d"
55*47f08d7aSLluísvirtio_console_chr_event(unsigned int port, int event) "port %u, event %d"
56d02e4fa4SAmit Shah
576d519a5fSStefan Hajnoczi# block.c
58*47f08d7aSLluísmultiwrite_cb(void *mcb, int ret) "mcb %p ret %d"
59*47f08d7aSLluísbdrv_aio_multiwrite(void *mcb, int num_callbacks, int num_reqs) "mcb %p num_callbacks %d num_reqs %d"
60*47f08d7aSLluísbdrv_aio_multiwrite_earlyfail(void *mcb) "mcb %p"
61*47f08d7aSLluísbdrv_aio_multiwrite_latefail(void *mcb, int i) "mcb %p i %d"
62*47f08d7aSLluísbdrv_aio_flush(void *bs, void *opaque) "bs %p opaque %p"
63*47f08d7aSLluísbdrv_aio_readv(void *bs, int64_t sector_num, int nb_sectors, void *opaque) "bs %p sector_num %"PRId64" nb_sectors %d opaque %p"
64*47f08d7aSLluísbdrv_aio_writev(void *bs, int64_t sector_num, int nb_sectors, void *opaque) "bs %p sector_num %"PRId64" nb_sectors %d opaque %p"
65*47f08d7aSLluísbdrv_set_locked(void *bs, int locked) "bs %p locked %d"
66*47f08d7aSLluísbdrv_co_readv(void *bs, int64_t sector_num, int nb_sector) "bs %p sector_num %"PRId64" nb_sectors %d"
67*47f08d7aSLluísbdrv_co_writev(void *bs, int64_t sector_num, int nb_sector) "bs %p sector_num %"PRId64" nb_sectors %d"
68*47f08d7aSLluísbdrv_co_io(int is_write, void *acb) "is_write %d acb %p"
696d519a5fSStefan Hajnoczi
706d519a5fSStefan Hajnoczi# hw/virtio-blk.c
71*47f08d7aSLluísvirtio_blk_req_complete(void *req, int status) "req %p status %d"
72*47f08d7aSLluísvirtio_blk_rw_complete(void *req, int ret) "req %p ret %d"
73*47f08d7aSLluísvirtio_blk_handle_write(void *req, uint64_t sector, size_t nsectors) "req %p sector %"PRIu64" nsectors %zu"
746d519a5fSStefan Hajnoczi
756d519a5fSStefan Hajnoczi# posix-aio-compat.c
76*47f08d7aSLluíspaio_submit(void *acb, void *opaque, int64_t sector_num, int nb_sectors, int type) "acb %p opaque %p sector_num %"PRId64" nb_sectors %d type %d"
77*47f08d7aSLluíspaio_complete(void *acb, void *opaque, int ret) "acb %p opaque %p ret %d"
78*47f08d7aSLluíspaio_cancel(void *acb, void *opaque) "acb %p opaque %p"
79bd3c9aa5SPrerna Saxena
80bd3c9aa5SPrerna Saxena# ioport.c
81*47f08d7aSLluíscpu_in(unsigned int addr, unsigned int val) "addr %#x value %u"
82*47f08d7aSLluíscpu_out(unsigned int addr, unsigned int val) "addr %#x value %u"
8362dd89deSPrerna Saxena
8462dd89deSPrerna Saxena# balloon.c
8562dd89deSPrerna Saxena# Since requests are raised via monitor, not many tracepoints are needed.
86*47f08d7aSLluísballoon_event(void *opaque, unsigned long addr) "opaque %p addr %lu"
87d8023f31SBlue Swirl
88d8023f31SBlue Swirl# hw/apic.c
89*47f08d7aSLluísapic_local_deliver(int vector, uint32_t lvt) "vector %d delivery mode %d"
90*47f08d7aSLluísapic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode, uint8_t vector_num, uint8_t trigger_mode) "dest %d dest_mode %d delivery_mode %d vector %d trigger_mode %d"
91*47f08d7aSLluíscpu_set_apic_base(uint64_t val) "%016"PRIx64""
92*47f08d7aSLluíscpu_get_apic_base(uint64_t val) "%016"PRIx64""
93*47f08d7aSLluísapic_mem_readl(uint64_t addr, uint32_t val)  "%"PRIx64" = %08x"
94*47f08d7aSLluísapic_mem_writel(uint64_t addr, uint32_t val) "%"PRIx64" = %08x"
95d8023f31SBlue Swirl# coalescing
96*47f08d7aSLluísapic_reset_irq_delivered(int apic_irq_delivered) "old coalescing %d"
97*47f08d7aSLluísapic_get_irq_delivered(int apic_irq_delivered) "returning coalescing %d"
98*47f08d7aSLluísapic_set_irq(int apic_irq_delivered) "coalescing %d"
9997bf4851SBlue Swirl
10097bf4851SBlue Swirl# hw/cs4231.c
101*47f08d7aSLluíscs4231_mem_readl_dreg(uint32_t reg, uint32_t ret) "read dreg %d: 0x%02x"
102*47f08d7aSLluíscs4231_mem_readl_reg(uint32_t reg, uint32_t ret) "read reg %d: 0x%08x"
103*47f08d7aSLluíscs4231_mem_writel_reg(uint32_t reg, uint32_t old, uint32_t val) "write reg %d: 0x%08x -> 0x%08x"
104*47f08d7aSLluíscs4231_mem_writel_dreg(uint32_t reg, uint32_t old, uint32_t val) "write dreg %d: 0x%02x -> 0x%02x"
10597bf4851SBlue Swirl
106d43ed9ecSHervé Poussineau# hw/ds1225y.c
107*47f08d7aSLluísnvram_read(uint32_t addr, uint32_t ret) "read addr %d: 0x%02x"
108*47f08d7aSLluísnvram_write(uint32_t addr, uint32_t old, uint32_t val) "write addr %d: 0x%02x -> 0x%02x"
109d43ed9ecSHervé Poussineau
11097bf4851SBlue Swirl# hw/eccmemctl.c
111*47f08d7aSLluísecc_mem_writel_mer(uint32_t val) "Write memory enable %08x"
112*47f08d7aSLluísecc_mem_writel_mdr(uint32_t val) "Write memory delay %08x"
113*47f08d7aSLluísecc_mem_writel_mfsr(uint32_t val) "Write memory fault status %08x"
114*47f08d7aSLluísecc_mem_writel_vcr(uint32_t val) "Write slot configuration %08x"
115*47f08d7aSLluísecc_mem_writel_dr(uint32_t val) "Write diagnostic %08x"
116*47f08d7aSLluísecc_mem_writel_ecr0(uint32_t val) "Write event count 1 %08x"
117*47f08d7aSLluísecc_mem_writel_ecr1(uint32_t val) "Write event count 2 %08x"
118*47f08d7aSLluísecc_mem_readl_mer(uint32_t ret) "Read memory enable %08x"
119*47f08d7aSLluísecc_mem_readl_mdr(uint32_t ret) "Read memory delay %08x"
120*47f08d7aSLluísecc_mem_readl_mfsr(uint32_t ret) "Read memory fault status %08x"
121*47f08d7aSLluísecc_mem_readl_vcr(uint32_t ret) "Read slot configuration %08x"
122*47f08d7aSLluísecc_mem_readl_mfar0(uint32_t ret) "Read memory fault address 0 %08x"
123*47f08d7aSLluísecc_mem_readl_mfar1(uint32_t ret) "Read memory fault address 1 %08x"
124*47f08d7aSLluísecc_mem_readl_dr(uint32_t ret) "Read diagnostic %08x"
125*47f08d7aSLluísecc_mem_readl_ecr0(uint32_t ret) "Read event count 1 %08x"
126*47f08d7aSLluísecc_mem_readl_ecr1(uint32_t ret) "Read event count 2 %08x"
127*47f08d7aSLluísecc_diag_mem_writeb(uint64_t addr, uint32_t val) "Write diagnostic %"PRId64" = %02x"
128*47f08d7aSLluísecc_diag_mem_readb(uint64_t addr, uint32_t ret) "Read diagnostic %"PRId64"= %02x"
12997bf4851SBlue Swirl
13097bf4851SBlue Swirl# hw/lance.c
131*47f08d7aSLluíslance_mem_readw(uint64_t addr, uint32_t ret) "addr=%"PRIx64"val=0x%04x"
132*47f08d7aSLluíslance_mem_writew(uint64_t addr, uint32_t val) "addr=%"PRIx64"val=0x%04x"
13397bf4851SBlue Swirl
13497bf4851SBlue Swirl# hw/slavio_intctl.c
135*47f08d7aSLluísslavio_intctl_mem_readl(uint32_t cpu, uint64_t addr, uint32_t ret) "read cpu %d reg 0x%"PRIx64" = %x"
136*47f08d7aSLluísslavio_intctl_mem_writel(uint32_t cpu, uint64_t addr, uint32_t val) "write cpu %d reg 0x%"PRIx64" = %x"
137*47f08d7aSLluísslavio_intctl_mem_writel_clear(uint32_t cpu, uint32_t val, uint32_t intreg_pending) "Cleared cpu %d irq mask %x, curmask %x"
138*47f08d7aSLluísslavio_intctl_mem_writel_set(uint32_t cpu, uint32_t val, uint32_t intreg_pending) "Set cpu %d irq mask %x, curmask %x"
139*47f08d7aSLluísslavio_intctlm_mem_readl(uint64_t addr, uint32_t ret) "read system reg 0x%"PRIx64" = %x"
140*47f08d7aSLluísslavio_intctlm_mem_writel(uint64_t addr, uint32_t val) "write system reg 0x%"PRIx64" = %x"
141*47f08d7aSLluísslavio_intctlm_mem_writel_enable(uint32_t val, uint32_t intregm_disabled) "Enabled master irq mask %x, curmask %x"
142*47f08d7aSLluísslavio_intctlm_mem_writel_disable(uint32_t val, uint32_t intregm_disabled) "Disabled master irq mask %x, curmask %x"
143*47f08d7aSLluísslavio_intctlm_mem_writel_target(uint32_t cpu) "Set master irq cpu %d"
144*47f08d7aSLluísslavio_check_interrupts(uint32_t pending, uint32_t intregm_disabled) "pending %x disabled %x"
145*47f08d7aSLluísslavio_set_irq(uint32_t target_cpu, int irq, uint32_t pil, int level) "Set cpu %d irq %d -> pil %d level %d"
146*47f08d7aSLluísslavio_set_timer_irq_cpu(int cpu, int level) "Set cpu %d local timer level %d"
14797bf4851SBlue Swirl
14897bf4851SBlue Swirl# hw/slavio_misc.c
149*47f08d7aSLluísslavio_misc_update_irq_raise(void) "Raise IRQ"
150*47f08d7aSLluísslavio_misc_update_irq_lower(void) "Lower IRQ"
151*47f08d7aSLluísslavio_set_power_fail(int power_failing, uint8_t config) "Power fail: %d, config: %d"
152*47f08d7aSLluísslavio_cfg_mem_writeb(uint32_t val) "Write config %02x"
153*47f08d7aSLluísslavio_cfg_mem_readb(uint32_t ret) "Read config %02x"
154*47f08d7aSLluísslavio_diag_mem_writeb(uint32_t val) "Write diag %02x"
155*47f08d7aSLluísslavio_diag_mem_readb(uint32_t ret) "Read diag %02x"
156*47f08d7aSLluísslavio_mdm_mem_writeb(uint32_t val) "Write modem control %02x"
157*47f08d7aSLluísslavio_mdm_mem_readb(uint32_t ret) "Read modem control %02x"
158*47f08d7aSLluísslavio_aux1_mem_writeb(uint32_t val) "Write aux1 %02x"
159*47f08d7aSLluísslavio_aux1_mem_readb(uint32_t ret) "Read aux1 %02x"
160*47f08d7aSLluísslavio_aux2_mem_writeb(uint32_t val) "Write aux2 %02x"
161*47f08d7aSLluísslavio_aux2_mem_readb(uint32_t ret) "Read aux2 %02x"
162*47f08d7aSLluísapc_mem_writeb(uint32_t val) "Write power management %02x"
163*47f08d7aSLluísapc_mem_readb(uint32_t ret) "Read power management %02x"
164*47f08d7aSLluísslavio_sysctrl_mem_writel(uint32_t val) "Write system control %08x"
165*47f08d7aSLluísslavio_sysctrl_mem_readl(uint32_t ret) "Read system control %08x"
166*47f08d7aSLluísslavio_led_mem_writew(uint32_t val) "Write diagnostic LED %04x"
167*47f08d7aSLluísslavio_led_mem_readw(uint32_t ret) "Read diagnostic LED %04x"
16897bf4851SBlue Swirl
16997bf4851SBlue Swirl# hw/slavio_timer.c
170*47f08d7aSLluísslavio_timer_get_out(uint64_t limit, uint32_t counthigh, uint32_t count) "limit %"PRIx64" count %x%08x"
171*47f08d7aSLluísslavio_timer_irq(uint32_t counthigh, uint32_t count) "callback: count %x%08x"
172*47f08d7aSLluísslavio_timer_mem_readl_invalid(uint64_t addr) "invalid read address %"PRIx64""
173*47f08d7aSLluísslavio_timer_mem_readl(uint64_t addr, uint32_t ret) "read %"PRIx64" = %08x"
174*47f08d7aSLluísslavio_timer_mem_writel(uint64_t addr, uint32_t val) "write %"PRIx64" = %08x"
175*47f08d7aSLluísslavio_timer_mem_writel_limit(unsigned int timer_index, uint64_t count) "processor %d user timer set to %016"PRIx64""
176*47f08d7aSLluísslavio_timer_mem_writel_counter_invalid(void) "not user timer"
177*47f08d7aSLluísslavio_timer_mem_writel_status_start(unsigned int timer_index) "processor %d user timer started"
178*47f08d7aSLluísslavio_timer_mem_writel_status_stop(unsigned int timer_index) "processor %d user timer stopped"
179*47f08d7aSLluísslavio_timer_mem_writel_mode_user(unsigned int timer_index) "processor %d changed from counter to user timer"
180*47f08d7aSLluísslavio_timer_mem_writel_mode_counter(unsigned int timer_index) "processor %d changed from user timer to counter"
181*47f08d7aSLluísslavio_timer_mem_writel_mode_invalid(void) "not system timer"
182*47f08d7aSLluísslavio_timer_mem_writel_invalid(uint64_t addr) "invalid write address %"PRIx64""
18397bf4851SBlue Swirl
18497bf4851SBlue Swirl# hw/sparc32_dma.c
185*47f08d7aSLluísledma_memory_read(uint64_t addr) "DMA read addr 0x%"PRIx64""
186*47f08d7aSLluísledma_memory_write(uint64_t addr) "DMA write addr 0x%"PRIx64""
187*47f08d7aSLluíssparc32_dma_set_irq_raise(void) "Raise IRQ"
188*47f08d7aSLluíssparc32_dma_set_irq_lower(void) "Lower IRQ"
189*47f08d7aSLluísespdma_memory_read(uint32_t addr) "DMA read addr 0x%08x"
190*47f08d7aSLluísespdma_memory_write(uint32_t addr) "DMA write addr 0x%08x"
191*47f08d7aSLluíssparc32_dma_mem_readl(uint64_t addr, uint32_t ret) "read dmareg %"PRIx64": 0x%08x"
192*47f08d7aSLluíssparc32_dma_mem_writel(uint64_t addr, uint32_t old, uint32_t val) "write dmareg %"PRIx64": 0x%08x -> 0x%08x"
193*47f08d7aSLluíssparc32_dma_enable_raise(void) "Raise DMA enable"
194*47f08d7aSLluíssparc32_dma_enable_lower(void) "Lower DMA enable"
19597bf4851SBlue Swirl
19697bf4851SBlue Swirl# hw/sun4m.c
197*47f08d7aSLluíssun4m_cpu_interrupt(unsigned int level) "Set CPU IRQ %d"
198*47f08d7aSLluíssun4m_cpu_reset_interrupt(unsigned int level) "Reset CPU IRQ %d"
199*47f08d7aSLluíssun4m_cpu_set_irq_raise(int level) "Raise CPU IRQ %d"
200*47f08d7aSLluíssun4m_cpu_set_irq_lower(int level) "Lower CPU IRQ %d"
20197bf4851SBlue Swirl
20297bf4851SBlue Swirl# hw/sun4m_iommu.c
203*47f08d7aSLluíssun4m_iommu_mem_readl(uint64_t addr, uint32_t ret) "read reg[%"PRIx64"] = %x"
204*47f08d7aSLluíssun4m_iommu_mem_writel(uint64_t addr, uint32_t val) "write reg[%"PRIx64"] = %x"
205*47f08d7aSLluíssun4m_iommu_mem_writel_ctrl(uint64_t iostart) "iostart = %"PRIx64""
206*47f08d7aSLluíssun4m_iommu_mem_writel_tlbflush(uint32_t val) "tlb flush %x"
207*47f08d7aSLluíssun4m_iommu_mem_writel_pgflush(uint32_t val) "page flush %x"
208*47f08d7aSLluíssun4m_iommu_page_get_flags(uint64_t pa, uint64_t iopte, uint32_t ret) "get flags addr %"PRIx64" => pte %"PRIx64", *pte = %x"
209*47f08d7aSLluíssun4m_iommu_translate_pa(uint64_t addr, uint64_t pa, uint32_t iopte) "xlate dva %"PRIx64" => pa %"PRIx64" iopte = %x"
210*47f08d7aSLluíssun4m_iommu_bad_addr(uint64_t addr) "bad addr %"PRIx64""
21194b0b5ffSStefan Hajnoczi
212439a97ccSGerd Hoffmann# hw/usb-ehci.c
213*47f08d7aSLluísusb_ehci_reset(void) "=== RESET ==="
214*47f08d7aSLluísusb_ehci_mmio_readl(uint32_t addr, const char *str, uint32_t val) "rd mmio %04x [%s] = %x"
215*47f08d7aSLluísusb_ehci_mmio_writel(uint32_t addr, const char *str, uint32_t val) "wr mmio %04x [%s] = %x"
216*47f08d7aSLluísusb_ehci_mmio_change(uint32_t addr, const char *str, uint32_t new, uint32_t old) "ch mmio %04x [%s] = %x (old: %x)"
217*47f08d7aSLluísusb_ehci_usbsts(const char *sts, int state) "usbsts %s %d"
218*47f08d7aSLluísusb_ehci_state(const char *schedule, const char *state) "%s schedule %s"
219*47f08d7aSLluísusb_ehci_qh_ptrs(void *q, uint32_t addr, uint32_t nxt, uint32_t c_qtd, uint32_t n_qtd, uint32_t a_qtd) "q %p - QH @ %08x: next %08x qtds %08x,%08x,%08x"
220*47f08d7aSLluísusb_ehci_qh_fields(uint32_t addr, int rl, int mplen, int eps, int ep, int devaddr) "QH @ %08x - rl %d, mplen %d, eps %d, ep %d, dev %d"
221*47f08d7aSLluísusb_ehci_qh_bits(uint32_t addr, int c, int h, int dtc, int i) "QH @ %08x - c %d, h %d, dtc %d, i %d"
222*47f08d7aSLluísusb_ehci_qtd_ptrs(void *q, uint32_t addr, uint32_t nxt, uint32_t altnext) "q %p - QTD @ %08x: next %08x altnext %08x"
223*47f08d7aSLluísusb_ehci_qtd_fields(uint32_t addr, int tbytes, int cpage, int cerr, int pid) "QTD @ %08x - tbytes %d, cpage %d, cerr %d, pid %d"
224*47f08d7aSLluísusb_ehci_qtd_bits(uint32_t addr, int ioc, int active, int halt, int babble, int xacterr) "QTD @ %08x - ioc %d, active %d, halt %d, babble %d, xacterr %d"
225*47f08d7aSLluísusb_ehci_itd(uint32_t addr, uint32_t nxt, uint32_t mplen, uint32_t mult, uint32_t ep, uint32_t devaddr) "ITD @ %08x: next %08x - mplen %d, mult %d, ep %d, dev %d"
226*47f08d7aSLluísusb_ehci_port_attach(uint32_t port, const char *device) "attach port #%d - %s"
227*47f08d7aSLluísusb_ehci_port_detach(uint32_t port) "detach port #%d"
228*47f08d7aSLluísusb_ehci_port_reset(uint32_t port, int enable) "reset port #%d - %d"
229*47f08d7aSLluísusb_ehci_data(int rw, uint32_t cpage, uint32_t offset, uint32_t addr, uint32_t len, uint32_t bufpos) "write %d, cpage %d, offset 0x%03x, addr 0x%08x, len %d, bufpos %d"
230*47f08d7aSLluísusb_ehci_queue_action(void *q, const char *action) "q %p: %s"
231439a97ccSGerd Hoffmann
23237fb59d3SGerd Hoffmann# hw/usb-desc.c
233*47f08d7aSLluísusb_desc_device(int addr, int len, int ret) "dev %d query device, len %d, ret %d"
234*47f08d7aSLluísusb_desc_device_qualifier(int addr, int len, int ret) "dev %d query device qualifier, len %d, ret %d"
235*47f08d7aSLluísusb_desc_config(int addr, int index, int len, int ret) "dev %d query config %d, len %d, ret %d"
236*47f08d7aSLluísusb_desc_other_speed_config(int addr, int index, int len, int ret) "dev %d query config %d, len %d, ret %d"
237*47f08d7aSLluísusb_desc_string(int addr, int index, int len, int ret) "dev %d query string %d, len %d, ret %d"
238*47f08d7aSLluísusb_set_addr(int addr) "dev %d"
239*47f08d7aSLluísusb_set_config(int addr, int config, int ret) "dev %d, config %d, ret %d"
240*47f08d7aSLluísusb_clear_device_feature(int addr, int feature, int ret) "dev %d, feature %d, ret %d"
241*47f08d7aSLluísusb_set_device_feature(int addr, int feature, int ret) "dev %d, feature %d, ret %d"
24237fb59d3SGerd Hoffmann
2435138efecSPaolo Bonzini# hw/scsi-bus.c
244*47f08d7aSLluísscsi_req_alloc(int target, int lun, int tag) "target %d lun %d tag %d"
245*47f08d7aSLluísscsi_req_data(int target, int lun, int tag, int len) "target %d lun %d tag %d len %d"
246*47f08d7aSLluísscsi_req_dequeue(int target, int lun, int tag) "target %d lun %d tag %d"
247*47f08d7aSLluísscsi_req_continue(int target, int lun, int tag) "target %d lun %d tag %d"
248*47f08d7aSLluísscsi_req_parsed(int target, int lun, int tag, int cmd, int mode, int xfer) "target %d lun %d tag %d command %d dir %d length %d"
249*47f08d7aSLluísscsi_req_parsed_lba(int target, int lun, int tag, int cmd, uint64_t lba) "target %d lun %d tag %d command %d lba %"PRIu64""
250*47f08d7aSLluísscsi_req_parse_bad(int target, int lun, int tag, int cmd) "target %d lun %d tag %d command %d"
251*47f08d7aSLluísscsi_req_build_sense(int target, int lun, int tag, int key, int asc, int ascq) "target %d lun %d tag %d key %#02x asc %#02x ascq %#02x"
252*47f08d7aSLluísscsi_report_luns(int target, int lun, int tag) "target %d lun %d tag %d"
253*47f08d7aSLluísscsi_inquiry(int target, int lun, int tag, int cdb1, int cdb2) "target %d lun %d tag %d page %#02x/%#02x"
254*47f08d7aSLluísscsi_test_unit_ready(int target, int lun, int tag) "target %d lun %d tag %d"
255*47f08d7aSLluísscsi_request_sense(int target, int lun, int tag) "target %d lun %d tag %d"
2565138efecSPaolo Bonzini
25794b0b5ffSStefan Hajnoczi# vl.c
258*47f08d7aSLluísvm_state_notify(int running, int reason) "running %d reason %d"
259298800caSStefan Hajnoczi
260298800caSStefan Hajnoczi# block/qed-l2-cache.c
261*47f08d7aSLluísqed_alloc_l2_cache_entry(void *l2_cache, void *entry) "l2_cache %p entry %p"
262*47f08d7aSLluísqed_unref_l2_cache_entry(void *entry, int ref) "entry %p ref %d"
263*47f08d7aSLluísqed_find_l2_cache_entry(void *l2_cache, void *entry, uint64_t offset, int ref) "l2_cache %p entry %p offset %"PRIu64" ref %d"
264298800caSStefan Hajnoczi
265298800caSStefan Hajnoczi# block/qed-table.c
266*47f08d7aSLluísqed_read_table(void *s, uint64_t offset, void *table) "s %p offset %"PRIu64" table %p"
267*47f08d7aSLluísqed_read_table_cb(void *s, void *table, int ret) "s %p table %p ret %d"
268*47f08d7aSLluísqed_write_table(void *s, uint64_t offset, void *table, unsigned int index, unsigned int n) "s %p offset %"PRIu64" table %p index %u n %u"
269*47f08d7aSLluísqed_write_table_cb(void *s, void *table, int flush, int ret) "s %p table %p flush %d ret %d"
270eabba580SStefan Hajnoczi
271eabba580SStefan Hajnoczi# block/qed.c
272*47f08d7aSLluísqed_need_check_timer_cb(void *s) "s %p"
273*47f08d7aSLluísqed_start_need_check_timer(void *s) "s %p"
274*47f08d7aSLluísqed_cancel_need_check_timer(void *s) "s %p"
275*47f08d7aSLluísqed_aio_complete(void *s, void *acb, int ret) "s %p acb %p ret %d"
276*47f08d7aSLluísqed_aio_setup(void *s, void *acb, int64_t sector_num, int nb_sectors, void *opaque, int is_write) "s %p acb %p sector_num %"PRId64" nb_sectors %d opaque %p is_write %d"
277*47f08d7aSLluísqed_aio_next_io(void *s, void *acb, int ret, uint64_t cur_pos) "s %p acb %p ret %d cur_pos %"PRIu64""
278*47f08d7aSLluísqed_aio_read_data(void *s, void *acb, int ret, uint64_t offset, size_t len) "s %p acb %p ret %d offset %"PRIu64" len %zu"
279*47f08d7aSLluísqed_aio_write_data(void *s, void *acb, int ret, uint64_t offset, size_t len) "s %p acb %p ret %d offset %"PRIu64" len %zu"
280*47f08d7aSLluísqed_aio_write_prefill(void *s, void *acb, uint64_t start, size_t len, uint64_t offset) "s %p acb %p start %"PRIu64" len %zu offset %"PRIu64""
281*47f08d7aSLluísqed_aio_write_postfill(void *s, void *acb, uint64_t start, size_t len, uint64_t offset) "s %p acb %p start %"PRIu64" len %zu offset %"PRIu64""
282*47f08d7aSLluísqed_aio_write_main(void *s, void *acb, int ret, uint64_t offset, size_t len) "s %p acb %p ret %d offset %"PRIu64" len %zu"
2830f3a4a01SFabien Chouteau
284b213b370SHervé Poussineau# hw/g364fb.c
285*47f08d7aSLluísg364fb_read(uint64_t addr, uint32_t val) "read addr=0x%"PRIx64": 0x%x"
286*47f08d7aSLluísg364fb_write(uint64_t addr, uint32_t new) "write addr=0x%"PRIx64": 0x%x"
287b213b370SHervé Poussineau
2880f3a4a01SFabien Chouteau# hw/grlib_gptimer.c
289*47f08d7aSLluísgrlib_gptimer_enable(int id, uint32_t count) "timer:%d set count 0x%x and run"
290*47f08d7aSLluísgrlib_gptimer_disabled(int id, uint32_t config) "timer:%d Timer disable config 0x%x"
291*47f08d7aSLluísgrlib_gptimer_restart(int id, uint32_t reload) "timer:%d reload val: 0x%x"
292*47f08d7aSLluísgrlib_gptimer_set_scaler(uint32_t scaler, uint32_t freq) "scaler:0x%x freq: 0x%x"
293*47f08d7aSLluísgrlib_gptimer_hit(int id) "timer:%d HIT"
294*47f08d7aSLluísgrlib_gptimer_readl(int id, uint64_t addr, uint32_t val) "timer:%d addr 0x%"PRIx64" 0x%x"
295*47f08d7aSLluísgrlib_gptimer_writel(int id, uint64_t addr, uint32_t val) "timer:%d addr 0x%"PRIx64" 0x%x"
2963f10bcbbSFabien Chouteau
2973f10bcbbSFabien Chouteau# hw/grlib_irqmp.c
298*47f08d7aSLluísgrlib_irqmp_check_irqs(uint32_t pend, uint32_t force, uint32_t mask, uint32_t lvl1, uint32_t lvl2) "pend:0x%04x force:0x%04x mask:0x%04x lvl1:0x%04x lvl0:0x%04x\n"
299*47f08d7aSLluísgrlib_irqmp_ack(int intno) "interrupt:%d"
300*47f08d7aSLluísgrlib_irqmp_set_irq(int irq) "Raise CPU IRQ %d"
301*47f08d7aSLluísgrlib_irqmp_readl_unknown(uint64_t addr) "addr 0x%"PRIx64""
302*47f08d7aSLluísgrlib_irqmp_writel_unknown(uint64_t addr, uint32_t value) "addr 0x%"PRIx64" value 0x%x"
3038b1e1320SFabien Chouteau
3048b1e1320SFabien Chouteau# hw/grlib_apbuart.c
305*47f08d7aSLluísgrlib_apbuart_event(int event) "event:%d"
306*47f08d7aSLluísgrlib_apbuart_writel_unknown(uint64_t addr, uint32_t value) "addr 0x%"PRIx64" value 0x%x"
307b04d9890SFabien Chouteau
308b04d9890SFabien Chouteau# hw/leon3.c
309*47f08d7aSLluísleon3_set_irq(int intno) "Set CPU IRQ %d"
310*47f08d7aSLluísleon3_reset_irq(int intno) "Reset CPU IRQ %d"
3119363ee31SAnthony Liguori
312cbcc6336SAlon Levy# spice-qemu-char.c
313*47f08d7aSLluísspice_vmc_write(ssize_t out, int len) "spice wrottn %zd of requested %d"
314*47f08d7aSLluísspice_vmc_read(int bytes, int len) "spice read %d of requested %d"
315*47f08d7aSLluísspice_vmc_register_interface(void *scd) "spice vmc registered interface %p"
316*47f08d7aSLluísspice_vmc_unregister_interface(void *scd) "spice vmc unregistered interface %p"
3174ef66fa7SMichael Walle
3184ef66fa7SMichael Walle# hw/lm32_pic.c
319*47f08d7aSLluíslm32_pic_raise_irq(void) "Raise CPU interrupt"
320*47f08d7aSLluíslm32_pic_lower_irq(void) "Lower CPU interrupt"
321*47f08d7aSLluíslm32_pic_interrupt(int irq, int level) "Set IRQ%d %d"
322*47f08d7aSLluíslm32_pic_set_im(uint32_t im) "im 0x%08x"
323*47f08d7aSLluíslm32_pic_set_ip(uint32_t ip) "ip 0x%08x"
324*47f08d7aSLluíslm32_pic_get_im(uint32_t im) "im 0x%08x"
325*47f08d7aSLluíslm32_pic_get_ip(uint32_t ip) "ip 0x%08x"
32615d7dc4fSMichael Walle
32715d7dc4fSMichael Walle# hw/lm32_juart.c
328*47f08d7aSLluíslm32_juart_get_jtx(uint32_t value) "jtx 0x%08x"
329*47f08d7aSLluíslm32_juart_set_jtx(uint32_t value) "jtx 0x%08x"
330*47f08d7aSLluíslm32_juart_get_jrx(uint32_t value) "jrx 0x%08x"
331*47f08d7aSLluíslm32_juart_set_jrx(uint32_t value) "jrx 0x%08x"
332ea7924dcSMichael Walle
333ea7924dcSMichael Walle# hw/lm32_timer.c
334*47f08d7aSLluíslm32_timer_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
335*47f08d7aSLluíslm32_timer_memory_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
336*47f08d7aSLluíslm32_timer_hit(void) "timer hit"
337*47f08d7aSLluíslm32_timer_irq_state(int level) "irq state %d"
338770ae571SMichael Walle
339770ae571SMichael Walle# hw/lm32_uart.c
340*47f08d7aSLluíslm32_uart_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
341*47f08d7aSLluíslm32_uart_memory_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
342*47f08d7aSLluíslm32_uart_irq_state(int level) "irq state %d"
343f19410caSMichael Walle
344f19410caSMichael Walle# hw/lm32_sys.c
345*47f08d7aSLluíslm32_sys_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
34625a8bb96SMichael Walle
34725a8bb96SMichael Walle# hw/milkymist-ac97.c
348*47f08d7aSLluísmilkymist_ac97_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x"
349*47f08d7aSLluísmilkymist_ac97_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x"
350*47f08d7aSLluísmilkymist_ac97_pulse_irq_crrequest(void) "Pulse IRQ CR request"
351*47f08d7aSLluísmilkymist_ac97_pulse_irq_crreply(void) "Pulse IRQ CR reply"
352*47f08d7aSLluísmilkymist_ac97_pulse_irq_dmaw(void) "Pulse IRQ DMA write"
353*47f08d7aSLluísmilkymist_ac97_pulse_irq_dmar(void) "Pulse IRQ DMA read"
354*47f08d7aSLluísmilkymist_ac97_in_cb(int avail, uint32_t remaining) "avail %d remaining %u"
355*47f08d7aSLluísmilkymist_ac97_in_cb_transferred(int transferred) "transferred %d"
356*47f08d7aSLluísmilkymist_ac97_out_cb(int free, uint32_t remaining) "free %d remaining %u"
357*47f08d7aSLluísmilkymist_ac97_out_cb_transferred(int transferred) "transferred %d"
358e4dc6d2cSMichael Walle
359e4dc6d2cSMichael Walle# hw/milkymist-hpdmc.c
360*47f08d7aSLluísmilkymist_hpdmc_memory_read(uint32_t addr, uint32_t value) "addr=%08x value=%08x"
361*47f08d7aSLluísmilkymist_hpdmc_memory_write(uint32_t addr, uint32_t value) "addr=%08x value=%08x"
362b4e37d98SMichael Walle
363b4e37d98SMichael Walle# hw/milkymist-memcard.c
364*47f08d7aSLluísmilkymist_memcard_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x"
365*47f08d7aSLluísmilkymist_memcard_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x"
36607424544SMichael Walle
36757aa265dSMichael Walle# hw/milkymist-minimac2.c
368*47f08d7aSLluísmilkymist_minimac2_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x"
369*47f08d7aSLluísmilkymist_minimac2_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x"
370*47f08d7aSLluísmilkymist_minimac2_mdio_write(uint8_t phy_addr, uint8_t addr, uint16_t value) "phy_addr %02x addr %02x value %04x"
371*47f08d7aSLluísmilkymist_minimac2_mdio_read(uint8_t phy_addr, uint8_t addr, uint16_t value) "phy_addr %02x addr %02x value %04x"
372*47f08d7aSLluísmilkymist_minimac2_tx_frame(uint32_t length) "length %u"
373*47f08d7aSLluísmilkymist_minimac2_rx_frame(const void *buf, uint32_t length) "buf %p length %u"
374*47f08d7aSLluísmilkymist_minimac2_drop_rx_frame(const void *buf) "buf %p"
375*47f08d7aSLluísmilkymist_minimac2_rx_transfer(const void *buf, uint32_t length) "buf %p length %d"
376*47f08d7aSLluísmilkymist_minimac2_raise_irq_rx(void) "Raise IRQ RX"
377*47f08d7aSLluísmilkymist_minimac2_lower_irq_rx(void) "Lower IRQ RX"
378*47f08d7aSLluísmilkymist_minimac2_pulse_irq_tx(void) "Pulse IRQ TX"
3795ee18b9cSMichael Walle
3805ee18b9cSMichael Walle# hw/milkymist-pfpu.c
381*47f08d7aSLluísmilkymist_pfpu_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x"
382*47f08d7aSLluísmilkymist_pfpu_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x"
383*47f08d7aSLluísmilkymist_pfpu_vectout(uint32_t a, uint32_t b, uint32_t dma_ptr) "a %08x b %08x dma_ptr %08x"
384*47f08d7aSLluísmilkymist_pfpu_pulse_irq(void) "Pulse IRQ"
38587a381ecSMichael Walle
38687a381ecSMichael Walle# hw/milkymist-softusb.c
387*47f08d7aSLluísmilkymist_softusb_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x"
388*47f08d7aSLluísmilkymist_softusb_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x"
389*47f08d7aSLluísmilkymist_softusb_mevt(uint8_t m) "m %d"
390*47f08d7aSLluísmilkymist_softusb_kevt(uint8_t m) "m %d"
391*47f08d7aSLluísmilkymist_softusb_mouse_event(int dx, int dy, int dz, int bs) "dx %d dy %d dz %d bs %02x"
392*47f08d7aSLluísmilkymist_softusb_pulse_irq(void) "Pulse IRQ"
39396832424SMichael Walle
39496832424SMichael Walle# hw/milkymist-sysctl.c
395*47f08d7aSLluísmilkymist_sysctl_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x"
396*47f08d7aSLluísmilkymist_sysctl_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x"
397*47f08d7aSLluísmilkymist_sysctl_icap_write(uint32_t value) "value %08x"
398*47f08d7aSLluísmilkymist_sysctl_start_timer0(void) "Start timer0"
399*47f08d7aSLluísmilkymist_sysctl_stop_timer0(void) "Stop timer0"
400*47f08d7aSLluísmilkymist_sysctl_start_timer1(void) "Start timer1"
401*47f08d7aSLluísmilkymist_sysctl_stop_timer1(void) "Stop timer1"
402*47f08d7aSLluísmilkymist_sysctl_pulse_irq_timer0(void) "Pulse IRQ Timer0"
403*47f08d7aSLluísmilkymist_sysctl_pulse_irq_timer1(void) "Pulse IRQ Timer1"
4040670daddSMichael Walle
4050670daddSMichael Walle# hw/milkymist-tmu2.c
406*47f08d7aSLluísmilkymist_tmu2_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x"
407*47f08d7aSLluísmilkymist_tmu2_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x"
408*47f08d7aSLluísmilkymist_tmu2_start(void) "Start TMU"
409*47f08d7aSLluísmilkymist_tmu2_pulse_irq(void) "Pulse IRQ"
410883de16bSMichael Walle
411883de16bSMichael Walle# hw/milkymist-uart.c
412*47f08d7aSLluísmilkymist_uart_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x"
413*47f08d7aSLluísmilkymist_uart_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x"
414*47f08d7aSLluísmilkymist_uart_pulse_irq_rx(void) "Pulse IRQ RX"
415*47f08d7aSLluísmilkymist_uart_pulse_irq_tx(void) "Pulse IRQ TX"
416d23948b1SMichael Walle
417d23948b1SMichael Walle# hw/milkymist-vgafb.c
418*47f08d7aSLluísmilkymist_vgafb_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x"
419*47f08d7aSLluísmilkymist_vgafb_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x"
420432d268cSJun Nakajima
421432d268cSJun Nakajima# xen-all.c
422*47f08d7aSLluísxen_ram_alloc(unsigned long ram_addr, unsigned long size) "requested: %#lx, size %#lx"
423*47f08d7aSLluísxen_client_set_memory(uint64_t start_addr, unsigned long size, unsigned long phys_offset, bool log_dirty) "%#"PRIx64" size %#lx, offset %#lx, log_dirty %i"
424432d268cSJun Nakajima
425432d268cSJun Nakajima# xen-mapcache.c
426*47f08d7aSLluísxen_map_cache(uint64_t phys_addr) "want %#"PRIx64""
427*47f08d7aSLluísxen_remap_bucket(uint64_t index) "index %#"PRIx64""
428*47f08d7aSLluísxen_map_cache_return(void* ptr) "%p"
429*47f08d7aSLluísxen_map_block(uint64_t phys_addr, uint64_t size) "%#"PRIx64", size %#"PRIx64""
430*47f08d7aSLluísxen_unmap_block(void* addr, unsigned long size) "%p, size %#lx"
431050a0ddfSAnthony PERARD
432050a0ddfSAnthony PERARD# exec.c
433*47f08d7aSLluísqemu_put_ram_ptr(void* addr) "%p"
43401195b73SSteven Smith
43501195b73SSteven Smith# hw/xen_platform.c
436*47f08d7aSLluísxen_platform_log(char *s) "xen platform: %s"
43700dccaf1SKevin Wolf
43800dccaf1SKevin Wolf# qemu-coroutine.c
439*47f08d7aSLluísqemu_coroutine_enter(void *from, void *to, void *opaque) "from %p to %p opaque %p"
440*47f08d7aSLluísqemu_coroutine_yield(void *from, void *to) "from %p to %p"
441*47f08d7aSLluísqemu_coroutine_terminate(void *co) "self %p"
442b96e9247SKevin Wolf
443b96e9247SKevin Wolf# qemu-coroutine-lock.c
444*47f08d7aSLluísqemu_co_queue_next_bh(void) ""
445*47f08d7aSLluísqemu_co_queue_next(void *next) "next %p"
446*47f08d7aSLluísqemu_co_mutex_lock_entry(void *mutex, void *self) "mutex %p self %p"
447*47f08d7aSLluísqemu_co_mutex_lock_return(void *mutex, void *self) "mutex %p self %p"
448*47f08d7aSLluísqemu_co_mutex_unlock_entry(void *mutex, void *self) "mutex %p self %p"
449*47f08d7aSLluísqemu_co_mutex_unlock_return(void *mutex, void *self) "mutex %p self %p"
45030c2f238SBlue Swirl
45130c2f238SBlue Swirl# hw/escc.c
452*47f08d7aSLluísescc_put_queue(char channel, int b) "channel %c put: 0x%02x"
453*47f08d7aSLluísescc_get_queue(char channel, int val) "channel %c get 0x%02x"
454*47f08d7aSLluísescc_update_irq(int irq) "IRQ = %d"
455*47f08d7aSLluísescc_update_parameters(char channel, int speed, int parity, int data_bits, int stop_bits) "channel %c: speed=%d parity=%c data=%d stop=%d"
456*47f08d7aSLluísescc_mem_writeb_ctrl(char channel, uint32_t reg, uint32_t val) "Write channel %c, reg[%d] = %2.2x"
457*47f08d7aSLluísescc_mem_writeb_data(char channel, uint32_t val) "Write channel %c, ch %d"
458*47f08d7aSLluísescc_mem_readb_ctrl(char channel, uint32_t reg, uint8_t val) "Read channel %c, reg[%d] = %2.2x"
459*47f08d7aSLluísescc_mem_readb_data(char channel, uint32_t ret) "Read channel %c, ch %d"
460*47f08d7aSLluísescc_serial_receive_byte(char channel, int ch) "channel %c put ch %d"
461*47f08d7aSLluísescc_sunkbd_event_in(int ch) "Untranslated keycode %2.2x"
462*47f08d7aSLluísescc_sunkbd_event_out(int ch) "Translated keycode %2.2x"
463*47f08d7aSLluísescc_kbd_command(int val) "Command %d"
464*47f08d7aSLluísescc_sunmouse_event(int dx, int dy, int buttons_state) "dx=%d dy=%d buttons=%01x"
465