xref: /qemu/trace-events (revision 439a97ccab2dba51e4dad94ba2d347143a0709cc)
194a420b1SStefan Hajnoczi# Trace events for debugging and performance instrumentation
294a420b1SStefan Hajnoczi#
394a420b1SStefan Hajnoczi# This file is processed by the tracetool script during the build.
494a420b1SStefan Hajnoczi#
594a420b1SStefan Hajnoczi# To add a new trace event:
694a420b1SStefan Hajnoczi#
794a420b1SStefan Hajnoczi# 1. Choose a name for the trace event.  Declare its arguments and format
894a420b1SStefan Hajnoczi#    string.
994a420b1SStefan Hajnoczi#
1094a420b1SStefan Hajnoczi# 2. Call the trace event from code using trace_##name, e.g. multiwrite_cb() ->
1194a420b1SStefan Hajnoczi#    trace_multiwrite_cb().  The source file must #include "trace.h".
1294a420b1SStefan Hajnoczi#
1394a420b1SStefan Hajnoczi# Format of a trace event:
1494a420b1SStefan Hajnoczi#
151e2cf2bcSStefan Hajnoczi# [disable] <name>(<type1> <arg1>[, <type2> <arg2>] ...) "<format-string>"
1694a420b1SStefan Hajnoczi#
1794a420b1SStefan Hajnoczi# Example: qemu_malloc(size_t size) "size %zu"
1894a420b1SStefan Hajnoczi#
191e2cf2bcSStefan Hajnoczi# The "disable" keyword will build without the trace event.
201e2cf2bcSStefan Hajnoczi# In case of 'simple' trace backend, it will allow the trace event to be
211e2cf2bcSStefan Hajnoczi# compiled, but this would be turned off by default. It can be toggled on via
221e2cf2bcSStefan Hajnoczi# the monitor.
231e2cf2bcSStefan Hajnoczi#
2494a420b1SStefan Hajnoczi# The <name> must be a valid as a C function name.
2594a420b1SStefan Hajnoczi#
2694a420b1SStefan Hajnoczi# Types should be standard C types.  Use void * for pointers because the trace
2794a420b1SStefan Hajnoczi# system may not have the necessary headers included.
2894a420b1SStefan Hajnoczi#
2994a420b1SStefan Hajnoczi# The <format-string> should be a sprintf()-compatible format string.
30cd245a19SStefan Hajnoczi
31cd245a19SStefan Hajnoczi# qemu-malloc.c
32cd245a19SStefan Hajnoczidisable qemu_malloc(size_t size, void *ptr) "size %zu ptr %p"
33cd245a19SStefan Hajnoczidisable qemu_realloc(void *ptr, size_t size, void *newptr) "ptr %p size %zu newptr %p"
34cd245a19SStefan Hajnoczidisable qemu_free(void *ptr) "ptr %p"
35cd245a19SStefan Hajnoczi
36cd245a19SStefan Hajnoczi# osdep.c
37cd245a19SStefan Hajnoczidisable qemu_memalign(size_t alignment, size_t size, void *ptr) "alignment %zu size %zu ptr %p"
38dda85211SBlue Swirldisable qemu_vmalloc(size_t size, void *ptr) "size %zu ptr %p"
39cd245a19SStefan Hajnoczidisable qemu_vfree(void *ptr) "ptr %p"
406d519a5fSStefan Hajnoczi
4164979a4dSStefan Hajnoczi# hw/virtio.c
4264979a4dSStefan Hajnoczidisable virtqueue_fill(void *vq, const void *elem, unsigned int len, unsigned int idx) "vq %p elem %p len %u idx %u"
4364979a4dSStefan Hajnoczidisable virtqueue_flush(void *vq, unsigned int count) "vq %p count %u"
4464979a4dSStefan Hajnoczidisable virtqueue_pop(void *vq, void *elem, unsigned int in_num, unsigned int out_num) "vq %p elem %p in_num %u out_num %u"
4564979a4dSStefan Hajnoczidisable virtio_queue_notify(void *vdev, int n, void *vq) "vdev %p n %d vq %p"
4664979a4dSStefan Hajnoczidisable virtio_irq(void *vq) "vq %p"
4764979a4dSStefan Hajnoczidisable virtio_notify(void *vdev, void *vq) "vdev %p vq %p"
4864979a4dSStefan Hajnoczi
496d519a5fSStefan Hajnoczi# block.c
506d519a5fSStefan Hajnoczidisable multiwrite_cb(void *mcb, int ret) "mcb %p ret %d"
516d519a5fSStefan Hajnoczidisable bdrv_aio_multiwrite(void *mcb, int num_callbacks, int num_reqs) "mcb %p num_callbacks %d num_reqs %d"
526d519a5fSStefan Hajnoczidisable bdrv_aio_multiwrite_earlyfail(void *mcb) "mcb %p"
536d519a5fSStefan Hajnoczidisable bdrv_aio_multiwrite_latefail(void *mcb, int i) "mcb %p i %d"
54a13aac04SStefan Hajnoczidisable bdrv_aio_flush(void *bs, void *opaque) "bs %p opaque %p"
55bbf0a440SStefan Hajnoczidisable bdrv_aio_readv(void *bs, int64_t sector_num, int nb_sectors, void *opaque) "bs %p sector_num %"PRId64" nb_sectors %d opaque %p"
56bbf0a440SStefan Hajnoczidisable bdrv_aio_writev(void *bs, int64_t sector_num, int nb_sectors, void *opaque) "bs %p sector_num %"PRId64" nb_sectors %d opaque %p"
57b8c6d095SStefan Hajnoczidisable bdrv_set_locked(void *bs, int locked) "bs %p locked %d"
586d519a5fSStefan Hajnoczi
596d519a5fSStefan Hajnoczi# hw/virtio-blk.c
606d519a5fSStefan Hajnoczidisable virtio_blk_req_complete(void *req, int status) "req %p status %d"
616d519a5fSStefan Hajnoczidisable virtio_blk_rw_complete(void *req, int ret) "req %p ret %d"
629a85d394SStefan Hajnoczidisable virtio_blk_handle_write(void *req, uint64_t sector, size_t nsectors) "req %p sector %"PRIu64" nsectors %zu"
636d519a5fSStefan Hajnoczi
646d519a5fSStefan Hajnoczi# posix-aio-compat.c
659a85d394SStefan Hajnoczidisable paio_submit(void *acb, void *opaque, int64_t sector_num, int nb_sectors, int type) "acb %p opaque %p sector_num %"PRId64" nb_sectors %d type %d"
66ddca9fb2SStefan Hajnoczidisable paio_complete(void *acb, void *opaque, int ret) "acb %p opaque %p ret %d"
67ddca9fb2SStefan Hajnoczidisable paio_cancel(void *acb, void *opaque) "acb %p opaque %p"
68bd3c9aa5SPrerna Saxena
69bd3c9aa5SPrerna Saxena# ioport.c
70bd3c9aa5SPrerna Saxenadisable cpu_in(unsigned int addr, unsigned int val) "addr %#x value %u"
71bd3c9aa5SPrerna Saxenadisable cpu_out(unsigned int addr, unsigned int val) "addr %#x value %u"
7262dd89deSPrerna Saxena
7362dd89deSPrerna Saxena# balloon.c
7462dd89deSPrerna Saxena# Since requests are raised via monitor, not many tracepoints are needed.
7562dd89deSPrerna Saxenadisable balloon_event(void *opaque, unsigned long addr) "opaque %p addr %lu"
76d8023f31SBlue Swirl
77d8023f31SBlue Swirl# hw/apic.c
78d8023f31SBlue Swirldisable apic_local_deliver(int vector, uint32_t lvt) "vector %d delivery mode %d"
79d8023f31SBlue Swirldisable apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode, uint8_t vector_num, uint8_t polarity, uint8_t trigger_mode) "dest %d dest_mode %d delivery_mode %d vector %d polarity %d trigger_mode %d"
80d8023f31SBlue Swirldisable cpu_set_apic_base(uint64_t val) "%016"PRIx64""
81d8023f31SBlue Swirldisable cpu_get_apic_base(uint64_t val) "%016"PRIx64""
82d8023f31SBlue Swirldisable apic_mem_readl(uint64_t addr, uint32_t val)  "%"PRIx64" = %08x"
83d8023f31SBlue Swirldisable apic_mem_writel(uint64_t addr, uint32_t val) "%"PRIx64" = %08x"
84d8023f31SBlue Swirl# coalescing
85d8023f31SBlue Swirldisable apic_reset_irq_delivered(int apic_irq_delivered) "old coalescing %d"
86d8023f31SBlue Swirldisable apic_get_irq_delivered(int apic_irq_delivered) "returning coalescing %d"
87d8023f31SBlue Swirldisable apic_set_irq(int apic_irq_delivered) "coalescing %d"
8897bf4851SBlue Swirl
8997bf4851SBlue Swirl# hw/cs4231.c
9097bf4851SBlue Swirldisable cs4231_mem_readl_dreg(uint32_t reg, uint32_t ret) "read dreg %d: 0x%02x"
9197bf4851SBlue Swirldisable cs4231_mem_readl_reg(uint32_t reg, uint32_t ret) "read reg %d: 0x%08x"
9297bf4851SBlue Swirldisable cs4231_mem_writel_reg(uint32_t reg, uint32_t old, uint32_t val) "write reg %d: 0x%08x -> 0x%08x"
9397bf4851SBlue Swirldisable cs4231_mem_writel_dreg(uint32_t reg, uint32_t old, uint32_t val) "write dreg %d: 0x%02x -> 0x%02x"
9497bf4851SBlue Swirl
9597bf4851SBlue Swirl# hw/eccmemctl.c
9697bf4851SBlue Swirldisable ecc_mem_writel_mer(uint32_t val) "Write memory enable %08x"
9797bf4851SBlue Swirldisable ecc_mem_writel_mdr(uint32_t val) "Write memory delay %08x"
9897bf4851SBlue Swirldisable ecc_mem_writel_mfsr(uint32_t val) "Write memory fault status %08x"
9997bf4851SBlue Swirldisable ecc_mem_writel_vcr(uint32_t val) "Write slot configuration %08x"
10097bf4851SBlue Swirldisable ecc_mem_writel_dr(uint32_t val) "Write diagnostic %08x"
10197bf4851SBlue Swirldisable ecc_mem_writel_ecr0(uint32_t val) "Write event count 1 %08x"
10297bf4851SBlue Swirldisable ecc_mem_writel_ecr1(uint32_t val) "Write event count 2 %08x"
10397bf4851SBlue Swirldisable ecc_mem_readl_mer(uint32_t ret) "Read memory enable %08x"
10497bf4851SBlue Swirldisable ecc_mem_readl_mdr(uint32_t ret) "Read memory delay %08x"
10597bf4851SBlue Swirldisable ecc_mem_readl_mfsr(uint32_t ret) "Read memory fault status %08x"
10697bf4851SBlue Swirldisable ecc_mem_readl_vcr(uint32_t ret) "Read slot configuration %08x"
10797bf4851SBlue Swirldisable ecc_mem_readl_mfar0(uint32_t ret) "Read memory fault address 0 %08x"
10897bf4851SBlue Swirldisable ecc_mem_readl_mfar1(uint32_t ret) "Read memory fault address 1 %08x"
10997bf4851SBlue Swirldisable ecc_mem_readl_dr(uint32_t ret) "Read diagnostic %08x"
11097bf4851SBlue Swirldisable ecc_mem_readl_ecr0(uint32_t ret) "Read event count 1 %08x"
11197bf4851SBlue Swirldisable ecc_mem_readl_ecr1(uint32_t ret) "Read event count 2 %08x"
11297bf4851SBlue Swirldisable ecc_diag_mem_writeb(uint64_t addr, uint32_t val) "Write diagnostic %"PRId64" = %02x"
11397bf4851SBlue Swirldisable ecc_diag_mem_readb(uint64_t addr, uint32_t ret) "Read diagnostic %"PRId64"= %02x"
11497bf4851SBlue Swirl
11597bf4851SBlue Swirl# hw/lance.c
11697bf4851SBlue Swirldisable lance_mem_readw(uint64_t addr, uint32_t ret) "addr=%"PRIx64"val=0x%04x"
11797bf4851SBlue Swirldisable lance_mem_writew(uint64_t addr, uint32_t val) "addr=%"PRIx64"val=0x%04x"
11897bf4851SBlue Swirl
11997bf4851SBlue Swirl# hw/slavio_intctl.c
12097bf4851SBlue Swirldisable slavio_intctl_mem_readl(uint32_t cpu, uint64_t addr, uint32_t ret) "read cpu %d reg 0x%"PRIx64" = %x"
12197bf4851SBlue Swirldisable slavio_intctl_mem_writel(uint32_t cpu, uint64_t addr, uint32_t val) "write cpu %d reg 0x%"PRIx64" = %x"
12297bf4851SBlue Swirldisable slavio_intctl_mem_writel_clear(uint32_t cpu, uint32_t val, uint32_t intreg_pending) "Cleared cpu %d irq mask %x, curmask %x"
12397bf4851SBlue Swirldisable slavio_intctl_mem_writel_set(uint32_t cpu, uint32_t val, uint32_t intreg_pending) "Set cpu %d irq mask %x, curmask %x"
12497bf4851SBlue Swirldisable slavio_intctlm_mem_readl(uint64_t addr, uint32_t ret) "read system reg 0x%"PRIx64" = %x"
12597bf4851SBlue Swirldisable slavio_intctlm_mem_writel(uint64_t addr, uint32_t val) "write system reg 0x%"PRIx64" = %x"
12697bf4851SBlue Swirldisable slavio_intctlm_mem_writel_enable(uint32_t val, uint32_t intregm_disabled) "Enabled master irq mask %x, curmask %x"
12797bf4851SBlue Swirldisable slavio_intctlm_mem_writel_disable(uint32_t val, uint32_t intregm_disabled) "Disabled master irq mask %x, curmask %x"
12897bf4851SBlue Swirldisable slavio_intctlm_mem_writel_target(uint32_t cpu) "Set master irq cpu %d"
12997bf4851SBlue Swirldisable slavio_check_interrupts(uint32_t pending, uint32_t intregm_disabled) "pending %x disabled %x"
13097bf4851SBlue Swirldisable slavio_set_irq(uint32_t target_cpu, int irq, uint32_t pil, int level) "Set cpu %d irq %d -> pil %d level %d"
13197bf4851SBlue Swirldisable slavio_set_timer_irq_cpu(int cpu, int level) "Set cpu %d local timer level %d"
13297bf4851SBlue Swirl
13397bf4851SBlue Swirl# hw/slavio_misc.c
13497bf4851SBlue Swirldisable slavio_misc_update_irq_raise(void) "Raise IRQ"
13597bf4851SBlue Swirldisable slavio_misc_update_irq_lower(void) "Lower IRQ"
13697bf4851SBlue Swirldisable slavio_set_power_fail(int power_failing, uint8_t config) "Power fail: %d, config: %d"
13797bf4851SBlue Swirldisable slavio_cfg_mem_writeb(uint32_t val) "Write config %02x"
13897bf4851SBlue Swirldisable slavio_cfg_mem_readb(uint32_t ret) "Read config %02x"
13997bf4851SBlue Swirldisable slavio_diag_mem_writeb(uint32_t val) "Write diag %02x"
14097bf4851SBlue Swirldisable slavio_diag_mem_readb(uint32_t ret) "Read diag %02x"
14197bf4851SBlue Swirldisable slavio_mdm_mem_writeb(uint32_t val) "Write modem control %02x"
14297bf4851SBlue Swirldisable slavio_mdm_mem_readb(uint32_t ret) "Read modem control %02x"
14397bf4851SBlue Swirldisable slavio_aux1_mem_writeb(uint32_t val) "Write aux1 %02x"
14497bf4851SBlue Swirldisable slavio_aux1_mem_readb(uint32_t ret) "Read aux1 %02x"
14597bf4851SBlue Swirldisable slavio_aux2_mem_writeb(uint32_t val) "Write aux2 %02x"
14697bf4851SBlue Swirldisable slavio_aux2_mem_readb(uint32_t ret) "Read aux2 %02x"
14797bf4851SBlue Swirldisable apc_mem_writeb(uint32_t val) "Write power management %02x"
14897bf4851SBlue Swirldisable apc_mem_readb(uint32_t ret) "Read power management %02x"
14997bf4851SBlue Swirldisable slavio_sysctrl_mem_writel(uint32_t val) "Write system control %08x"
15097bf4851SBlue Swirldisable slavio_sysctrl_mem_readl(uint32_t ret) "Read system control %08x"
15197bf4851SBlue Swirldisable slavio_led_mem_writew(uint32_t val) "Write diagnostic LED %04x"
15297bf4851SBlue Swirldisable slavio_led_mem_readw(uint32_t ret) "Read diagnostic LED %04x"
15397bf4851SBlue Swirl
15497bf4851SBlue Swirl# hw/slavio_timer.c
15597bf4851SBlue Swirldisable slavio_timer_get_out(uint64_t limit, uint32_t counthigh, uint32_t count) "limit %"PRIx64" count %x%08x"
15697bf4851SBlue Swirldisable slavio_timer_irq(uint32_t counthigh, uint32_t count) "callback: count %x%08x"
15797bf4851SBlue Swirldisable slavio_timer_mem_readl_invalid(uint64_t addr) "invalid read address %"PRIx64""
15897bf4851SBlue Swirldisable slavio_timer_mem_readl(uint64_t addr, uint32_t ret) "read %"PRIx64" = %08x"
15997bf4851SBlue Swirldisable slavio_timer_mem_writel(uint64_t addr, uint32_t val) "write %"PRIx64" = %08x"
16097bf4851SBlue Swirldisable slavio_timer_mem_writel_limit(unsigned int timer_index, uint64_t count) "processor %d user timer set to %016"PRIx64""
16197bf4851SBlue Swirldisable slavio_timer_mem_writel_counter_invalid(void) "not user timer"
16297bf4851SBlue Swirldisable slavio_timer_mem_writel_status_start(unsigned int timer_index) "processor %d user timer started"
16397bf4851SBlue Swirldisable slavio_timer_mem_writel_status_stop(unsigned int timer_index) "processor %d user timer stopped"
16497bf4851SBlue Swirldisable slavio_timer_mem_writel_mode_user(unsigned int timer_index) "processor %d changed from counter to user timer"
16597bf4851SBlue Swirldisable slavio_timer_mem_writel_mode_counter(unsigned int timer_index) "processor %d changed from user timer to counter"
16697bf4851SBlue Swirldisable slavio_timer_mem_writel_mode_invalid(void) "not system timer"
16797bf4851SBlue Swirldisable slavio_timer_mem_writel_invalid(uint64_t addr) "invalid write address %"PRIx64""
16897bf4851SBlue Swirl
16997bf4851SBlue Swirl# hw/sparc32_dma.c
17097bf4851SBlue Swirldisable ledma_memory_read(uint64_t addr) "DMA read addr 0x%"PRIx64""
17197bf4851SBlue Swirldisable ledma_memory_write(uint64_t addr) "DMA write addr 0x%"PRIx64""
17297bf4851SBlue Swirldisable sparc32_dma_set_irq_raise(void) "Raise IRQ"
17397bf4851SBlue Swirldisable sparc32_dma_set_irq_lower(void) "Lower IRQ"
17497bf4851SBlue Swirldisable espdma_memory_read(uint32_t addr) "DMA read addr 0x%08x"
17597bf4851SBlue Swirldisable espdma_memory_write(uint32_t addr) "DMA write addr 0x%08x"
17697bf4851SBlue Swirldisable sparc32_dma_mem_readl(uint64_t addr, uint32_t ret) "read dmareg %"PRIx64": 0x%08x"
17797bf4851SBlue Swirldisable sparc32_dma_mem_writel(uint64_t addr, uint32_t old, uint32_t val) "write dmareg %"PRIx64": 0x%08x -> 0x%08x"
17897bf4851SBlue Swirldisable sparc32_dma_enable_raise(void) "Raise DMA enable"
17997bf4851SBlue Swirldisable sparc32_dma_enable_lower(void) "Lower DMA enable"
18097bf4851SBlue Swirl
18197bf4851SBlue Swirl# hw/sun4m.c
18297bf4851SBlue Swirldisable sun4m_cpu_interrupt(unsigned int level) "Set CPU IRQ %d"
18397bf4851SBlue Swirldisable sun4m_cpu_reset_interrupt(unsigned int level) "Reset CPU IRQ %d"
18497bf4851SBlue Swirldisable sun4m_cpu_set_irq_raise(int level) "Raise CPU IRQ %d"
18597bf4851SBlue Swirldisable sun4m_cpu_set_irq_lower(int level) "Lower CPU IRQ %d"
18697bf4851SBlue Swirl
18797bf4851SBlue Swirl# hw/sun4m_iommu.c
18897bf4851SBlue Swirldisable sun4m_iommu_mem_readl(uint64_t addr, uint32_t ret) "read reg[%"PRIx64"] = %x"
18997bf4851SBlue Swirldisable sun4m_iommu_mem_writel(uint64_t addr, uint32_t val) "write reg[%"PRIx64"] = %x"
19097bf4851SBlue Swirldisable sun4m_iommu_mem_writel_ctrl(uint64_t iostart) "iostart = %"PRIx64""
19197bf4851SBlue Swirldisable sun4m_iommu_mem_writel_tlbflush(uint32_t val) "tlb flush %x"
19297bf4851SBlue Swirldisable sun4m_iommu_mem_writel_pgflush(uint32_t val) "page flush %x"
19397bf4851SBlue Swirldisable sun4m_iommu_page_get_flags(uint64_t pa, uint64_t iopte, uint32_t ret) "get flags addr %"PRIx64" => pte %"PRIx64", *pte = %x"
19497bf4851SBlue Swirldisable sun4m_iommu_translate_pa(uint64_t addr, uint64_t pa, uint32_t iopte) "xlate dva %"PRIx64" => pa %"PRIx64" iopte = %x"
19597bf4851SBlue Swirldisable sun4m_iommu_bad_addr(uint64_t addr) "bad addr %"PRIx64""
19694b0b5ffSStefan Hajnoczi
197*439a97ccSGerd Hoffmann# hw/usb-ehci.c
198*439a97ccSGerd Hoffmanndisable usb_ehci_reset(void) "=== RESET ==="
199*439a97ccSGerd Hoffmanndisable usb_ehci_mmio_readl(uint32_t addr, const char *str, uint32_t val) "rd mmio %04x [%s] = %x"
200*439a97ccSGerd Hoffmanndisable usb_ehci_mmio_writel(uint32_t addr, const char *str, uint32_t val, uint32_t oldval) "wr mmio %04x [%s] = %x (old: %x)"
201*439a97ccSGerd Hoffmanndisable usb_ehci_usbsts(const char *sts, int state) "usbsts %s %d"
202*439a97ccSGerd Hoffmann
20337fb59d3SGerd Hoffmann# hw/usb-desc.c
20437fb59d3SGerd Hoffmanndisable usb_desc_device(int addr, int len, int ret) "dev %d query device, len %d, ret %d"
20525620cbaSGerd Hoffmanndisable usb_desc_device_qualifier(int addr, int len, int ret) "dev %d query device qualifier, len %d, ret %d"
20637fb59d3SGerd Hoffmanndisable usb_desc_config(int addr, int index, int len, int ret) "dev %d query config %d, len %d, ret %d"
20725620cbaSGerd Hoffmanndisable usb_desc_other_speed_config(int addr, int index, int len, int ret) "dev %d query config %d, len %d, ret %d"
20837fb59d3SGerd Hoffmanndisable usb_desc_string(int addr, int index, int len, int ret) "dev %d query string %d, len %d, ret %d"
20941c6abbdSGerd Hoffmanndisable usb_set_addr(int addr) "dev %d"
210a980a065SGerd Hoffmanndisable usb_set_config(int addr, int config, int ret) "dev %d, config %d, ret %d"
211ed5a83ddSGerd Hoffmanndisable usb_clear_device_feature(int addr, int feature, int ret) "dev %d, feature %d, ret %d"
212ed5a83ddSGerd Hoffmanndisable usb_set_device_feature(int addr, int feature, int ret) "dev %d, feature %d, ret %d"
21337fb59d3SGerd Hoffmann
2145138efecSPaolo Bonzini# hw/scsi-bus.c
2155138efecSPaolo Bonzinidisable scsi_req_alloc(int target, int lun, int tag) "target %d lun %d tag %d"
216ab9adc88SPaolo Bonzinidisable scsi_req_data(int target, int lun, int tag, int len) "target %d lun %d tag %d len %d"
2175138efecSPaolo Bonzinidisable scsi_req_dequeue(int target, int lun, int tag) "target %d lun %d tag %d"
218ad3376ccSPaolo Bonzinidisable scsi_req_continue(int target, int lun, int tag) "target %d lun %d tag %d"
219d800040fSPaolo Bonzinidisable scsi_req_parsed(int target, int lun, int tag, int cmd, int mode, int xfer) "target %d lun %d tag %d command %d dir %d length %d"
220d800040fSPaolo Bonzinidisable scsi_req_parsed_lba(int target, int lun, int tag, int cmd, uint64_t lba) "target %d lun %d tag %d command %d lba %"PRIu64""
2215138efecSPaolo Bonzinidisable scsi_req_parse_bad(int target, int lun, int tag, int cmd) "target %d lun %d tag %d command %d"
2225138efecSPaolo Bonzini
22394b0b5ffSStefan Hajnoczi# vl.c
22494b0b5ffSStefan Hajnoczidisable vm_state_notify(int running, int reason) "running %d reason %d"
225298800caSStefan Hajnoczi
226298800caSStefan Hajnoczi# block/qed-l2-cache.c
227298800caSStefan Hajnoczidisable qed_alloc_l2_cache_entry(void *l2_cache, void *entry) "l2_cache %p entry %p"
228298800caSStefan Hajnoczidisable qed_unref_l2_cache_entry(void *entry, int ref) "entry %p ref %d"
229298800caSStefan Hajnoczidisable qed_find_l2_cache_entry(void *l2_cache, void *entry, uint64_t offset, int ref) "l2_cache %p entry %p offset %"PRIu64" ref %d"
230298800caSStefan Hajnoczi
231298800caSStefan Hajnoczi# block/qed-table.c
232298800caSStefan Hajnoczidisable qed_read_table(void *s, uint64_t offset, void *table) "s %p offset %"PRIu64" table %p"
233298800caSStefan Hajnoczidisable qed_read_table_cb(void *s, void *table, int ret) "s %p table %p ret %d"
234298800caSStefan Hajnoczidisable qed_write_table(void *s, uint64_t offset, void *table, unsigned int index, unsigned int n) "s %p offset %"PRIu64" table %p index %u n %u"
235298800caSStefan Hajnoczidisable qed_write_table_cb(void *s, void *table, int flush, int ret) "s %p table %p flush %d ret %d"
236eabba580SStefan Hajnoczi
237eabba580SStefan Hajnoczi# block/qed.c
2386f321e93SStefan Hajnoczidisable qed_need_check_timer_cb(void *s) "s %p"
2396f321e93SStefan Hajnoczidisable qed_start_need_check_timer(void *s) "s %p"
2406f321e93SStefan Hajnoczidisable qed_cancel_need_check_timer(void *s) "s %p"
241eabba580SStefan Hajnoczidisable qed_aio_complete(void *s, void *acb, int ret) "s %p acb %p ret %d"
242eabba580SStefan Hajnoczidisable qed_aio_setup(void *s, void *acb, int64_t sector_num, int nb_sectors, void *opaque, int is_write) "s %p acb %p sector_num %"PRId64" nb_sectors %d opaque %p is_write %d"
243eabba580SStefan Hajnoczidisable qed_aio_next_io(void *s, void *acb, int ret, uint64_t cur_pos) "s %p acb %p ret %d cur_pos %"PRIu64""
244eabba580SStefan Hajnoczidisable qed_aio_read_data(void *s, void *acb, int ret, uint64_t offset, size_t len) "s %p acb %p ret %d offset %"PRIu64" len %zu"
245eabba580SStefan Hajnoczidisable qed_aio_write_data(void *s, void *acb, int ret, uint64_t offset, size_t len) "s %p acb %p ret %d offset %"PRIu64" len %zu"
246eabba580SStefan Hajnoczidisable qed_aio_write_prefill(void *s, void *acb, uint64_t start, size_t len, uint64_t offset) "s %p acb %p start %"PRIu64" len %zu offset %"PRIu64""
247eabba580SStefan Hajnoczidisable qed_aio_write_postfill(void *s, void *acb, uint64_t start, size_t len, uint64_t offset) "s %p acb %p start %"PRIu64" len %zu offset %"PRIu64""
248eabba580SStefan Hajnoczidisable qed_aio_write_main(void *s, void *acb, int ret, uint64_t offset, size_t len) "s %p acb %p ret %d offset %"PRIu64" len %zu"
2490f3a4a01SFabien Chouteau
2500f3a4a01SFabien Chouteau# hw/grlib_gptimer.c
2510f3a4a01SFabien Chouteaudisable grlib_gptimer_enable(int id, uint32_t count) "timer:%d set count 0x%x and run"
2520f3a4a01SFabien Chouteaudisable grlib_gptimer_disabled(int id, uint32_t config) "timer:%d Timer disable config 0x%x"
2530f3a4a01SFabien Chouteaudisable grlib_gptimer_restart(int id, uint32_t reload) "timer:%d reload val: 0x%x"
2540f3a4a01SFabien Chouteaudisable grlib_gptimer_set_scaler(uint32_t scaler, uint32_t freq) "scaler:0x%x freq: 0x%x"
2550f3a4a01SFabien Chouteaudisable grlib_gptimer_hit(int id) "timer:%d HIT"
256b4548fccSStefan Hajnoczidisable grlib_gptimer_readl(int id, uint64_t addr, uint32_t val) "timer:%d addr 0x%"PRIx64" 0x%x"
257b4548fccSStefan Hajnoczidisable grlib_gptimer_writel(int id, uint64_t addr, uint32_t val) "timer:%d addr 0x%"PRIx64" 0x%x"
2583f10bcbbSFabien Chouteau
2593f10bcbbSFabien Chouteau# hw/grlib_irqmp.c
2603f10bcbbSFabien Chouteaudisable grlib_irqmp_check_irqs(uint32_t pend, uint32_t force, uint32_t mask, uint32_t lvl1, uint32_t lvl2) "pend:0x%04x force:0x%04x mask:0x%04x lvl1:0x%04x lvl0:0x%04x\n"
2613f10bcbbSFabien Chouteaudisable grlib_irqmp_ack(int intno) "interrupt:%d"
2623f10bcbbSFabien Chouteaudisable grlib_irqmp_set_irq(int irq) "Raise CPU IRQ %d"
263b4548fccSStefan Hajnoczidisable grlib_irqmp_readl_unknown(uint64_t addr) "addr 0x%"PRIx64""
264b4548fccSStefan Hajnoczidisable grlib_irqmp_writel_unknown(uint64_t addr, uint32_t value) "addr 0x%"PRIx64" value 0x%x"
2658b1e1320SFabien Chouteau
2668b1e1320SFabien Chouteau# hw/grlib_apbuart.c
2678b1e1320SFabien Chouteaudisable grlib_apbuart_event(int event) "event:%d"
268b4548fccSStefan Hajnoczidisable grlib_apbuart_writel_unknown(uint64_t addr, uint32_t value) "addr 0x%"PRIx64" value 0x%x"
269b04d9890SFabien Chouteau
270b04d9890SFabien Chouteau# hw/leon3.c
271b04d9890SFabien Chouteaudisable leon3_set_irq(int intno) "Set CPU IRQ %d"
272b04d9890SFabien Chouteaudisable leon3_reset_irq(int intno) "Reset CPU IRQ %d"
2739363ee31SAnthony Liguori
274cbcc6336SAlon Levy# spice-qemu-char.c
2752b287af6SLluísdisable spice_vmc_write(ssize_t out, int len) "spice wrottn %zd of requested %d"
2762b287af6SLluísdisable spice_vmc_read(int bytes, int len) "spice read %d of requested %d"
277cbcc6336SAlon Levydisable spice_vmc_register_interface(void *scd) "spice vmc registered interface %p"
278cbcc6336SAlon Levydisable spice_vmc_unregister_interface(void *scd) "spice vmc unregistered interface %p"
2794ef66fa7SMichael Walle
2804ef66fa7SMichael Walle# hw/lm32_pic.c
2814ef66fa7SMichael Walledisable lm32_pic_raise_irq(void) "Raise CPU interrupt"
2824ef66fa7SMichael Walledisable lm32_pic_lower_irq(void) "Lower CPU interrupt"
2834ef66fa7SMichael Walledisable lm32_pic_interrupt(int irq, int level) "Set IRQ%d %d"
2844ef66fa7SMichael Walledisable lm32_pic_set_im(uint32_t im) "im 0x%08x"
2854ef66fa7SMichael Walledisable lm32_pic_set_ip(uint32_t ip) "ip 0x%08x"
2864ef66fa7SMichael Walledisable lm32_pic_get_im(uint32_t im) "im 0x%08x"
2874ef66fa7SMichael Walledisable lm32_pic_get_ip(uint32_t ip) "ip 0x%08x"
28815d7dc4fSMichael Walle
28915d7dc4fSMichael Walle# hw/lm32_juart.c
29015d7dc4fSMichael Walledisable lm32_juart_get_jtx(uint32_t value) "jtx 0x%08x"
29115d7dc4fSMichael Walledisable lm32_juart_set_jtx(uint32_t value) "jtx 0x%08x"
29215d7dc4fSMichael Walledisable lm32_juart_get_jrx(uint32_t value) "jrx 0x%08x"
29315d7dc4fSMichael Walledisable lm32_juart_set_jrx(uint32_t value) "jrx 0x%08x"
294ea7924dcSMichael Walle
295ea7924dcSMichael Walle# hw/lm32_timer.c
296ea7924dcSMichael Walledisable lm32_timer_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
297ea7924dcSMichael Walledisable lm32_timer_memory_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
298ea7924dcSMichael Walledisable lm32_timer_hit(void) "timer hit"
299ea7924dcSMichael Walledisable lm32_timer_irq_state(int level) "irq state %d"
300770ae571SMichael Walle
301770ae571SMichael Walle# hw/lm32_uart.c
302770ae571SMichael Walledisable lm32_uart_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
303770ae571SMichael Walledisable lm32_uart_memory_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
304770ae571SMichael Walledisable lm32_uart_irq_state(int level) "irq state %d"
305f19410caSMichael Walle
306f19410caSMichael Walle# hw/lm32_sys.c
307f19410caSMichael Walledisable lm32_sys_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
30825a8bb96SMichael Walle
30925a8bb96SMichael Walle# hw/milkymist-ac97.c
31025a8bb96SMichael Walledisable milkymist_ac97_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x"
31125a8bb96SMichael Walledisable milkymist_ac97_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x"
31225a8bb96SMichael Walledisable milkymist_ac97_pulse_irq_crrequest(void) "Pulse IRQ CR request"
31325a8bb96SMichael Walledisable milkymist_ac97_pulse_irq_crreply(void) "Pulse IRQ CR reply"
31425a8bb96SMichael Walledisable milkymist_ac97_pulse_irq_dmaw(void) "Pulse IRQ DMA write"
31525a8bb96SMichael Walledisable milkymist_ac97_pulse_irq_dmar(void) "Pulse IRQ DMA read"
31625a8bb96SMichael Walledisable milkymist_ac97_in_cb(int avail, uint32_t remaining) "avail %d remaining %u"
31725a8bb96SMichael Walledisable milkymist_ac97_in_cb_transferred(int transferred) "transferred %d"
31825a8bb96SMichael Walledisable milkymist_ac97_out_cb(int free, uint32_t remaining) "free %d remaining %u"
31925a8bb96SMichael Walledisable milkymist_ac97_out_cb_transferred(int transferred) "transferred %d"
320e4dc6d2cSMichael Walle
321e4dc6d2cSMichael Walle# hw/milkymist-hpdmc.c
322b4e37d98SMichael Walledisable milkymist_hpdmc_memory_read(uint32_t addr, uint32_t value) "addr=%08x value=%08x"
323b4e37d98SMichael Walledisable milkymist_hpdmc_memory_write(uint32_t addr, uint32_t value) "addr=%08x value=%08x"
324b4e37d98SMichael Walle
325b4e37d98SMichael Walle# hw/milkymist-memcard.c
326b4e37d98SMichael Walledisable milkymist_memcard_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x"
327b4e37d98SMichael Walledisable milkymist_memcard_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x"
32807424544SMichael Walle
32957aa265dSMichael Walle# hw/milkymist-minimac2.c
33057aa265dSMichael Walledisable milkymist_minimac2_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x"
33157aa265dSMichael Walledisable milkymist_minimac2_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x"
33257aa265dSMichael Walledisable milkymist_minimac2_mdio_write(uint8_t phy_addr, uint8_t addr, uint16_t value) "phy_addr %02x addr %02x value %04x"
33357aa265dSMichael Walledisable milkymist_minimac2_mdio_read(uint8_t phy_addr, uint8_t addr, uint16_t value) "phy_addr %02x addr %02x value %04x"
33457aa265dSMichael Walledisable milkymist_minimac2_tx_frame(uint32_t length) "length %u"
33557aa265dSMichael Walledisable milkymist_minimac2_rx_frame(const void *buf, uint32_t length) "buf %p length %u"
33657aa265dSMichael Walledisable milkymist_minimac2_drop_rx_frame(const void *buf) "buf %p"
33757aa265dSMichael Walledisable milkymist_minimac2_rx_transfer(const void *buf, uint32_t length) "buf %p length %d"
33857aa265dSMichael Walledisable milkymist_minimac2_raise_irq_rx(void) "Raise IRQ RX"
33957aa265dSMichael Walledisable milkymist_minimac2_lower_irq_rx(void) "Lower IRQ RX"
34057aa265dSMichael Walledisable milkymist_minimac2_pulse_irq_tx(void) "Pulse IRQ TX"
3415ee18b9cSMichael Walle
3425ee18b9cSMichael Walle# hw/milkymist-pfpu.c
3435ee18b9cSMichael Walledisable milkymist_pfpu_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x"
3445ee18b9cSMichael Walledisable milkymist_pfpu_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x"
3455ee18b9cSMichael Walledisable milkymist_pfpu_vectout(uint32_t a, uint32_t b, uint32_t dma_ptr) "a %08x b %08x dma_ptr %08x"
3465ee18b9cSMichael Walledisable milkymist_pfpu_pulse_irq(void) "Pulse IRQ"
34787a381ecSMichael Walle
34887a381ecSMichael Walle# hw/milkymist-softusb.c
34987a381ecSMichael Walledisable milkymist_softusb_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x"
35087a381ecSMichael Walledisable milkymist_softusb_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x"
35187a381ecSMichael Walledisable milkymist_softusb_mevt(uint8_t m) "m %d"
35287a381ecSMichael Walledisable milkymist_softusb_kevt(uint8_t m) "m %d"
35387a381ecSMichael Walledisable milkymist_softusb_mouse_event(int dx, int dy, int dz, int bs) "dx %d dy %d dz %d bs %02x"
35487a381ecSMichael Walledisable milkymist_softusb_pulse_irq(void) "Pulse IRQ"
35596832424SMichael Walle
35696832424SMichael Walle# hw/milkymist-sysctl.c
35796832424SMichael Walledisable milkymist_sysctl_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x"
35896832424SMichael Walledisable milkymist_sysctl_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x"
35996832424SMichael Walledisable milkymist_sysctl_icap_write(uint32_t value) "value %08x"
36096832424SMichael Walledisable milkymist_sysctl_start_timer0(void) "Start timer0"
36196832424SMichael Walledisable milkymist_sysctl_stop_timer0(void) "Stop timer0"
36296832424SMichael Walledisable milkymist_sysctl_start_timer1(void) "Start timer1"
36396832424SMichael Walledisable milkymist_sysctl_stop_timer1(void) "Stop timer1"
36496832424SMichael Walledisable milkymist_sysctl_pulse_irq_timer0(void) "Pulse IRQ Timer0"
36596832424SMichael Walledisable milkymist_sysctl_pulse_irq_timer1(void) "Pulse IRQ Timer1"
3660670daddSMichael Walle
3670670daddSMichael Walle# hw/milkymist-tmu2.c
3680670daddSMichael Walledisable milkymist_tmu2_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x"
3690670daddSMichael Walledisable milkymist_tmu2_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x"
3700670daddSMichael Walledisable milkymist_tmu2_start(void) "Start TMU"
3710670daddSMichael Walledisable milkymist_tmu2_pulse_irq(void) "Pulse IRQ"
372883de16bSMichael Walle
373883de16bSMichael Walle# hw/milkymist-uart.c
374883de16bSMichael Walledisable milkymist_uart_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x"
375883de16bSMichael Walledisable milkymist_uart_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x"
376883de16bSMichael Walledisable milkymist_uart_pulse_irq_rx(void) "Pulse IRQ RX"
377883de16bSMichael Walledisable milkymist_uart_pulse_irq_tx(void) "Pulse IRQ TX"
378d23948b1SMichael Walle
379d23948b1SMichael Walle# hw/milkymist-vgafb.c
380d23948b1SMichael Walledisable milkymist_vgafb_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x"
381d23948b1SMichael Walledisable milkymist_vgafb_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x"
382432d268cSJun Nakajima
383432d268cSJun Nakajima# xen-all.c
384432d268cSJun Nakajimadisable xen_ram_alloc(unsigned long ram_addr, unsigned long size) "requested: %#lx, size %#lx"
385432d268cSJun Nakajima
386432d268cSJun Nakajima# xen-mapcache.c
387432d268cSJun Nakajimadisable qemu_map_cache(uint64_t phys_addr) "want %#"PRIx64""
388432d268cSJun Nakajimadisable qemu_remap_bucket(uint64_t index) "index %#"PRIx64""
389432d268cSJun Nakajimadisable qemu_map_cache_return(void* ptr) "%p"
390432d268cSJun Nakajimadisable xen_map_block(uint64_t phys_addr, uint64_t size) "%#"PRIx64", size %#"PRIx64""
391432d268cSJun Nakajimadisable xen_unmap_block(void* addr, unsigned long size) "%p, size %#lx"
392050a0ddfSAnthony PERARD
393050a0ddfSAnthony PERARD# exec.c
394050a0ddfSAnthony PERARDdisable qemu_put_ram_ptr(void* addr) "%p"
395