1a2e67072SMax Filippov#include "macros.inc" 27d890b40SMax Filippov 372b3b8f2SMax Filippov#define CCOUNT_SHIFT 4 472b3b8f2SMax Filippov#define WAIT_LOOPS 20 572b3b8f2SMax Filippov 672b3b8f2SMax Filippov.macro make_ccount_delta target, delta 772b3b8f2SMax Filippov rsr \delta, ccount 872b3b8f2SMax Filippov rsr \target, ccount 972b3b8f2SMax Filippov sub \delta, \target, \delta 1072b3b8f2SMax Filippov slli \delta, \delta, CCOUNT_SHIFT 1172b3b8f2SMax Filippov add \target, \target, \delta 1272b3b8f2SMax Filippov.endm 1372b3b8f2SMax Filippov 147d890b40SMax Filippovtest_suite timer 157d890b40SMax Filippov 167d890b40SMax Filippovtest ccount 177d890b40SMax Filippov rsr a3, ccount 187d890b40SMax Filippov rsr a4, ccount 1972b3b8f2SMax Filippov assert ne, a3, a4 207d890b40SMax Filippovtest_end 217d890b40SMax Filippov 22*0a362d07SMax Filippovtest ccount_write 23*0a362d07SMax Filippov rsr a3, ccount 24*0a362d07SMax Filippov rsr a4, ccount 25*0a362d07SMax Filippov sub a4, a4, a3 26*0a362d07SMax Filippov movi a2, 0x12345678 27*0a362d07SMax Filippov wsr a2, ccount 28*0a362d07SMax Filippov esync 29*0a362d07SMax Filippov rsr a3, ccount 30*0a362d07SMax Filippov sub a3, a3, a2 31*0a362d07SMax Filippov slli a4, a4, 2 32*0a362d07SMax Filippov assert ltu, a3, a4 33*0a362d07SMax Filippovtest_end 34*0a362d07SMax Filippov 35*0a362d07SMax Filippovtest ccount_update_deadline 36*0a362d07SMax Filippov movi a2, 0 37*0a362d07SMax Filippov wsr a2, intenable 38*0a362d07SMax Filippov rsr a2, interrupt 39*0a362d07SMax Filippov wsr a2, intclear 40*0a362d07SMax Filippov movi a2, 0 41*0a362d07SMax Filippov wsr a2, ccompare1 42*0a362d07SMax Filippov wsr a2, ccompare2 43*0a362d07SMax Filippov movi a2, 0x12345678 44*0a362d07SMax Filippov wsr a2, ccompare0 45*0a362d07SMax Filippov rsr a3, interrupt 46*0a362d07SMax Filippov assert eqi, a3, 0 47*0a362d07SMax Filippov movi a2, 0x12345677 48*0a362d07SMax Filippov wsr a2, ccount 49*0a362d07SMax Filippov esync 50*0a362d07SMax Filippov nop 51*0a362d07SMax Filippov rsr a2, interrupt 52*0a362d07SMax Filippov movi a3, 1 << XCHAL_TIMER0_INTERRUPT 53*0a362d07SMax Filippov assert eq, a2, a3 54*0a362d07SMax Filippovtest_end 55*0a362d07SMax Filippov 567d890b40SMax Filippovtest ccompare 577d890b40SMax Filippov movi a2, 0 587d890b40SMax Filippov wsr a2, intenable 597d890b40SMax Filippov rsr a2, interrupt 607d890b40SMax Filippov wsr a2, intclear 61890c6333SMax Filippov movi a2, 0 627d890b40SMax Filippov wsr a2, ccompare1 637d890b40SMax Filippov wsr a2, ccompare2 647d890b40SMax Filippov 6572b3b8f2SMax Filippov make_ccount_delta a2, a15 667d890b40SMax Filippov wsr a2, ccompare0 677d890b40SMax Filippov1: 6872b3b8f2SMax Filippov rsr a3, interrupt 6972b3b8f2SMax Filippov rsr a4, ccount 7072b3b8f2SMax Filippov rsr a5, interrupt 7172b3b8f2SMax Filippov sub a4, a4, a2 7272b3b8f2SMax Filippov bgez a4, 2f 7372b3b8f2SMax Filippov assert eqi, a3, 0 7472b3b8f2SMax Filippov j 1b 757d890b40SMax Filippov2: 7672b3b8f2SMax Filippov assert nei, a5, 0 777d890b40SMax Filippovtest_end 787d890b40SMax Filippov 797d890b40SMax Filippovtest ccompare0_interrupt 807d890b40SMax Filippov set_vector kernel, 2f 817d890b40SMax Filippov movi a2, 0 827d890b40SMax Filippov wsr a2, intenable 837d890b40SMax Filippov rsr a2, interrupt 847d890b40SMax Filippov wsr a2, intclear 85890c6333SMax Filippov movi a2, 0 867d890b40SMax Filippov wsr a2, ccompare1 877d890b40SMax Filippov wsr a2, ccompare2 887d890b40SMax Filippov 8972b3b8f2SMax Filippov movi a3, WAIT_LOOPS 9072b3b8f2SMax Filippov make_ccount_delta a2, a15 917d890b40SMax Filippov wsr a2, ccompare0 927d890b40SMax Filippov rsync 937d890b40SMax Filippov rsr a2, interrupt 947d890b40SMax Filippov assert eqi, a2, 0 957d890b40SMax Filippov 964f89b41cSMax Filippov movi a2, 1 << XCHAL_TIMER0_INTERRUPT 977d890b40SMax Filippov wsr a2, intenable 987d890b40SMax Filippov rsil a2, 0 997d890b40SMax Filippov loop a3, 1f 1007d890b40SMax Filippov nop 1017d890b40SMax Filippov1: 1027d890b40SMax Filippov test_fail 1037d890b40SMax Filippov2: 1047d890b40SMax Filippov rsr a2, exccause 1057d890b40SMax Filippov assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */ 1067d890b40SMax Filippovtest_end 1077d890b40SMax Filippov 1087d890b40SMax Filippovtest ccompare1_interrupt 1097d890b40SMax Filippov set_vector level3, 2f 1107d890b40SMax Filippov movi a2, 0 1117d890b40SMax Filippov wsr a2, intenable 1127d890b40SMax Filippov rsr a2, interrupt 1137d890b40SMax Filippov wsr a2, intclear 114890c6333SMax Filippov movi a2, 0 1157d890b40SMax Filippov wsr a2, ccompare0 1167d890b40SMax Filippov wsr a2, ccompare2 1177d890b40SMax Filippov 11872b3b8f2SMax Filippov movi a3, WAIT_LOOPS 11972b3b8f2SMax Filippov make_ccount_delta a2, a15 1207d890b40SMax Filippov wsr a2, ccompare1 1217d890b40SMax Filippov rsync 1227d890b40SMax Filippov rsr a2, interrupt 1237d890b40SMax Filippov assert eqi, a2, 0 1244f89b41cSMax Filippov movi a2, 1 << XCHAL_TIMER1_INTERRUPT 1257d890b40SMax Filippov wsr a2, intenable 1267d890b40SMax Filippov rsil a2, 2 1277d890b40SMax Filippov loop a3, 1f 1287d890b40SMax Filippov nop 1297d890b40SMax Filippov1: 1307d890b40SMax Filippov test_fail 1317d890b40SMax Filippov2: 1327d890b40SMax Filippovtest_end 1337d890b40SMax Filippov 1347d890b40SMax Filippovtest ccompare2_interrupt 1357d890b40SMax Filippov set_vector level5, 2f 1367d890b40SMax Filippov movi a2, 0 1377d890b40SMax Filippov wsr a2, intenable 1387d890b40SMax Filippov rsr a2, interrupt 1397d890b40SMax Filippov wsr a2, intclear 140890c6333SMax Filippov movi a2, 0 1417d890b40SMax Filippov wsr a2, ccompare0 1427d890b40SMax Filippov wsr a2, ccompare1 1437d890b40SMax Filippov 14472b3b8f2SMax Filippov movi a3, WAIT_LOOPS 14572b3b8f2SMax Filippov make_ccount_delta a2, a15 1467d890b40SMax Filippov wsr a2, ccompare2 1477d890b40SMax Filippov rsync 1487d890b40SMax Filippov rsr a2, interrupt 1497d890b40SMax Filippov assert eqi, a2, 0 1504f89b41cSMax Filippov movi a2, 1 << XCHAL_TIMER2_INTERRUPT 1517d890b40SMax Filippov wsr a2, intenable 1527d890b40SMax Filippov rsil a2, 4 1537d890b40SMax Filippov loop a3, 1f 1547d890b40SMax Filippov nop 1557d890b40SMax Filippov1: 1567d890b40SMax Filippov test_fail 1577d890b40SMax Filippov2: 1587d890b40SMax Filippovtest_end 1597d890b40SMax Filippov 160890c6333SMax Filippovtest ccompare_interrupt_masked 161890c6333SMax Filippov set_vector kernel, 2f 162890c6333SMax Filippov movi a2, 0 163890c6333SMax Filippov wsr a2, intenable 164890c6333SMax Filippov rsr a2, interrupt 165890c6333SMax Filippov wsr a2, intclear 166890c6333SMax Filippov movi a2, 0 167890c6333SMax Filippov wsr a2, ccompare2 168890c6333SMax Filippov 16972b3b8f2SMax Filippov movi a3, 2 * WAIT_LOOPS 17072b3b8f2SMax Filippov make_ccount_delta a2, a15 171890c6333SMax Filippov wsr a2, ccompare1 17272b3b8f2SMax Filippov add a2, a2, a15 173890c6333SMax Filippov wsr a2, ccompare0 174890c6333SMax Filippov rsync 175890c6333SMax Filippov rsr a2, interrupt 176890c6333SMax Filippov assert eqi, a2, 0 177890c6333SMax Filippov 1784f89b41cSMax Filippov movi a2, 1 << XCHAL_TIMER0_INTERRUPT 179890c6333SMax Filippov wsr a2, intenable 180890c6333SMax Filippov rsil a2, 0 181890c6333SMax Filippov loop a3, 1f 182890c6333SMax Filippov nop 183890c6333SMax Filippov1: 184890c6333SMax Filippov test_fail 185890c6333SMax Filippov2: 186890c6333SMax Filippov rsr a2, exccause 187890c6333SMax Filippov assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */ 188890c6333SMax Filippovtest_end 189890c6333SMax Filippov 190890c6333SMax Filippovtest ccompare_interrupt_masked_waiti 191890c6333SMax Filippov set_vector kernel, 2f 192890c6333SMax Filippov movi a2, 0 193890c6333SMax Filippov wsr a2, intenable 194890c6333SMax Filippov rsr a2, interrupt 195890c6333SMax Filippov wsr a2, intclear 196890c6333SMax Filippov movi a2, 0 197890c6333SMax Filippov wsr a2, ccompare2 198890c6333SMax Filippov 19972b3b8f2SMax Filippov movi a3, 2 * WAIT_LOOPS 20072b3b8f2SMax Filippov make_ccount_delta a2, a15 201890c6333SMax Filippov wsr a2, ccompare1 20272b3b8f2SMax Filippov add a2, a2, a15 203890c6333SMax Filippov wsr a2, ccompare0 204890c6333SMax Filippov rsync 205890c6333SMax Filippov rsr a2, interrupt 206890c6333SMax Filippov assert eqi, a2, 0 207890c6333SMax Filippov 2084f89b41cSMax Filippov movi a2, 1 << XCHAL_TIMER0_INTERRUPT 209890c6333SMax Filippov wsr a2, intenable 210890c6333SMax Filippov waiti 0 211890c6333SMax Filippov test_fail 212890c6333SMax Filippov2: 213890c6333SMax Filippov rsr a2, exccause 214890c6333SMax Filippov assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */ 215890c6333SMax Filippovtest_end 216890c6333SMax Filippov 2177d890b40SMax Filippovtest_suite_end 218