xref: /qemu/tests/tcg/mips/user/ase/dsp/test_dsp_r1_extpv.c (revision 073d9f2ce051d7a4bad9aa7bfdacf97394c57c05)
1*d70080c4SJia Liu #include<stdio.h>
2*d70080c4SJia Liu #include<assert.h>
3*d70080c4SJia Liu 
main()4*d70080c4SJia Liu int main()
5*d70080c4SJia Liu {
6*d70080c4SJia Liu     int rt, ac, ach, acl, dsp;
7*d70080c4SJia Liu     int result;
8*d70080c4SJia Liu 
9*d70080c4SJia Liu     ach = 0x05;
10*d70080c4SJia Liu     acl = 0xB4CB;
11*d70080c4SJia Liu     dsp = 0x07;
12*d70080c4SJia Liu     ac  = 0x03;
13*d70080c4SJia Liu     result = 0x000C;
14*d70080c4SJia Liu 
15*d70080c4SJia Liu     __asm
16*d70080c4SJia Liu         ("wrdsp %1, 0x01\n\t"
17*d70080c4SJia Liu          "mthi %2, $ac1\n\t"
18*d70080c4SJia Liu          "mtlo %3, $ac1\n\t"
19*d70080c4SJia Liu          "extpv %0, $ac1, %4\n\t"
20*d70080c4SJia Liu          "rddsp %1\n\t"
21*d70080c4SJia Liu          : "=r"(rt), "+r"(dsp)
22*d70080c4SJia Liu          : "r"(ach), "r"(acl), "r"(ac)
23*d70080c4SJia Liu         );
24*d70080c4SJia Liu     dsp = (dsp >> 14) & 0x01;
25*d70080c4SJia Liu     assert(dsp == 0);
26*d70080c4SJia Liu     assert(result == rt);
27*d70080c4SJia Liu 
28*d70080c4SJia Liu     ach = 0x05;
29*d70080c4SJia Liu     acl = 0xB4CB;
30*d70080c4SJia Liu     dsp = 0x01;
31*d70080c4SJia Liu 
32*d70080c4SJia Liu     __asm
33*d70080c4SJia Liu         ("wrdsp %1, 0x01\n\t"
34*d70080c4SJia Liu          "mthi %2, $ac1\n\t"
35*d70080c4SJia Liu          "mtlo %3, $ac1\n\t"
36*d70080c4SJia Liu          "extpv %0, $ac1, %4\n\t"
37*d70080c4SJia Liu          "rddsp %1\n\t"
38*d70080c4SJia Liu          : "=r"(rt), "+r"(dsp)
39*d70080c4SJia Liu          : "r"(ach), "r"(acl), "r"(ac)
40*d70080c4SJia Liu         );
41*d70080c4SJia Liu     dsp = (dsp >> 14) & 0x01;
42*d70080c4SJia Liu     assert(dsp == 1);
43*d70080c4SJia Liu 
44*d70080c4SJia Liu     return 0;
45*d70080c4SJia Liu }
46