1 /* 2 * QTest testcase for SDHCI controllers 3 * 4 * Written by Philippe Mathieu-Daudé <f4bug@amsat.org> 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 * SPDX-License-Identifier: GPL-2.0-or-later 9 */ 10 #include "qemu/osdep.h" 11 #include "hw/registerfields.h" 12 #include "libqtest.h" 13 #include "libqos/pci-pc.h" 14 #include "hw/pci/pci.h" 15 16 #define SDHC_CAPAB 0x40 17 FIELD(SDHC_CAPAB, BASECLKFREQ, 8, 8); /* since v2 */ 18 FIELD(SDHC_CAPAB, SDMA, 22, 1); 19 #define SDHC_HCVER 0xFE 20 21 static const struct sdhci_t { 22 const char *arch, *machine; 23 struct { 24 uintptr_t addr; 25 uint8_t version; 26 uint8_t baseclock; 27 struct { 28 bool sdma; 29 uint64_t reg; 30 } capab; 31 } sdhci; 32 struct { 33 uint16_t vendor_id, device_id; 34 } pci; 35 } models[] = { 36 /* PC via PCI */ 37 { "x86_64", "pc", 38 {-1, 2, 0, {1, 0x057834b4} }, 39 .pci = { PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_SDHCI } }, 40 41 /* Exynos4210 */ 42 { "arm", "smdkc210", 43 {0x12510000, 2, 0, {1, 0x5e80080} } }, 44 }; 45 46 typedef struct QSDHCI { 47 struct { 48 QPCIBus *bus; 49 QPCIDevice *dev; 50 } pci; 51 union { 52 QPCIBar mem_bar; 53 uint64_t addr; 54 }; 55 } QSDHCI; 56 57 static uint64_t sdhci_readq(QSDHCI *s, uint32_t reg) 58 { 59 uint64_t val; 60 61 if (s->pci.dev) { 62 val = qpci_io_readq(s->pci.dev, s->mem_bar, reg); 63 } else { 64 val = qtest_readq(global_qtest, s->addr + reg); 65 } 66 67 return val; 68 } 69 70 static void sdhci_writeq(QSDHCI *s, uint32_t reg, uint64_t val) 71 { 72 if (s->pci.dev) { 73 qpci_io_writeq(s->pci.dev, s->mem_bar, reg, val); 74 } else { 75 qtest_writeq(global_qtest, s->addr + reg, val); 76 } 77 } 78 79 static void check_capab_capareg(QSDHCI *s, uint64_t expec_capab) 80 { 81 uint64_t capab; 82 83 capab = sdhci_readq(s, SDHC_CAPAB); 84 g_assert_cmphex(capab, ==, expec_capab); 85 } 86 87 static void check_capab_readonly(QSDHCI *s) 88 { 89 const uint64_t vrand = 0x123456789abcdef; 90 uint64_t capab0, capab1; 91 92 capab0 = sdhci_readq(s, SDHC_CAPAB); 93 g_assert_cmpuint(capab0, !=, vrand); 94 95 sdhci_writeq(s, SDHC_CAPAB, vrand); 96 capab1 = sdhci_readq(s, SDHC_CAPAB); 97 g_assert_cmpuint(capab1, !=, vrand); 98 g_assert_cmpuint(capab1, ==, capab0); 99 } 100 101 static void check_capab_baseclock(QSDHCI *s, uint8_t expec_freq) 102 { 103 uint64_t capab, capab_freq; 104 105 if (!expec_freq) { 106 return; 107 } 108 capab = sdhci_readq(s, SDHC_CAPAB); 109 capab_freq = FIELD_EX64(capab, SDHC_CAPAB, BASECLKFREQ); 110 g_assert_cmpuint(capab_freq, ==, expec_freq); 111 } 112 113 static void check_capab_sdma(QSDHCI *s, bool supported) 114 { 115 uint64_t capab, capab_sdma; 116 117 capab = sdhci_readq(s, SDHC_CAPAB); 118 capab_sdma = FIELD_EX64(capab, SDHC_CAPAB, SDMA); 119 g_assert_cmpuint(capab_sdma, ==, supported); 120 } 121 122 static QSDHCI *machine_start(const struct sdhci_t *test) 123 { 124 QSDHCI *s = g_new0(QSDHCI, 1); 125 126 if (test->pci.vendor_id) { 127 /* PCI */ 128 uint16_t vendor_id, device_id; 129 uint64_t barsize; 130 131 global_qtest = qtest_startf("-machine %s -device sdhci-pci", 132 test->machine); 133 134 s->pci.bus = qpci_init_pc(NULL); 135 136 /* Find PCI device and verify it's the right one */ 137 s->pci.dev = qpci_device_find(s->pci.bus, QPCI_DEVFN(4, 0)); 138 g_assert_nonnull(s->pci.dev); 139 vendor_id = qpci_config_readw(s->pci.dev, PCI_VENDOR_ID); 140 device_id = qpci_config_readw(s->pci.dev, PCI_DEVICE_ID); 141 g_assert(vendor_id == test->pci.vendor_id); 142 g_assert(device_id == test->pci.device_id); 143 s->mem_bar = qpci_iomap(s->pci.dev, 0, &barsize); 144 qpci_device_enable(s->pci.dev); 145 } else { 146 /* SysBus */ 147 global_qtest = qtest_startf("-machine %s", test->machine); 148 s->addr = test->sdhci.addr; 149 } 150 151 return s; 152 } 153 154 static void machine_stop(QSDHCI *s) 155 { 156 g_free(s->pci.dev); 157 qtest_quit(global_qtest); 158 } 159 160 static void test_machine(const void *data) 161 { 162 const struct sdhci_t *test = data; 163 QSDHCI *s; 164 165 s = machine_start(test); 166 167 check_capab_capareg(s, test->sdhci.capab.reg); 168 check_capab_readonly(s); 169 check_capab_sdma(s, test->sdhci.capab.sdma); 170 check_capab_baseclock(s, test->sdhci.baseclock); 171 172 machine_stop(s); 173 } 174 175 int main(int argc, char *argv[]) 176 { 177 const char *arch = qtest_get_arch(); 178 char *name; 179 int i; 180 181 g_test_init(&argc, &argv, NULL); 182 for (i = 0; i < ARRAY_SIZE(models); i++) { 183 if (strcmp(arch, models[i].arch)) { 184 continue; 185 } 186 name = g_strdup_printf("sdhci/%s", models[i].machine); 187 qtest_add_data_func(name, &models[i], test_machine); 188 g_free(name); 189 } 190 191 return g_test_run(); 192 } 193