1 /* 2 * QTest testcase for SDHCI controllers 3 * 4 * Written by Philippe Mathieu-Daudé <f4bug@amsat.org> 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 * SPDX-License-Identifier: GPL-2.0-or-later 9 */ 10 #include "qemu/osdep.h" 11 #include "hw/registerfields.h" 12 #include "libqtest.h" 13 #include "libqos/pci-pc.h" 14 #include "hw/pci/pci.h" 15 16 #define SDHC_CAPAB 0x40 17 FIELD(SDHC_CAPAB, BASECLKFREQ, 8, 8); /* since v2 */ 18 FIELD(SDHC_CAPAB, SDMA, 22, 1); 19 #define SDHC_HCVER 0xFE 20 21 static const struct sdhci_t { 22 const char *arch, *machine; 23 struct { 24 uintptr_t addr; 25 uint8_t version; 26 uint8_t baseclock; 27 struct { 28 bool sdma; 29 uint64_t reg; 30 } capab; 31 } sdhci; 32 struct { 33 uint16_t vendor_id, device_id; 34 } pci; 35 } models[] = { 36 /* PC via PCI */ 37 { "x86_64", "pc", 38 {-1, 2, 0, {1, 0x057834b4} }, 39 .pci = { PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_SDHCI } }, 40 41 /* Exynos4210 */ 42 { "arm", "smdkc210", 43 {0x12510000, 2, 0, {1, 0x5e80080} } }, 44 45 /* Zynq-7000 */ 46 { "arm", "xilinx-zynq-a9", /* Datasheet: UG585 (v1.12.1) */ 47 {0xe0100000, 2, 0, {1, 0x69ec0080} } }, 48 49 }; 50 51 typedef struct QSDHCI { 52 struct { 53 QPCIBus *bus; 54 QPCIDevice *dev; 55 } pci; 56 union { 57 QPCIBar mem_bar; 58 uint64_t addr; 59 }; 60 } QSDHCI; 61 62 static uint16_t sdhci_readw(QSDHCI *s, uint32_t reg) 63 { 64 uint16_t val; 65 66 if (s->pci.dev) { 67 val = qpci_io_readw(s->pci.dev, s->mem_bar, reg); 68 } else { 69 val = qtest_readw(global_qtest, s->addr + reg); 70 } 71 72 return val; 73 } 74 75 static uint64_t sdhci_readq(QSDHCI *s, uint32_t reg) 76 { 77 uint64_t val; 78 79 if (s->pci.dev) { 80 val = qpci_io_readq(s->pci.dev, s->mem_bar, reg); 81 } else { 82 val = qtest_readq(global_qtest, s->addr + reg); 83 } 84 85 return val; 86 } 87 88 static void sdhci_writeq(QSDHCI *s, uint32_t reg, uint64_t val) 89 { 90 if (s->pci.dev) { 91 qpci_io_writeq(s->pci.dev, s->mem_bar, reg, val); 92 } else { 93 qtest_writeq(global_qtest, s->addr + reg, val); 94 } 95 } 96 97 static void check_specs_version(QSDHCI *s, uint8_t version) 98 { 99 uint32_t v; 100 101 v = sdhci_readw(s, SDHC_HCVER); 102 v &= 0xff; 103 v += 1; 104 g_assert_cmpuint(v, ==, version); 105 } 106 107 static void check_capab_capareg(QSDHCI *s, uint64_t expec_capab) 108 { 109 uint64_t capab; 110 111 capab = sdhci_readq(s, SDHC_CAPAB); 112 g_assert_cmphex(capab, ==, expec_capab); 113 } 114 115 static void check_capab_readonly(QSDHCI *s) 116 { 117 const uint64_t vrand = 0x123456789abcdef; 118 uint64_t capab0, capab1; 119 120 capab0 = sdhci_readq(s, SDHC_CAPAB); 121 g_assert_cmpuint(capab0, !=, vrand); 122 123 sdhci_writeq(s, SDHC_CAPAB, vrand); 124 capab1 = sdhci_readq(s, SDHC_CAPAB); 125 g_assert_cmpuint(capab1, !=, vrand); 126 g_assert_cmpuint(capab1, ==, capab0); 127 } 128 129 static void check_capab_baseclock(QSDHCI *s, uint8_t expec_freq) 130 { 131 uint64_t capab, capab_freq; 132 133 if (!expec_freq) { 134 return; 135 } 136 capab = sdhci_readq(s, SDHC_CAPAB); 137 capab_freq = FIELD_EX64(capab, SDHC_CAPAB, BASECLKFREQ); 138 g_assert_cmpuint(capab_freq, ==, expec_freq); 139 } 140 141 static void check_capab_sdma(QSDHCI *s, bool supported) 142 { 143 uint64_t capab, capab_sdma; 144 145 capab = sdhci_readq(s, SDHC_CAPAB); 146 capab_sdma = FIELD_EX64(capab, SDHC_CAPAB, SDMA); 147 g_assert_cmpuint(capab_sdma, ==, supported); 148 } 149 150 static QSDHCI *machine_start(const struct sdhci_t *test) 151 { 152 QSDHCI *s = g_new0(QSDHCI, 1); 153 154 if (test->pci.vendor_id) { 155 /* PCI */ 156 uint16_t vendor_id, device_id; 157 uint64_t barsize; 158 159 global_qtest = qtest_startf("-machine %s -device sdhci-pci", 160 test->machine); 161 162 s->pci.bus = qpci_init_pc(NULL); 163 164 /* Find PCI device and verify it's the right one */ 165 s->pci.dev = qpci_device_find(s->pci.bus, QPCI_DEVFN(4, 0)); 166 g_assert_nonnull(s->pci.dev); 167 vendor_id = qpci_config_readw(s->pci.dev, PCI_VENDOR_ID); 168 device_id = qpci_config_readw(s->pci.dev, PCI_DEVICE_ID); 169 g_assert(vendor_id == test->pci.vendor_id); 170 g_assert(device_id == test->pci.device_id); 171 s->mem_bar = qpci_iomap(s->pci.dev, 0, &barsize); 172 qpci_device_enable(s->pci.dev); 173 } else { 174 /* SysBus */ 175 global_qtest = qtest_startf("-machine %s", test->machine); 176 s->addr = test->sdhci.addr; 177 } 178 179 return s; 180 } 181 182 static void machine_stop(QSDHCI *s) 183 { 184 g_free(s->pci.dev); 185 qtest_quit(global_qtest); 186 } 187 188 static void test_machine(const void *data) 189 { 190 const struct sdhci_t *test = data; 191 QSDHCI *s; 192 193 s = machine_start(test); 194 195 check_specs_version(s, test->sdhci.version); 196 check_capab_capareg(s, test->sdhci.capab.reg); 197 check_capab_readonly(s); 198 check_capab_sdma(s, test->sdhci.capab.sdma); 199 check_capab_baseclock(s, test->sdhci.baseclock); 200 201 machine_stop(s); 202 } 203 204 int main(int argc, char *argv[]) 205 { 206 const char *arch = qtest_get_arch(); 207 char *name; 208 int i; 209 210 g_test_init(&argc, &argv, NULL); 211 for (i = 0; i < ARRAY_SIZE(models); i++) { 212 if (strcmp(arch, models[i].arch)) { 213 continue; 214 } 215 name = g_strdup_printf("sdhci/%s", models[i].machine); 216 qtest_add_data_func(name, &models[i], test_machine); 217 g_free(name); 218 } 219 220 return g_test_run(); 221 } 222