1 /* 2 * QTest testcase for SDHCI controllers 3 * 4 * Written by Philippe Mathieu-Daudé <f4bug@amsat.org> 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 * SPDX-License-Identifier: GPL-2.0-or-later 9 */ 10 #include "qemu/osdep.h" 11 #include "hw/registerfields.h" 12 #include "libqtest.h" 13 #include "libqos/pci-pc.h" 14 #include "hw/pci/pci.h" 15 16 #define SDHC_CAPAB 0x40 17 FIELD(SDHC_CAPAB, BASECLKFREQ, 8, 8); /* since v2 */ 18 FIELD(SDHC_CAPAB, SDMA, 22, 1); 19 #define SDHC_HCVER 0xFE 20 21 static const struct sdhci_t { 22 const char *arch, *machine; 23 struct { 24 uintptr_t addr; 25 uint8_t version; 26 uint8_t baseclock; 27 struct { 28 bool sdma; 29 uint64_t reg; 30 } capab; 31 } sdhci; 32 struct { 33 uint16_t vendor_id, device_id; 34 } pci; 35 } models[] = { 36 /* PC via PCI */ 37 { "x86_64", "pc", 38 {-1, 2, 0, {1, 0x057834b4} }, 39 .pci = { PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_SDHCI } }, 40 41 /* Exynos4210 */ 42 { "arm", "smdkc210", 43 {0x12510000, 2, 0, {1, 0x5e80080} } }, 44 45 /* i.MX 6 */ 46 { "arm", "sabrelite", 47 {0x02190000, 3, 0, {1, 0x057834b4} } }, 48 49 /* BCM2835 */ 50 { "arm", "raspi2", 51 {0x3f300000, 3, 52, {0, 0x052134b4} } }, 52 53 /* Zynq-7000 */ 54 { "arm", "xilinx-zynq-a9", /* Datasheet: UG585 (v1.12.1) */ 55 {0xe0100000, 2, 0, {1, 0x69ec0080} } }, 56 57 /* ZynqMP */ 58 { "aarch64", "xlnx-zcu102", /* Datasheet: UG1085 (v1.7) */ 59 {0xff160000, 3, 0, {1, 0x280737ec6481} } }, 60 61 }; 62 63 typedef struct QSDHCI { 64 struct { 65 QPCIBus *bus; 66 QPCIDevice *dev; 67 } pci; 68 union { 69 QPCIBar mem_bar; 70 uint64_t addr; 71 }; 72 } QSDHCI; 73 74 static uint16_t sdhci_readw(QSDHCI *s, uint32_t reg) 75 { 76 uint16_t val; 77 78 if (s->pci.dev) { 79 val = qpci_io_readw(s->pci.dev, s->mem_bar, reg); 80 } else { 81 val = qtest_readw(global_qtest, s->addr + reg); 82 } 83 84 return val; 85 } 86 87 static uint64_t sdhci_readq(QSDHCI *s, uint32_t reg) 88 { 89 uint64_t val; 90 91 if (s->pci.dev) { 92 val = qpci_io_readq(s->pci.dev, s->mem_bar, reg); 93 } else { 94 val = qtest_readq(global_qtest, s->addr + reg); 95 } 96 97 return val; 98 } 99 100 static void sdhci_writeq(QSDHCI *s, uint32_t reg, uint64_t val) 101 { 102 if (s->pci.dev) { 103 qpci_io_writeq(s->pci.dev, s->mem_bar, reg, val); 104 } else { 105 qtest_writeq(global_qtest, s->addr + reg, val); 106 } 107 } 108 109 static void check_specs_version(QSDHCI *s, uint8_t version) 110 { 111 uint32_t v; 112 113 v = sdhci_readw(s, SDHC_HCVER); 114 v &= 0xff; 115 v += 1; 116 g_assert_cmpuint(v, ==, version); 117 } 118 119 static void check_capab_capareg(QSDHCI *s, uint64_t expec_capab) 120 { 121 uint64_t capab; 122 123 capab = sdhci_readq(s, SDHC_CAPAB); 124 g_assert_cmphex(capab, ==, expec_capab); 125 } 126 127 static void check_capab_readonly(QSDHCI *s) 128 { 129 const uint64_t vrand = 0x123456789abcdef; 130 uint64_t capab0, capab1; 131 132 capab0 = sdhci_readq(s, SDHC_CAPAB); 133 g_assert_cmpuint(capab0, !=, vrand); 134 135 sdhci_writeq(s, SDHC_CAPAB, vrand); 136 capab1 = sdhci_readq(s, SDHC_CAPAB); 137 g_assert_cmpuint(capab1, !=, vrand); 138 g_assert_cmpuint(capab1, ==, capab0); 139 } 140 141 static void check_capab_baseclock(QSDHCI *s, uint8_t expec_freq) 142 { 143 uint64_t capab, capab_freq; 144 145 if (!expec_freq) { 146 return; 147 } 148 capab = sdhci_readq(s, SDHC_CAPAB); 149 capab_freq = FIELD_EX64(capab, SDHC_CAPAB, BASECLKFREQ); 150 g_assert_cmpuint(capab_freq, ==, expec_freq); 151 } 152 153 static void check_capab_sdma(QSDHCI *s, bool supported) 154 { 155 uint64_t capab, capab_sdma; 156 157 capab = sdhci_readq(s, SDHC_CAPAB); 158 capab_sdma = FIELD_EX64(capab, SDHC_CAPAB, SDMA); 159 g_assert_cmpuint(capab_sdma, ==, supported); 160 } 161 162 static QSDHCI *machine_start(const struct sdhci_t *test) 163 { 164 QSDHCI *s = g_new0(QSDHCI, 1); 165 166 if (test->pci.vendor_id) { 167 /* PCI */ 168 uint16_t vendor_id, device_id; 169 uint64_t barsize; 170 171 global_qtest = qtest_startf("-machine %s -device sdhci-pci", 172 test->machine); 173 174 s->pci.bus = qpci_init_pc(NULL); 175 176 /* Find PCI device and verify it's the right one */ 177 s->pci.dev = qpci_device_find(s->pci.bus, QPCI_DEVFN(4, 0)); 178 g_assert_nonnull(s->pci.dev); 179 vendor_id = qpci_config_readw(s->pci.dev, PCI_VENDOR_ID); 180 device_id = qpci_config_readw(s->pci.dev, PCI_DEVICE_ID); 181 g_assert(vendor_id == test->pci.vendor_id); 182 g_assert(device_id == test->pci.device_id); 183 s->mem_bar = qpci_iomap(s->pci.dev, 0, &barsize); 184 qpci_device_enable(s->pci.dev); 185 } else { 186 /* SysBus */ 187 global_qtest = qtest_startf("-machine %s", test->machine); 188 s->addr = test->sdhci.addr; 189 } 190 191 return s; 192 } 193 194 static void machine_stop(QSDHCI *s) 195 { 196 g_free(s->pci.dev); 197 qtest_quit(global_qtest); 198 } 199 200 static void test_machine(const void *data) 201 { 202 const struct sdhci_t *test = data; 203 QSDHCI *s; 204 205 s = machine_start(test); 206 207 check_specs_version(s, test->sdhci.version); 208 check_capab_capareg(s, test->sdhci.capab.reg); 209 check_capab_readonly(s); 210 check_capab_sdma(s, test->sdhci.capab.sdma); 211 check_capab_baseclock(s, test->sdhci.baseclock); 212 213 machine_stop(s); 214 } 215 216 int main(int argc, char *argv[]) 217 { 218 const char *arch = qtest_get_arch(); 219 char *name; 220 int i; 221 222 g_test_init(&argc, &argv, NULL); 223 for (i = 0; i < ARRAY_SIZE(models); i++) { 224 if (strcmp(arch, models[i].arch)) { 225 continue; 226 } 227 name = g_strdup_printf("sdhci/%s", models[i].machine); 228 qtest_add_data_func(name, &models[i], test_machine); 229 g_free(name); 230 } 231 232 return g_test_run(); 233 } 234