xref: /qemu/tests/qtest/libqos/sdhci-cmd.h (revision 07f0d32641e04703e6ed9626d06179060ea772ca)
1  /*
2   * MMC Host Controller Commands
3   *
4   * Copyright (c) 2021 Google LLC
5   *
6   * This program is free software; you can redistribute it and/or modify it
7   * under the terms of the GNU General Public License as published by the
8   * Free Software Foundation; either version 2 of the License, or
9   * (at your option) any later version.
10   *
11   * This program is distributed in the hope that it will be useful, but WITHOUT
12   * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13   * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14   * for more details.
15   */
16  
17  #include "../libqtest.h"
18  
19  /* more details at hw/sd/sdhci-internal.h */
20  #define SDHC_BLKSIZE 0x04
21  #define SDHC_BLKCNT 0x06
22  #define SDHC_ARGUMENT 0x08
23  #define SDHC_TRNMOD 0x0C
24  #define SDHC_CMDREG 0x0E
25  #define SDHC_RSPREG0 0x10
26  #define SDHC_BDATA 0x20
27  #define SDHC_PRNSTS 0x24
28  #define SDHC_BLKGAP 0x2A
29  #define SDHC_CLKCON 0x2C
30  #define SDHC_SWRST 0x2F
31  #define SDHC_CAPAB 0x40
32  #define SDHC_MAXCURR 0x48
33  #define SDHC_HCVER 0xFE
34  
35  /* TRNSMOD Reg */
36  #define SDHC_TRNS_BLK_CNT_EN 0x0002
37  #define SDHC_TRNS_READ 0x0010
38  #define SDHC_TRNS_WRITE 0x0000
39  #define SDHC_TRNS_MULTI 0x0020
40  
41  /* CMD Reg */
42  #define SDHC_CMD_RESPONSE (3 << 0)
43  #define SDHC_CMD_DATA_PRESENT (1 << 5)
44  #define SDHC_ALL_SEND_CID (2 << 8)
45  #define SDHC_SEND_RELATIVE_ADDR (3 << 8)
46  #define SDHC_SELECT_DESELECT_CARD (7 << 8)
47  #define SDHC_SEND_CSD (9 << 8)
48  #define SDHC_STOP_TRANSMISSION (12 << 8)
49  #define SDHC_READ_MULTIPLE_BLOCK (18 << 8)
50  #define SDHC_WRITE_MULTIPLE_BLOCK (25 << 8)
51  #define SDHC_APP_CMD (55 << 8)
52  
53  /* SWRST Reg */
54  #define SDHC_RESET_ALL 0x01
55  
56  /* CLKCTRL Reg */
57  #define SDHC_CLOCK_INT_EN 0x0001
58  #define SDHC_CLOCK_INT_STABLE 0x0002
59  #define SDHC_CLOCK_SDCLK_EN (1 << 2)
60  
61  /* Set registers needed to send commands to SD */
62  void sdhci_cmd_regs(QTestState *qts, uint64_t base_addr, uint16_t blksize,
63                      uint16_t blkcnt, uint32_t argument, uint16_t trnmod,
64                      uint16_t cmdreg);
65  
66  /* Read at most 1 block of SD using non-DMA  */
67  ssize_t sdhci_read_cmd(QTestState *qts, uint64_t base_addr, char *msg,
68                         size_t count);
69  
70  /* Write at most 1 block of SD using non-DMA  */
71  void sdhci_write_cmd(QTestState *qts, uint64_t base_addr, const char *msg,
72                       size_t count, size_t blksize);
73