1 /* 2 * QTest testcase for intel-iommu 3 * 4 * Copyright (c) 2024 Intel, Inc. 5 * 6 * Author: Zhenzhong Duan <zhenzhong.duan@intel.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0-or-later 9 */ 10 11 #include "qemu/osdep.h" 12 #include "libqtest.h" 13 #include "hw/i386/intel_iommu_internal.h" 14 15 #define CAP_STAGE_1_FIXED1 (VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND | \ 16 VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SLLPS) 17 #define ECAP_STAGE_1_FIXED1 (VTD_ECAP_QI | VTD_ECAP_IR | VTD_ECAP_IRO | \ 18 VTD_ECAP_MHMV | VTD_ECAP_SMTS | VTD_ECAP_FLTS) 19 20 static inline uint64_t vtd_reg_readq(QTestState *s, uint64_t offset) 21 { 22 return qtest_readq(s, Q35_HOST_BRIDGE_IOMMU_ADDR + offset); 23 } 24 25 static void test_intel_iommu_stage_1(void) 26 { 27 uint8_t init_csr[DMAR_REG_SIZE]; /* register values */ 28 uint8_t post_reset_csr[DMAR_REG_SIZE]; /* register values */ 29 uint64_t cap, ecap, tmp; 30 QTestState *s; 31 32 s = qtest_init("-M q35 -device intel-iommu,x-scalable-mode=on,x-flts=on"); 33 34 cap = vtd_reg_readq(s, DMAR_CAP_REG); 35 g_assert((cap & CAP_STAGE_1_FIXED1) == CAP_STAGE_1_FIXED1); 36 37 tmp = cap & VTD_CAP_SAGAW_MASK; 38 g_assert(tmp == (VTD_CAP_SAGAW_39bit | VTD_CAP_SAGAW_48bit)); 39 40 tmp = VTD_MGAW_FROM_CAP(cap); 41 g_assert(tmp == VTD_HOST_AW_48BIT - 1); 42 43 ecap = vtd_reg_readq(s, DMAR_ECAP_REG); 44 g_assert((ecap & ECAP_STAGE_1_FIXED1) == ECAP_STAGE_1_FIXED1); 45 46 qtest_memread(s, Q35_HOST_BRIDGE_IOMMU_ADDR, init_csr, DMAR_REG_SIZE); 47 48 qobject_unref(qtest_qmp(s, "{ 'execute': 'system_reset' }")); 49 qtest_qmp_eventwait(s, "RESET"); 50 51 qtest_memread(s, Q35_HOST_BRIDGE_IOMMU_ADDR, post_reset_csr, DMAR_REG_SIZE); 52 /* Ensure registers are consistent after hard reset */ 53 g_assert(!memcmp(init_csr, post_reset_csr, DMAR_REG_SIZE)); 54 55 qtest_quit(s); 56 } 57 58 int main(int argc, char **argv) 59 { 60 g_test_init(&argc, &argv, NULL); 61 qtest_add_func("/q35/intel-iommu/stage-1", test_intel_iommu_stage_1); 62 63 return g_test_run(); 64 } 65