1 /* 2 * IDE test cases 3 * 4 * Copyright (c) 2013 Kevin Wolf <kwolf@redhat.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 27 28 #include "libqtest.h" 29 #include "libqos/libqos.h" 30 #include "libqos/pci-pc.h" 31 #include "libqos/malloc-pc.h" 32 33 #include "qemu-common.h" 34 #include "qemu/bswap.h" 35 #include "hw/pci/pci_ids.h" 36 #include "hw/pci/pci_regs.h" 37 38 #define TEST_IMAGE_SIZE 64 * 1024 * 1024 39 40 #define IDE_PCI_DEV 1 41 #define IDE_PCI_FUNC 1 42 43 #define IDE_BASE 0x1f0 44 #define IDE_PRIMARY_IRQ 14 45 46 #define ATAPI_BLOCK_SIZE 2048 47 48 /* How many bytes to receive via ATAPI PIO at one time. 49 * Must be less than 0xFFFF. */ 50 #define BYTE_COUNT_LIMIT 5120 51 52 enum { 53 reg_data = 0x0, 54 reg_feature = 0x1, 55 reg_nsectors = 0x2, 56 reg_lba_low = 0x3, 57 reg_lba_middle = 0x4, 58 reg_lba_high = 0x5, 59 reg_device = 0x6, 60 reg_status = 0x7, 61 reg_command = 0x7, 62 }; 63 64 enum { 65 BSY = 0x80, 66 DRDY = 0x40, 67 DF = 0x20, 68 DRQ = 0x08, 69 ERR = 0x01, 70 }; 71 72 enum { 73 DEV = 0x10, 74 LBA = 0x40, 75 }; 76 77 enum { 78 bmreg_cmd = 0x0, 79 bmreg_status = 0x2, 80 bmreg_prdt = 0x4, 81 }; 82 83 enum { 84 CMD_READ_DMA = 0xc8, 85 CMD_WRITE_DMA = 0xca, 86 CMD_FLUSH_CACHE = 0xe7, 87 CMD_IDENTIFY = 0xec, 88 CMD_PACKET = 0xa0, 89 90 CMDF_ABORT = 0x100, 91 CMDF_NO_BM = 0x200, 92 }; 93 94 enum { 95 BM_CMD_START = 0x1, 96 BM_CMD_WRITE = 0x8, /* write = from device to memory */ 97 }; 98 99 enum { 100 BM_STS_ACTIVE = 0x1, 101 BM_STS_ERROR = 0x2, 102 BM_STS_INTR = 0x4, 103 }; 104 105 enum { 106 PRDT_EOT = 0x80000000, 107 }; 108 109 #define assert_bit_set(data, mask) g_assert_cmphex((data) & (mask), ==, (mask)) 110 #define assert_bit_clear(data, mask) g_assert_cmphex((data) & (mask), ==, 0) 111 112 static QPCIBus *pcibus = NULL; 113 static QGuestAllocator *guest_malloc; 114 115 static char tmp_path[] = "/tmp/qtest.XXXXXX"; 116 static char debug_path[] = "/tmp/qtest-blkdebug.XXXXXX"; 117 118 static void ide_test_start(const char *cmdline_fmt, ...) 119 { 120 va_list ap; 121 char *cmdline; 122 123 va_start(ap, cmdline_fmt); 124 cmdline = g_strdup_vprintf(cmdline_fmt, ap); 125 va_end(ap); 126 127 qtest_start(cmdline); 128 guest_malloc = pc_alloc_init(); 129 130 g_free(cmdline); 131 } 132 133 static void ide_test_quit(void) 134 { 135 pc_alloc_uninit(guest_malloc); 136 guest_malloc = NULL; 137 qtest_end(); 138 } 139 140 static QPCIDevice *get_pci_device(void **bmdma_base, void **ide_base) 141 { 142 QPCIDevice *dev; 143 uint16_t vendor_id, device_id; 144 145 if (!pcibus) { 146 pcibus = qpci_init_pc(NULL); 147 } 148 149 /* Find PCI device and verify it's the right one */ 150 dev = qpci_device_find(pcibus, QPCI_DEVFN(IDE_PCI_DEV, IDE_PCI_FUNC)); 151 g_assert(dev != NULL); 152 153 vendor_id = qpci_config_readw(dev, PCI_VENDOR_ID); 154 device_id = qpci_config_readw(dev, PCI_DEVICE_ID); 155 g_assert(vendor_id == PCI_VENDOR_ID_INTEL); 156 g_assert(device_id == PCI_DEVICE_ID_INTEL_82371SB_1); 157 158 /* Map bmdma BAR */ 159 *bmdma_base = qpci_iomap(dev, 4, NULL); 160 161 *ide_base = qpci_legacy_iomap(dev, IDE_BASE); 162 163 qpci_device_enable(dev); 164 165 return dev; 166 } 167 168 static void free_pci_device(QPCIDevice *dev) 169 { 170 /* libqos doesn't have a function for this, so free it manually */ 171 g_free(dev); 172 } 173 174 typedef struct PrdtEntry { 175 uint32_t addr; 176 uint32_t size; 177 } QEMU_PACKED PrdtEntry; 178 179 #define assert_bit_set(data, mask) g_assert_cmphex((data) & (mask), ==, (mask)) 180 #define assert_bit_clear(data, mask) g_assert_cmphex((data) & (mask), ==, 0) 181 182 static int send_dma_request(int cmd, uint64_t sector, int nb_sectors, 183 PrdtEntry *prdt, int prdt_entries, 184 void(*post_exec)(QPCIDevice *dev, void *ide_base, 185 uint64_t sector, int nb_sectors)) 186 { 187 QPCIDevice *dev; 188 void *bmdma_base; 189 void *ide_base; 190 uintptr_t guest_prdt; 191 size_t len; 192 bool from_dev; 193 uint8_t status; 194 int flags; 195 196 dev = get_pci_device(&bmdma_base, &ide_base); 197 198 flags = cmd & ~0xff; 199 cmd &= 0xff; 200 201 switch (cmd) { 202 case CMD_READ_DMA: 203 case CMD_PACKET: 204 /* Assuming we only test data reads w/ ATAPI, otherwise we need to know 205 * the SCSI command being sent in the packet, too. */ 206 from_dev = true; 207 break; 208 case CMD_WRITE_DMA: 209 from_dev = false; 210 break; 211 default: 212 g_assert_not_reached(); 213 } 214 215 if (flags & CMDF_NO_BM) { 216 qpci_config_writew(dev, PCI_COMMAND, 217 PCI_COMMAND_IO | PCI_COMMAND_MEMORY); 218 } 219 220 /* Select device 0 */ 221 qpci_io_writeb(dev, ide_base + reg_device, 0 | LBA); 222 223 /* Stop any running transfer, clear any pending interrupt */ 224 qpci_io_writeb(dev, bmdma_base + bmreg_cmd, 0); 225 qpci_io_writeb(dev, bmdma_base + bmreg_status, BM_STS_INTR); 226 227 /* Setup PRDT */ 228 len = sizeof(*prdt) * prdt_entries; 229 guest_prdt = guest_alloc(guest_malloc, len); 230 memwrite(guest_prdt, prdt, len); 231 qpci_io_writel(dev, bmdma_base + bmreg_prdt, guest_prdt); 232 233 /* ATA DMA command */ 234 if (cmd == CMD_PACKET) { 235 /* Enables ATAPI DMA; otherwise PIO is attempted */ 236 qpci_io_writeb(dev, ide_base + reg_feature, 0x01); 237 } else { 238 qpci_io_writeb(dev, ide_base + reg_nsectors, nb_sectors); 239 qpci_io_writeb(dev, ide_base + reg_lba_low, sector & 0xff); 240 qpci_io_writeb(dev, ide_base + reg_lba_middle, (sector >> 8) & 0xff); 241 qpci_io_writeb(dev, ide_base + reg_lba_high, (sector >> 16) & 0xff); 242 } 243 244 qpci_io_writeb(dev, ide_base + reg_command, cmd); 245 246 if (post_exec) { 247 post_exec(dev, ide_base, sector, nb_sectors); 248 } 249 250 /* Start DMA transfer */ 251 qpci_io_writeb(dev, bmdma_base + bmreg_cmd, 252 BM_CMD_START | (from_dev ? BM_CMD_WRITE : 0)); 253 254 if (flags & CMDF_ABORT) { 255 qpci_io_writeb(dev, bmdma_base + bmreg_cmd, 0); 256 } 257 258 /* Wait for the DMA transfer to complete */ 259 do { 260 status = qpci_io_readb(dev, bmdma_base + bmreg_status); 261 } while ((status & (BM_STS_ACTIVE | BM_STS_INTR)) == BM_STS_ACTIVE); 262 263 g_assert_cmpint(get_irq(IDE_PRIMARY_IRQ), ==, !!(status & BM_STS_INTR)); 264 265 /* Check IDE status code */ 266 assert_bit_set(qpci_io_readb(dev, ide_base + reg_status), DRDY); 267 assert_bit_clear(qpci_io_readb(dev, ide_base + reg_status), BSY | DRQ); 268 269 /* Reading the status register clears the IRQ */ 270 g_assert(!get_irq(IDE_PRIMARY_IRQ)); 271 272 /* Stop DMA transfer if still active */ 273 if (status & BM_STS_ACTIVE) { 274 qpci_io_writeb(dev, bmdma_base + bmreg_cmd, 0); 275 } 276 277 free_pci_device(dev); 278 279 return status; 280 } 281 282 static void test_bmdma_simple_rw(void) 283 { 284 QPCIDevice *dev; 285 void *bmdma_base, *ide_base; 286 uint8_t status; 287 uint8_t *buf; 288 uint8_t *cmpbuf; 289 size_t len = 512; 290 uintptr_t guest_buf = guest_alloc(guest_malloc, len); 291 292 PrdtEntry prdt[] = { 293 { 294 .addr = cpu_to_le32(guest_buf), 295 .size = cpu_to_le32(len | PRDT_EOT), 296 }, 297 }; 298 299 dev = get_pci_device(&bmdma_base, &ide_base); 300 301 buf = g_malloc(len); 302 cmpbuf = g_malloc(len); 303 304 /* Write 0x55 pattern to sector 0 */ 305 memset(buf, 0x55, len); 306 memwrite(guest_buf, buf, len); 307 308 status = send_dma_request(CMD_WRITE_DMA, 0, 1, prdt, 309 ARRAY_SIZE(prdt), NULL); 310 g_assert_cmphex(status, ==, BM_STS_INTR); 311 assert_bit_clear(qpci_io_readb(dev, ide_base + reg_status), DF | ERR); 312 313 /* Write 0xaa pattern to sector 1 */ 314 memset(buf, 0xaa, len); 315 memwrite(guest_buf, buf, len); 316 317 status = send_dma_request(CMD_WRITE_DMA, 1, 1, prdt, 318 ARRAY_SIZE(prdt), NULL); 319 g_assert_cmphex(status, ==, BM_STS_INTR); 320 assert_bit_clear(qpci_io_readb(dev, ide_base + reg_status), DF | ERR); 321 322 /* Read and verify 0x55 pattern in sector 0 */ 323 memset(cmpbuf, 0x55, len); 324 325 status = send_dma_request(CMD_READ_DMA, 0, 1, prdt, ARRAY_SIZE(prdt), NULL); 326 g_assert_cmphex(status, ==, BM_STS_INTR); 327 assert_bit_clear(qpci_io_readb(dev, ide_base + reg_status), DF | ERR); 328 329 memread(guest_buf, buf, len); 330 g_assert(memcmp(buf, cmpbuf, len) == 0); 331 332 /* Read and verify 0xaa pattern in sector 1 */ 333 memset(cmpbuf, 0xaa, len); 334 335 status = send_dma_request(CMD_READ_DMA, 1, 1, prdt, ARRAY_SIZE(prdt), NULL); 336 g_assert_cmphex(status, ==, BM_STS_INTR); 337 assert_bit_clear(qpci_io_readb(dev, ide_base + reg_status), DF | ERR); 338 339 memread(guest_buf, buf, len); 340 g_assert(memcmp(buf, cmpbuf, len) == 0); 341 342 343 g_free(buf); 344 g_free(cmpbuf); 345 } 346 347 static void test_bmdma_short_prdt(void) 348 { 349 QPCIDevice *dev; 350 void *bmdma_base, *ide_base; 351 uint8_t status; 352 353 PrdtEntry prdt[] = { 354 { 355 .addr = 0, 356 .size = cpu_to_le32(0x10 | PRDT_EOT), 357 }, 358 }; 359 360 dev = get_pci_device(&bmdma_base, &ide_base); 361 362 /* Normal request */ 363 status = send_dma_request(CMD_READ_DMA, 0, 1, 364 prdt, ARRAY_SIZE(prdt), NULL); 365 g_assert_cmphex(status, ==, 0); 366 assert_bit_clear(qpci_io_readb(dev, ide_base + reg_status), DF | ERR); 367 368 /* Abort the request before it completes */ 369 status = send_dma_request(CMD_READ_DMA | CMDF_ABORT, 0, 1, 370 prdt, ARRAY_SIZE(prdt), NULL); 371 g_assert_cmphex(status, ==, 0); 372 assert_bit_clear(qpci_io_readb(dev, ide_base + reg_status), DF | ERR); 373 } 374 375 static void test_bmdma_one_sector_short_prdt(void) 376 { 377 QPCIDevice *dev; 378 void *bmdma_base, *ide_base; 379 uint8_t status; 380 381 /* Read 2 sectors but only give 1 sector in PRDT */ 382 PrdtEntry prdt[] = { 383 { 384 .addr = 0, 385 .size = cpu_to_le32(0x200 | PRDT_EOT), 386 }, 387 }; 388 389 dev = get_pci_device(&bmdma_base, &ide_base); 390 391 /* Normal request */ 392 status = send_dma_request(CMD_READ_DMA, 0, 2, 393 prdt, ARRAY_SIZE(prdt), NULL); 394 g_assert_cmphex(status, ==, 0); 395 assert_bit_clear(qpci_io_readb(dev, ide_base + reg_status), DF | ERR); 396 397 /* Abort the request before it completes */ 398 status = send_dma_request(CMD_READ_DMA | CMDF_ABORT, 0, 2, 399 prdt, ARRAY_SIZE(prdt), NULL); 400 g_assert_cmphex(status, ==, 0); 401 assert_bit_clear(qpci_io_readb(dev, ide_base + reg_status), DF | ERR); 402 } 403 404 static void test_bmdma_long_prdt(void) 405 { 406 QPCIDevice *dev; 407 void *bmdma_base, *ide_base; 408 uint8_t status; 409 410 PrdtEntry prdt[] = { 411 { 412 .addr = 0, 413 .size = cpu_to_le32(0x1000 | PRDT_EOT), 414 }, 415 }; 416 417 dev = get_pci_device(&bmdma_base, &ide_base); 418 419 /* Normal request */ 420 status = send_dma_request(CMD_READ_DMA, 0, 1, 421 prdt, ARRAY_SIZE(prdt), NULL); 422 g_assert_cmphex(status, ==, BM_STS_ACTIVE | BM_STS_INTR); 423 assert_bit_clear(qpci_io_readb(dev, ide_base + reg_status), DF | ERR); 424 425 /* Abort the request before it completes */ 426 status = send_dma_request(CMD_READ_DMA | CMDF_ABORT, 0, 1, 427 prdt, ARRAY_SIZE(prdt), NULL); 428 g_assert_cmphex(status, ==, BM_STS_INTR); 429 assert_bit_clear(qpci_io_readb(dev, ide_base + reg_status), DF | ERR); 430 } 431 432 static void test_bmdma_no_busmaster(void) 433 { 434 QPCIDevice *dev; 435 void *bmdma_base, *ide_base; 436 uint8_t status; 437 438 dev = get_pci_device(&bmdma_base, &ide_base); 439 440 /* No PRDT_EOT, each entry addr 0/size 64k, and in theory qemu shouldn't be 441 * able to access it anyway because the Bus Master bit in the PCI command 442 * register isn't set. This is complete nonsense, but it used to be pretty 443 * good at confusing and occasionally crashing qemu. */ 444 PrdtEntry prdt[4096] = { }; 445 446 status = send_dma_request(CMD_READ_DMA | CMDF_NO_BM, 0, 512, 447 prdt, ARRAY_SIZE(prdt), NULL); 448 449 /* Not entirely clear what the expected result is, but this is what we get 450 * in practice. At least we want to be aware of any changes. */ 451 g_assert_cmphex(status, ==, BM_STS_ACTIVE | BM_STS_INTR); 452 assert_bit_clear(qpci_io_readb(dev, ide_base + reg_status), DF | ERR); 453 } 454 455 static void test_bmdma_setup(void) 456 { 457 ide_test_start( 458 "-drive file=%s,if=ide,serial=%s,cache=writeback,format=raw " 459 "-global ide-hd.ver=%s", 460 tmp_path, "testdisk", "version"); 461 qtest_irq_intercept_in(global_qtest, "ioapic"); 462 } 463 464 static void test_bmdma_teardown(void) 465 { 466 ide_test_quit(); 467 } 468 469 static void string_cpu_to_be16(uint16_t *s, size_t bytes) 470 { 471 g_assert((bytes & 1) == 0); 472 bytes /= 2; 473 474 while (bytes--) { 475 *s = cpu_to_be16(*s); 476 s++; 477 } 478 } 479 480 static void test_identify(void) 481 { 482 QPCIDevice *dev; 483 void *bmdma_base, *ide_base; 484 uint8_t data; 485 uint16_t buf[256]; 486 int i; 487 int ret; 488 489 ide_test_start( 490 "-drive file=%s,if=ide,serial=%s,cache=writeback,format=raw " 491 "-global ide-hd.ver=%s", 492 tmp_path, "testdisk", "version"); 493 494 dev = get_pci_device(&bmdma_base, &ide_base); 495 496 /* IDENTIFY command on device 0*/ 497 qpci_io_writeb(dev, ide_base + reg_device, 0); 498 qpci_io_writeb(dev, ide_base + reg_command, CMD_IDENTIFY); 499 500 /* Read in the IDENTIFY buffer and check registers */ 501 data = qpci_io_readb(dev, ide_base + reg_device); 502 g_assert_cmpint(data & DEV, ==, 0); 503 504 for (i = 0; i < 256; i++) { 505 data = qpci_io_readb(dev, ide_base + reg_status); 506 assert_bit_set(data, DRDY | DRQ); 507 assert_bit_clear(data, BSY | DF | ERR); 508 509 buf[i] = qpci_io_readw(dev, ide_base + reg_data); 510 } 511 512 data = qpci_io_readb(dev, ide_base + reg_status); 513 assert_bit_set(data, DRDY); 514 assert_bit_clear(data, BSY | DF | ERR | DRQ); 515 516 /* Check serial number/version in the buffer */ 517 string_cpu_to_be16(&buf[10], 20); 518 ret = memcmp(&buf[10], "testdisk ", 20); 519 g_assert(ret == 0); 520 521 string_cpu_to_be16(&buf[23], 8); 522 ret = memcmp(&buf[23], "version ", 8); 523 g_assert(ret == 0); 524 525 /* Write cache enabled bit */ 526 assert_bit_set(buf[85], 0x20); 527 528 ide_test_quit(); 529 } 530 531 /* 532 * Write sector 1 with random data to make IDE storage dirty 533 * Needed for flush tests so that flushes actually go though the block layer 534 */ 535 static void make_dirty(uint8_t device) 536 { 537 QPCIDevice *dev; 538 void *bmdma_base, *ide_base; 539 uint8_t status; 540 size_t len = 512; 541 uintptr_t guest_buf; 542 void* buf; 543 544 dev = get_pci_device(&bmdma_base, &ide_base); 545 546 guest_buf = guest_alloc(guest_malloc, len); 547 buf = g_malloc(len); 548 g_assert(guest_buf); 549 g_assert(buf); 550 551 memwrite(guest_buf, buf, len); 552 553 PrdtEntry prdt[] = { 554 { 555 .addr = cpu_to_le32(guest_buf), 556 .size = cpu_to_le32(len | PRDT_EOT), 557 }, 558 }; 559 560 status = send_dma_request(CMD_WRITE_DMA, 1, 1, prdt, 561 ARRAY_SIZE(prdt), NULL); 562 g_assert_cmphex(status, ==, BM_STS_INTR); 563 assert_bit_clear(qpci_io_readb(dev, ide_base + reg_status), DF | ERR); 564 565 g_free(buf); 566 } 567 568 static void test_flush(void) 569 { 570 QPCIDevice *dev; 571 void *bmdma_base, *ide_base; 572 uint8_t data; 573 574 ide_test_start( 575 "-drive file=blkdebug::%s,if=ide,cache=writeback,format=raw", 576 tmp_path); 577 578 dev = get_pci_device(&bmdma_base, &ide_base); 579 580 qtest_irq_intercept_in(global_qtest, "ioapic"); 581 582 /* Dirty media so that CMD_FLUSH_CACHE will actually go to disk */ 583 make_dirty(0); 584 585 /* Delay the completion of the flush request until we explicitly do it */ 586 g_free(hmp("qemu-io ide0-hd0 \"break flush_to_os A\"")); 587 588 /* FLUSH CACHE command on device 0*/ 589 qpci_io_writeb(dev, ide_base + reg_device, 0); 590 qpci_io_writeb(dev, ide_base + reg_command, CMD_FLUSH_CACHE); 591 592 /* Check status while request is in flight*/ 593 data = qpci_io_readb(dev, ide_base + reg_status); 594 assert_bit_set(data, BSY | DRDY); 595 assert_bit_clear(data, DF | ERR | DRQ); 596 597 /* Complete the command */ 598 g_free(hmp("qemu-io ide0-hd0 \"resume A\"")); 599 600 /* Check registers */ 601 data = qpci_io_readb(dev, ide_base + reg_device); 602 g_assert_cmpint(data & DEV, ==, 0); 603 604 do { 605 data = qpci_io_readb(dev, ide_base + reg_status); 606 } while (data & BSY); 607 608 assert_bit_set(data, DRDY); 609 assert_bit_clear(data, BSY | DF | ERR | DRQ); 610 611 ide_test_quit(); 612 } 613 614 static void test_retry_flush(const char *machine) 615 { 616 QPCIDevice *dev; 617 void *bmdma_base, *ide_base; 618 uint8_t data; 619 const char *s; 620 621 prepare_blkdebug_script(debug_path, "flush_to_disk"); 622 623 ide_test_start( 624 "-vnc none " 625 "-drive file=blkdebug:%s:%s,if=ide,cache=writeback,format=raw," 626 "rerror=stop,werror=stop", 627 debug_path, tmp_path); 628 629 dev = get_pci_device(&bmdma_base, &ide_base); 630 631 qtest_irq_intercept_in(global_qtest, "ioapic"); 632 633 /* Dirty media so that CMD_FLUSH_CACHE will actually go to disk */ 634 make_dirty(0); 635 636 /* FLUSH CACHE command on device 0*/ 637 qpci_io_writeb(dev, ide_base + reg_device, 0); 638 qpci_io_writeb(dev, ide_base + reg_command, CMD_FLUSH_CACHE); 639 640 /* Check status while request is in flight*/ 641 data = qpci_io_readb(dev, ide_base + reg_status); 642 assert_bit_set(data, BSY | DRDY); 643 assert_bit_clear(data, DF | ERR | DRQ); 644 645 qmp_eventwait("STOP"); 646 647 /* Complete the command */ 648 s = "{'execute':'cont' }"; 649 qmp_discard_response(s); 650 651 /* Check registers */ 652 data = qpci_io_readb(dev, ide_base + reg_device); 653 g_assert_cmpint(data & DEV, ==, 0); 654 655 do { 656 data = qpci_io_readb(dev, ide_base + reg_status); 657 } while (data & BSY); 658 659 assert_bit_set(data, DRDY); 660 assert_bit_clear(data, BSY | DF | ERR | DRQ); 661 662 ide_test_quit(); 663 } 664 665 static void test_flush_nodev(void) 666 { 667 QPCIDevice *dev; 668 void *bmdma_base, *ide_base; 669 670 ide_test_start(""); 671 672 dev = get_pci_device(&bmdma_base, &ide_base); 673 674 /* FLUSH CACHE command on device 0*/ 675 qpci_io_writeb(dev, ide_base + reg_device, 0); 676 qpci_io_writeb(dev, ide_base + reg_command, CMD_FLUSH_CACHE); 677 678 /* Just testing that qemu doesn't crash... */ 679 680 ide_test_quit(); 681 } 682 683 static void test_pci_retry_flush(void) 684 { 685 test_retry_flush("pc"); 686 } 687 688 static void test_isa_retry_flush(void) 689 { 690 test_retry_flush("isapc"); 691 } 692 693 typedef struct Read10CDB { 694 uint8_t opcode; 695 uint8_t flags; 696 uint32_t lba; 697 uint8_t reserved; 698 uint16_t nblocks; 699 uint8_t control; 700 uint16_t padding; 701 } __attribute__((__packed__)) Read10CDB; 702 703 static void send_scsi_cdb_read10(QPCIDevice *dev, void *ide_base, 704 uint64_t lba, int nblocks) 705 { 706 Read10CDB pkt = { .padding = 0 }; 707 int i; 708 709 g_assert_cmpint(lba, <=, UINT32_MAX); 710 g_assert_cmpint(nblocks, <=, UINT16_MAX); 711 g_assert_cmpint(nblocks, >=, 0); 712 713 /* Construct SCSI CDB packet */ 714 pkt.opcode = 0x28; 715 pkt.lba = cpu_to_be32(lba); 716 pkt.nblocks = cpu_to_be16(nblocks); 717 718 /* Send Packet */ 719 for (i = 0; i < sizeof(Read10CDB)/2; i++) { 720 qpci_io_writew(dev, ide_base + reg_data, 721 le16_to_cpu(((uint16_t *)&pkt)[i])); 722 } 723 } 724 725 static void nsleep(int64_t nsecs) 726 { 727 const struct timespec val = { .tv_nsec = nsecs }; 728 nanosleep(&val, NULL); 729 clock_set(nsecs); 730 } 731 732 static uint8_t ide_wait_clear(uint8_t flag) 733 { 734 QPCIDevice *dev; 735 void *bmdma_base, *ide_base; 736 uint8_t data; 737 time_t st; 738 739 dev = get_pci_device(&bmdma_base, &ide_base); 740 741 /* Wait with a 5 second timeout */ 742 time(&st); 743 while (true) { 744 data = qpci_io_readb(dev, ide_base + reg_status); 745 if (!(data & flag)) { 746 return data; 747 } 748 if (difftime(time(NULL), st) > 5.0) { 749 break; 750 } 751 nsleep(400); 752 } 753 g_assert_not_reached(); 754 } 755 756 static void ide_wait_intr(int irq) 757 { 758 time_t st; 759 bool intr; 760 761 time(&st); 762 while (true) { 763 intr = get_irq(irq); 764 if (intr) { 765 return; 766 } 767 if (difftime(time(NULL), st) > 5.0) { 768 break; 769 } 770 nsleep(400); 771 } 772 773 g_assert_not_reached(); 774 } 775 776 static void cdrom_pio_impl(int nblocks) 777 { 778 QPCIDevice *dev; 779 void *bmdma_base, *ide_base; 780 FILE *fh; 781 int patt_blocks = MAX(16, nblocks); 782 size_t patt_len = ATAPI_BLOCK_SIZE * patt_blocks; 783 char *pattern = g_malloc(patt_len); 784 size_t rxsize = ATAPI_BLOCK_SIZE * nblocks; 785 uint16_t *rx = g_malloc0(rxsize); 786 int i, j; 787 uint8_t data; 788 uint16_t limit; 789 790 /* Prepopulate the CDROM with an interesting pattern */ 791 generate_pattern(pattern, patt_len, ATAPI_BLOCK_SIZE); 792 fh = fopen(tmp_path, "w+"); 793 fwrite(pattern, ATAPI_BLOCK_SIZE, patt_blocks, fh); 794 fclose(fh); 795 796 ide_test_start("-drive if=none,file=%s,media=cdrom,format=raw,id=sr0,index=0 " 797 "-device ide-cd,drive=sr0,bus=ide.0", tmp_path); 798 dev = get_pci_device(&bmdma_base, &ide_base); 799 qtest_irq_intercept_in(global_qtest, "ioapic"); 800 801 /* PACKET command on device 0 */ 802 qpci_io_writeb(dev, ide_base + reg_device, 0); 803 qpci_io_writeb(dev, ide_base + reg_lba_middle, BYTE_COUNT_LIMIT & 0xFF); 804 qpci_io_writeb(dev, ide_base + reg_lba_high, 805 (BYTE_COUNT_LIMIT >> 8 & 0xFF)); 806 qpci_io_writeb(dev, ide_base + reg_command, CMD_PACKET); 807 /* HP0: Check_Status_A State */ 808 nsleep(400); 809 data = ide_wait_clear(BSY); 810 /* HP1: Send_Packet State */ 811 assert_bit_set(data, DRQ | DRDY); 812 assert_bit_clear(data, ERR | DF | BSY); 813 814 /* SCSI CDB (READ10) -- read n*2048 bytes from block 0 */ 815 send_scsi_cdb_read10(dev, ide_base, 0, nblocks); 816 817 /* Read data back: occurs in bursts of 'BYTE_COUNT_LIMIT' bytes. 818 * If BYTE_COUNT_LIMIT is odd, we transfer BYTE_COUNT_LIMIT - 1 bytes. 819 * We allow an odd limit only when the remaining transfer size is 820 * less than BYTE_COUNT_LIMIT. However, SCSI's read10 command can only 821 * request n blocks, so our request size is always even. 822 * For this reason, we assume there is never a hanging byte to fetch. */ 823 g_assert(!(rxsize & 1)); 824 limit = BYTE_COUNT_LIMIT & ~1; 825 for (i = 0; i < DIV_ROUND_UP(rxsize, limit); i++) { 826 size_t offset = i * (limit / 2); 827 size_t rem = (rxsize / 2) - offset; 828 829 /* HP3: INTRQ_Wait */ 830 ide_wait_intr(IDE_PRIMARY_IRQ); 831 832 /* HP2: Check_Status_B (and clear IRQ) */ 833 data = ide_wait_clear(BSY); 834 assert_bit_set(data, DRQ | DRDY); 835 assert_bit_clear(data, ERR | DF | BSY); 836 837 /* HP4: Transfer_Data */ 838 for (j = 0; j < MIN((limit / 2), rem); j++) { 839 rx[offset + j] = cpu_to_le16(qpci_io_readw(dev, 840 ide_base + reg_data)); 841 } 842 } 843 844 /* Check for final completion IRQ */ 845 ide_wait_intr(IDE_PRIMARY_IRQ); 846 847 /* Sanity check final state */ 848 data = ide_wait_clear(DRQ); 849 assert_bit_set(data, DRDY); 850 assert_bit_clear(data, DRQ | ERR | DF | BSY); 851 852 g_assert_cmpint(memcmp(pattern, rx, rxsize), ==, 0); 853 g_free(pattern); 854 g_free(rx); 855 test_bmdma_teardown(); 856 } 857 858 static void test_cdrom_pio(void) 859 { 860 cdrom_pio_impl(1); 861 } 862 863 static void test_cdrom_pio_large(void) 864 { 865 /* Test a few loops of the PIO DRQ mechanism. */ 866 cdrom_pio_impl(BYTE_COUNT_LIMIT * 4 / ATAPI_BLOCK_SIZE); 867 } 868 869 870 static void test_cdrom_dma(void) 871 { 872 static const size_t len = ATAPI_BLOCK_SIZE; 873 char *pattern = g_malloc(ATAPI_BLOCK_SIZE * 16); 874 char *rx = g_malloc0(len); 875 uintptr_t guest_buf; 876 PrdtEntry prdt[1]; 877 FILE *fh; 878 879 ide_test_start("-drive if=none,file=%s,media=cdrom,format=raw,id=sr0,index=0 " 880 "-device ide-cd,drive=sr0,bus=ide.0", tmp_path); 881 qtest_irq_intercept_in(global_qtest, "ioapic"); 882 883 guest_buf = guest_alloc(guest_malloc, len); 884 prdt[0].addr = cpu_to_le32(guest_buf); 885 prdt[0].size = cpu_to_le32(len | PRDT_EOT); 886 887 generate_pattern(pattern, ATAPI_BLOCK_SIZE * 16, ATAPI_BLOCK_SIZE); 888 fh = fopen(tmp_path, "w+"); 889 fwrite(pattern, ATAPI_BLOCK_SIZE, 16, fh); 890 fclose(fh); 891 892 send_dma_request(CMD_PACKET, 0, 1, prdt, 1, send_scsi_cdb_read10); 893 894 /* Read back data from guest memory into local qtest memory */ 895 memread(guest_buf, rx, len); 896 g_assert_cmpint(memcmp(pattern, rx, len), ==, 0); 897 898 g_free(pattern); 899 g_free(rx); 900 test_bmdma_teardown(); 901 } 902 903 int main(int argc, char **argv) 904 { 905 const char *arch = qtest_get_arch(); 906 int fd; 907 int ret; 908 909 /* Check architecture */ 910 if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) { 911 g_test_message("Skipping test for non-x86\n"); 912 return 0; 913 } 914 915 /* Create temporary blkdebug instructions */ 916 fd = mkstemp(debug_path); 917 g_assert(fd >= 0); 918 close(fd); 919 920 /* Create a temporary raw image */ 921 fd = mkstemp(tmp_path); 922 g_assert(fd >= 0); 923 ret = ftruncate(fd, TEST_IMAGE_SIZE); 924 g_assert(ret == 0); 925 close(fd); 926 927 /* Run the tests */ 928 g_test_init(&argc, &argv, NULL); 929 930 qtest_add_func("/ide/identify", test_identify); 931 932 qtest_add_func("/ide/bmdma/setup", test_bmdma_setup); 933 qtest_add_func("/ide/bmdma/simple_rw", test_bmdma_simple_rw); 934 qtest_add_func("/ide/bmdma/short_prdt", test_bmdma_short_prdt); 935 qtest_add_func("/ide/bmdma/one_sector_short_prdt", 936 test_bmdma_one_sector_short_prdt); 937 qtest_add_func("/ide/bmdma/long_prdt", test_bmdma_long_prdt); 938 qtest_add_func("/ide/bmdma/no_busmaster", test_bmdma_no_busmaster); 939 qtest_add_func("/ide/bmdma/teardown", test_bmdma_teardown); 940 941 qtest_add_func("/ide/flush", test_flush); 942 qtest_add_func("/ide/flush/nodev", test_flush_nodev); 943 qtest_add_func("/ide/flush/retry_pci", test_pci_retry_flush); 944 qtest_add_func("/ide/flush/retry_isa", test_isa_retry_flush); 945 946 qtest_add_func("/ide/cdrom/pio", test_cdrom_pio); 947 qtest_add_func("/ide/cdrom/pio_large", test_cdrom_pio_large); 948 qtest_add_func("/ide/cdrom/dma", test_cdrom_dma); 949 950 ret = g_test_run(); 951 952 /* Cleanup */ 953 unlink(tmp_path); 954 unlink(debug_path); 955 956 return ret; 957 } 958