1 /* 2 * IDE test cases 3 * 4 * Copyright (c) 2013 Kevin Wolf <kwolf@redhat.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 27 28 #include "libqtest.h" 29 #include "libqos/libqos.h" 30 #include "libqos/pci-pc.h" 31 #include "libqos/malloc-pc.h" 32 #include "qapi/qmp/qdict.h" 33 #include "qemu-common.h" 34 #include "qemu/bswap.h" 35 #include "hw/pci/pci_ids.h" 36 #include "hw/pci/pci_regs.h" 37 38 /* TODO actually test the results and get rid of this */ 39 #define qmp_discard_response(...) qobject_unref(qmp(__VA_ARGS__)) 40 41 #define TEST_IMAGE_SIZE 64 * 1024 * 1024 42 43 #define IDE_PCI_DEV 1 44 #define IDE_PCI_FUNC 1 45 46 #define IDE_BASE 0x1f0 47 #define IDE_PRIMARY_IRQ 14 48 49 #define ATAPI_BLOCK_SIZE 2048 50 51 /* How many bytes to receive via ATAPI PIO at one time. 52 * Must be less than 0xFFFF. */ 53 #define BYTE_COUNT_LIMIT 5120 54 55 enum { 56 reg_data = 0x0, 57 reg_feature = 0x1, 58 reg_error = 0x1, 59 reg_nsectors = 0x2, 60 reg_lba_low = 0x3, 61 reg_lba_middle = 0x4, 62 reg_lba_high = 0x5, 63 reg_device = 0x6, 64 reg_status = 0x7, 65 reg_command = 0x7, 66 }; 67 68 enum { 69 BSY = 0x80, 70 DRDY = 0x40, 71 DF = 0x20, 72 DRQ = 0x08, 73 ERR = 0x01, 74 }; 75 76 /* Error field */ 77 enum { 78 ABRT = 0x04, 79 }; 80 81 enum { 82 DEV = 0x10, 83 LBA = 0x40, 84 }; 85 86 enum { 87 bmreg_cmd = 0x0, 88 bmreg_status = 0x2, 89 bmreg_prdt = 0x4, 90 }; 91 92 enum { 93 CMD_DSM = 0x06, 94 CMD_READ_DMA = 0xc8, 95 CMD_WRITE_DMA = 0xca, 96 CMD_FLUSH_CACHE = 0xe7, 97 CMD_IDENTIFY = 0xec, 98 CMD_PACKET = 0xa0, 99 100 CMDF_ABORT = 0x100, 101 CMDF_NO_BM = 0x200, 102 }; 103 104 enum { 105 BM_CMD_START = 0x1, 106 BM_CMD_WRITE = 0x8, /* write = from device to memory */ 107 }; 108 109 enum { 110 BM_STS_ACTIVE = 0x1, 111 BM_STS_ERROR = 0x2, 112 BM_STS_INTR = 0x4, 113 }; 114 115 enum { 116 PRDT_EOT = 0x80000000, 117 }; 118 119 #define assert_bit_set(data, mask) g_assert_cmphex((data) & (mask), ==, (mask)) 120 #define assert_bit_clear(data, mask) g_assert_cmphex((data) & (mask), ==, 0) 121 122 static QPCIBus *pcibus = NULL; 123 static QGuestAllocator *guest_malloc; 124 125 static char tmp_path[] = "/tmp/qtest.XXXXXX"; 126 static char debug_path[] = "/tmp/qtest-blkdebug.XXXXXX"; 127 128 static void ide_test_start(const char *cmdline_fmt, ...) 129 { 130 va_list ap; 131 char *cmdline; 132 133 va_start(ap, cmdline_fmt); 134 cmdline = g_strdup_vprintf(cmdline_fmt, ap); 135 va_end(ap); 136 137 qtest_start(cmdline); 138 guest_malloc = pc_alloc_init(global_qtest); 139 140 g_free(cmdline); 141 } 142 143 static void ide_test_quit(void) 144 { 145 if (pcibus) { 146 qpci_free_pc(pcibus); 147 pcibus = NULL; 148 } 149 pc_alloc_uninit(guest_malloc); 150 guest_malloc = NULL; 151 qtest_end(); 152 } 153 154 static QPCIDevice *get_pci_device(QPCIBar *bmdma_bar, QPCIBar *ide_bar) 155 { 156 QPCIDevice *dev; 157 uint16_t vendor_id, device_id; 158 159 if (!pcibus) { 160 pcibus = qpci_init_pc(global_qtest, NULL); 161 } 162 163 /* Find PCI device and verify it's the right one */ 164 dev = qpci_device_find(pcibus, QPCI_DEVFN(IDE_PCI_DEV, IDE_PCI_FUNC)); 165 g_assert(dev != NULL); 166 167 vendor_id = qpci_config_readw(dev, PCI_VENDOR_ID); 168 device_id = qpci_config_readw(dev, PCI_DEVICE_ID); 169 g_assert(vendor_id == PCI_VENDOR_ID_INTEL); 170 g_assert(device_id == PCI_DEVICE_ID_INTEL_82371SB_1); 171 172 /* Map bmdma BAR */ 173 *bmdma_bar = qpci_iomap(dev, 4, NULL); 174 175 *ide_bar = qpci_legacy_iomap(dev, IDE_BASE); 176 177 qpci_device_enable(dev); 178 179 return dev; 180 } 181 182 static void free_pci_device(QPCIDevice *dev) 183 { 184 /* libqos doesn't have a function for this, so free it manually */ 185 g_free(dev); 186 } 187 188 typedef struct PrdtEntry { 189 uint32_t addr; 190 uint32_t size; 191 } QEMU_PACKED PrdtEntry; 192 193 #define assert_bit_set(data, mask) g_assert_cmphex((data) & (mask), ==, (mask)) 194 #define assert_bit_clear(data, mask) g_assert_cmphex((data) & (mask), ==, 0) 195 196 static uint64_t trim_range_le(uint64_t sector, uint16_t count) 197 { 198 /* 2-byte range, 6-byte LBA */ 199 return cpu_to_le64(((uint64_t)count << 48) + sector); 200 } 201 202 static int send_dma_request(int cmd, uint64_t sector, int nb_sectors, 203 PrdtEntry *prdt, int prdt_entries, 204 void(*post_exec)(QPCIDevice *dev, QPCIBar ide_bar, 205 uint64_t sector, int nb_sectors)) 206 { 207 QPCIDevice *dev; 208 QPCIBar bmdma_bar, ide_bar; 209 uintptr_t guest_prdt; 210 size_t len; 211 bool from_dev; 212 uint8_t status; 213 int flags; 214 215 dev = get_pci_device(&bmdma_bar, &ide_bar); 216 217 flags = cmd & ~0xff; 218 cmd &= 0xff; 219 220 switch (cmd) { 221 case CMD_READ_DMA: 222 case CMD_PACKET: 223 /* Assuming we only test data reads w/ ATAPI, otherwise we need to know 224 * the SCSI command being sent in the packet, too. */ 225 from_dev = true; 226 break; 227 case CMD_DSM: 228 case CMD_WRITE_DMA: 229 from_dev = false; 230 break; 231 default: 232 g_assert_not_reached(); 233 } 234 235 if (flags & CMDF_NO_BM) { 236 qpci_config_writew(dev, PCI_COMMAND, 237 PCI_COMMAND_IO | PCI_COMMAND_MEMORY); 238 } 239 240 /* Select device 0 */ 241 qpci_io_writeb(dev, ide_bar, reg_device, 0 | LBA); 242 243 /* Stop any running transfer, clear any pending interrupt */ 244 qpci_io_writeb(dev, bmdma_bar, bmreg_cmd, 0); 245 qpci_io_writeb(dev, bmdma_bar, bmreg_status, BM_STS_INTR); 246 247 /* Setup PRDT */ 248 len = sizeof(*prdt) * prdt_entries; 249 guest_prdt = guest_alloc(guest_malloc, len); 250 memwrite(guest_prdt, prdt, len); 251 qpci_io_writel(dev, bmdma_bar, bmreg_prdt, guest_prdt); 252 253 /* ATA DMA command */ 254 if (cmd == CMD_PACKET) { 255 /* Enables ATAPI DMA; otherwise PIO is attempted */ 256 qpci_io_writeb(dev, ide_bar, reg_feature, 0x01); 257 } else { 258 if (cmd == CMD_DSM) { 259 /* trim bit */ 260 qpci_io_writeb(dev, ide_bar, reg_feature, 0x01); 261 } 262 qpci_io_writeb(dev, ide_bar, reg_nsectors, nb_sectors); 263 qpci_io_writeb(dev, ide_bar, reg_lba_low, sector & 0xff); 264 qpci_io_writeb(dev, ide_bar, reg_lba_middle, (sector >> 8) & 0xff); 265 qpci_io_writeb(dev, ide_bar, reg_lba_high, (sector >> 16) & 0xff); 266 } 267 268 qpci_io_writeb(dev, ide_bar, reg_command, cmd); 269 270 if (post_exec) { 271 post_exec(dev, ide_bar, sector, nb_sectors); 272 } 273 274 /* Start DMA transfer */ 275 qpci_io_writeb(dev, bmdma_bar, bmreg_cmd, 276 BM_CMD_START | (from_dev ? BM_CMD_WRITE : 0)); 277 278 if (flags & CMDF_ABORT) { 279 qpci_io_writeb(dev, bmdma_bar, bmreg_cmd, 0); 280 } 281 282 /* Wait for the DMA transfer to complete */ 283 do { 284 status = qpci_io_readb(dev, bmdma_bar, bmreg_status); 285 } while ((status & (BM_STS_ACTIVE | BM_STS_INTR)) == BM_STS_ACTIVE); 286 287 g_assert_cmpint(get_irq(IDE_PRIMARY_IRQ), ==, !!(status & BM_STS_INTR)); 288 289 /* Check IDE status code */ 290 assert_bit_set(qpci_io_readb(dev, ide_bar, reg_status), DRDY); 291 assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), BSY | DRQ); 292 293 /* Reading the status register clears the IRQ */ 294 g_assert(!get_irq(IDE_PRIMARY_IRQ)); 295 296 /* Stop DMA transfer if still active */ 297 if (status & BM_STS_ACTIVE) { 298 qpci_io_writeb(dev, bmdma_bar, bmreg_cmd, 0); 299 } 300 301 free_pci_device(dev); 302 303 return status; 304 } 305 306 static void test_bmdma_simple_rw(void) 307 { 308 QPCIDevice *dev; 309 QPCIBar bmdma_bar, ide_bar; 310 uint8_t status; 311 uint8_t *buf; 312 uint8_t *cmpbuf; 313 size_t len = 512; 314 uintptr_t guest_buf = guest_alloc(guest_malloc, len); 315 316 PrdtEntry prdt[] = { 317 { 318 .addr = cpu_to_le32(guest_buf), 319 .size = cpu_to_le32(len | PRDT_EOT), 320 }, 321 }; 322 323 dev = get_pci_device(&bmdma_bar, &ide_bar); 324 325 buf = g_malloc(len); 326 cmpbuf = g_malloc(len); 327 328 /* Write 0x55 pattern to sector 0 */ 329 memset(buf, 0x55, len); 330 memwrite(guest_buf, buf, len); 331 332 status = send_dma_request(CMD_WRITE_DMA, 0, 1, prdt, 333 ARRAY_SIZE(prdt), NULL); 334 g_assert_cmphex(status, ==, BM_STS_INTR); 335 assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); 336 337 /* Write 0xaa pattern to sector 1 */ 338 memset(buf, 0xaa, len); 339 memwrite(guest_buf, buf, len); 340 341 status = send_dma_request(CMD_WRITE_DMA, 1, 1, prdt, 342 ARRAY_SIZE(prdt), NULL); 343 g_assert_cmphex(status, ==, BM_STS_INTR); 344 assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); 345 346 /* Read and verify 0x55 pattern in sector 0 */ 347 memset(cmpbuf, 0x55, len); 348 349 status = send_dma_request(CMD_READ_DMA, 0, 1, prdt, ARRAY_SIZE(prdt), NULL); 350 g_assert_cmphex(status, ==, BM_STS_INTR); 351 assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); 352 353 memread(guest_buf, buf, len); 354 g_assert(memcmp(buf, cmpbuf, len) == 0); 355 356 /* Read and verify 0xaa pattern in sector 1 */ 357 memset(cmpbuf, 0xaa, len); 358 359 status = send_dma_request(CMD_READ_DMA, 1, 1, prdt, ARRAY_SIZE(prdt), NULL); 360 g_assert_cmphex(status, ==, BM_STS_INTR); 361 assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); 362 363 memread(guest_buf, buf, len); 364 g_assert(memcmp(buf, cmpbuf, len) == 0); 365 366 367 free_pci_device(dev); 368 g_free(buf); 369 g_free(cmpbuf); 370 } 371 372 static void test_bmdma_trim(void) 373 { 374 QPCIDevice *dev; 375 QPCIBar bmdma_bar, ide_bar; 376 uint8_t status; 377 const uint64_t trim_range[] = { trim_range_le(0, 2), 378 trim_range_le(6, 8), 379 trim_range_le(10, 1), 380 }; 381 const uint64_t bad_range = trim_range_le(TEST_IMAGE_SIZE / 512 - 1, 2); 382 size_t len = 512; 383 uint8_t *buf; 384 uintptr_t guest_buf = guest_alloc(guest_malloc, len); 385 386 PrdtEntry prdt[] = { 387 { 388 .addr = cpu_to_le32(guest_buf), 389 .size = cpu_to_le32(len | PRDT_EOT), 390 }, 391 }; 392 393 dev = get_pci_device(&bmdma_bar, &ide_bar); 394 395 buf = g_malloc(len); 396 397 /* Normal request */ 398 *((uint64_t *)buf) = trim_range[0]; 399 *((uint64_t *)buf + 1) = trim_range[1]; 400 401 memwrite(guest_buf, buf, 2 * sizeof(uint64_t)); 402 403 status = send_dma_request(CMD_DSM, 0, 1, prdt, 404 ARRAY_SIZE(prdt), NULL); 405 g_assert_cmphex(status, ==, BM_STS_INTR); 406 assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); 407 408 /* Request contains invalid range */ 409 *((uint64_t *)buf) = trim_range[2]; 410 *((uint64_t *)buf + 1) = bad_range; 411 412 memwrite(guest_buf, buf, 2 * sizeof(uint64_t)); 413 414 status = send_dma_request(CMD_DSM, 0, 1, prdt, 415 ARRAY_SIZE(prdt), NULL); 416 g_assert_cmphex(status, ==, BM_STS_INTR); 417 assert_bit_set(qpci_io_readb(dev, ide_bar, reg_status), ERR); 418 assert_bit_set(qpci_io_readb(dev, ide_bar, reg_error), ABRT); 419 420 free_pci_device(dev); 421 g_free(buf); 422 } 423 424 static void test_bmdma_short_prdt(void) 425 { 426 QPCIDevice *dev; 427 QPCIBar bmdma_bar, ide_bar; 428 uint8_t status; 429 430 PrdtEntry prdt[] = { 431 { 432 .addr = 0, 433 .size = cpu_to_le32(0x10 | PRDT_EOT), 434 }, 435 }; 436 437 dev = get_pci_device(&bmdma_bar, &ide_bar); 438 439 /* Normal request */ 440 status = send_dma_request(CMD_READ_DMA, 0, 1, 441 prdt, ARRAY_SIZE(prdt), NULL); 442 g_assert_cmphex(status, ==, 0); 443 assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); 444 445 /* Abort the request before it completes */ 446 status = send_dma_request(CMD_READ_DMA | CMDF_ABORT, 0, 1, 447 prdt, ARRAY_SIZE(prdt), NULL); 448 g_assert_cmphex(status, ==, 0); 449 assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); 450 free_pci_device(dev); 451 } 452 453 static void test_bmdma_one_sector_short_prdt(void) 454 { 455 QPCIDevice *dev; 456 QPCIBar bmdma_bar, ide_bar; 457 uint8_t status; 458 459 /* Read 2 sectors but only give 1 sector in PRDT */ 460 PrdtEntry prdt[] = { 461 { 462 .addr = 0, 463 .size = cpu_to_le32(0x200 | PRDT_EOT), 464 }, 465 }; 466 467 dev = get_pci_device(&bmdma_bar, &ide_bar); 468 469 /* Normal request */ 470 status = send_dma_request(CMD_READ_DMA, 0, 2, 471 prdt, ARRAY_SIZE(prdt), NULL); 472 g_assert_cmphex(status, ==, 0); 473 assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); 474 475 /* Abort the request before it completes */ 476 status = send_dma_request(CMD_READ_DMA | CMDF_ABORT, 0, 2, 477 prdt, ARRAY_SIZE(prdt), NULL); 478 g_assert_cmphex(status, ==, 0); 479 assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); 480 free_pci_device(dev); 481 } 482 483 static void test_bmdma_long_prdt(void) 484 { 485 QPCIDevice *dev; 486 QPCIBar bmdma_bar, ide_bar; 487 uint8_t status; 488 489 PrdtEntry prdt[] = { 490 { 491 .addr = 0, 492 .size = cpu_to_le32(0x1000 | PRDT_EOT), 493 }, 494 }; 495 496 dev = get_pci_device(&bmdma_bar, &ide_bar); 497 498 /* Normal request */ 499 status = send_dma_request(CMD_READ_DMA, 0, 1, 500 prdt, ARRAY_SIZE(prdt), NULL); 501 g_assert_cmphex(status, ==, BM_STS_ACTIVE | BM_STS_INTR); 502 assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); 503 504 /* Abort the request before it completes */ 505 status = send_dma_request(CMD_READ_DMA | CMDF_ABORT, 0, 1, 506 prdt, ARRAY_SIZE(prdt), NULL); 507 g_assert_cmphex(status, ==, BM_STS_INTR); 508 assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); 509 free_pci_device(dev); 510 } 511 512 static void test_bmdma_no_busmaster(void) 513 { 514 QPCIDevice *dev; 515 QPCIBar bmdma_bar, ide_bar; 516 uint8_t status; 517 518 dev = get_pci_device(&bmdma_bar, &ide_bar); 519 520 /* No PRDT_EOT, each entry addr 0/size 64k, and in theory qemu shouldn't be 521 * able to access it anyway because the Bus Master bit in the PCI command 522 * register isn't set. This is complete nonsense, but it used to be pretty 523 * good at confusing and occasionally crashing qemu. */ 524 PrdtEntry prdt[4096] = { }; 525 526 status = send_dma_request(CMD_READ_DMA | CMDF_NO_BM, 0, 512, 527 prdt, ARRAY_SIZE(prdt), NULL); 528 529 /* Not entirely clear what the expected result is, but this is what we get 530 * in practice. At least we want to be aware of any changes. */ 531 g_assert_cmphex(status, ==, BM_STS_ACTIVE | BM_STS_INTR); 532 assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); 533 free_pci_device(dev); 534 } 535 536 static void test_bmdma_setup(void) 537 { 538 ide_test_start( 539 "-drive file=%s,if=ide,cache=writeback,format=raw " 540 "-global ide-hd.serial=%s -global ide-hd.ver=%s", 541 tmp_path, "testdisk", "version"); 542 qtest_irq_intercept_in(global_qtest, "ioapic"); 543 } 544 545 static void test_bmdma_teardown(void) 546 { 547 ide_test_quit(); 548 } 549 550 static void string_cpu_to_be16(uint16_t *s, size_t bytes) 551 { 552 g_assert((bytes & 1) == 0); 553 bytes /= 2; 554 555 while (bytes--) { 556 *s = cpu_to_be16(*s); 557 s++; 558 } 559 } 560 561 static void test_identify(void) 562 { 563 QPCIDevice *dev; 564 QPCIBar bmdma_bar, ide_bar; 565 uint8_t data; 566 uint16_t buf[256]; 567 int i; 568 int ret; 569 570 ide_test_start( 571 "-drive file=%s,if=ide,cache=writeback,format=raw " 572 "-global ide-hd.serial=%s -global ide-hd.ver=%s", 573 tmp_path, "testdisk", "version"); 574 575 dev = get_pci_device(&bmdma_bar, &ide_bar); 576 577 /* IDENTIFY command on device 0*/ 578 qpci_io_writeb(dev, ide_bar, reg_device, 0); 579 qpci_io_writeb(dev, ide_bar, reg_command, CMD_IDENTIFY); 580 581 /* Read in the IDENTIFY buffer and check registers */ 582 data = qpci_io_readb(dev, ide_bar, reg_device); 583 g_assert_cmpint(data & DEV, ==, 0); 584 585 for (i = 0; i < 256; i++) { 586 data = qpci_io_readb(dev, ide_bar, reg_status); 587 assert_bit_set(data, DRDY | DRQ); 588 assert_bit_clear(data, BSY | DF | ERR); 589 590 buf[i] = qpci_io_readw(dev, ide_bar, reg_data); 591 } 592 593 data = qpci_io_readb(dev, ide_bar, reg_status); 594 assert_bit_set(data, DRDY); 595 assert_bit_clear(data, BSY | DF | ERR | DRQ); 596 597 /* Check serial number/version in the buffer */ 598 string_cpu_to_be16(&buf[10], 20); 599 ret = memcmp(&buf[10], "testdisk ", 20); 600 g_assert(ret == 0); 601 602 string_cpu_to_be16(&buf[23], 8); 603 ret = memcmp(&buf[23], "version ", 8); 604 g_assert(ret == 0); 605 606 /* Write cache enabled bit */ 607 assert_bit_set(buf[85], 0x20); 608 609 ide_test_quit(); 610 free_pci_device(dev); 611 } 612 613 /* 614 * Write sector 1 with random data to make IDE storage dirty 615 * Needed for flush tests so that flushes actually go though the block layer 616 */ 617 static void make_dirty(uint8_t device) 618 { 619 QPCIDevice *dev; 620 QPCIBar bmdma_bar, ide_bar; 621 uint8_t status; 622 size_t len = 512; 623 uintptr_t guest_buf; 624 void* buf; 625 626 dev = get_pci_device(&bmdma_bar, &ide_bar); 627 628 guest_buf = guest_alloc(guest_malloc, len); 629 buf = g_malloc(len); 630 memset(buf, rand() % 255 + 1, len); 631 g_assert(guest_buf); 632 g_assert(buf); 633 634 memwrite(guest_buf, buf, len); 635 636 PrdtEntry prdt[] = { 637 { 638 .addr = cpu_to_le32(guest_buf), 639 .size = cpu_to_le32(len | PRDT_EOT), 640 }, 641 }; 642 643 status = send_dma_request(CMD_WRITE_DMA, 1, 1, prdt, 644 ARRAY_SIZE(prdt), NULL); 645 g_assert_cmphex(status, ==, BM_STS_INTR); 646 assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); 647 648 g_free(buf); 649 free_pci_device(dev); 650 } 651 652 static void test_flush(void) 653 { 654 QPCIDevice *dev; 655 QPCIBar bmdma_bar, ide_bar; 656 uint8_t data; 657 658 ide_test_start( 659 "-drive file=blkdebug::%s,if=ide,cache=writeback,format=raw", 660 tmp_path); 661 662 dev = get_pci_device(&bmdma_bar, &ide_bar); 663 664 qtest_irq_intercept_in(global_qtest, "ioapic"); 665 666 /* Dirty media so that CMD_FLUSH_CACHE will actually go to disk */ 667 make_dirty(0); 668 669 /* Delay the completion of the flush request until we explicitly do it */ 670 g_free(hmp("qemu-io ide0-hd0 \"break flush_to_os A\"")); 671 672 /* FLUSH CACHE command on device 0*/ 673 qpci_io_writeb(dev, ide_bar, reg_device, 0); 674 qpci_io_writeb(dev, ide_bar, reg_command, CMD_FLUSH_CACHE); 675 676 /* Check status while request is in flight*/ 677 data = qpci_io_readb(dev, ide_bar, reg_status); 678 assert_bit_set(data, BSY | DRDY); 679 assert_bit_clear(data, DF | ERR | DRQ); 680 681 /* Complete the command */ 682 g_free(hmp("qemu-io ide0-hd0 \"resume A\"")); 683 684 /* Check registers */ 685 data = qpci_io_readb(dev, ide_bar, reg_device); 686 g_assert_cmpint(data & DEV, ==, 0); 687 688 do { 689 data = qpci_io_readb(dev, ide_bar, reg_status); 690 } while (data & BSY); 691 692 assert_bit_set(data, DRDY); 693 assert_bit_clear(data, BSY | DF | ERR | DRQ); 694 695 ide_test_quit(); 696 free_pci_device(dev); 697 } 698 699 static void test_retry_flush(const char *machine) 700 { 701 QPCIDevice *dev; 702 QPCIBar bmdma_bar, ide_bar; 703 uint8_t data; 704 705 prepare_blkdebug_script(debug_path, "flush_to_disk"); 706 707 ide_test_start( 708 "-drive file=blkdebug:%s:%s,if=ide,cache=writeback,format=raw," 709 "rerror=stop,werror=stop", 710 debug_path, tmp_path); 711 712 dev = get_pci_device(&bmdma_bar, &ide_bar); 713 714 qtest_irq_intercept_in(global_qtest, "ioapic"); 715 716 /* Dirty media so that CMD_FLUSH_CACHE will actually go to disk */ 717 make_dirty(0); 718 719 /* FLUSH CACHE command on device 0*/ 720 qpci_io_writeb(dev, ide_bar, reg_device, 0); 721 qpci_io_writeb(dev, ide_bar, reg_command, CMD_FLUSH_CACHE); 722 723 /* Check status while request is in flight*/ 724 data = qpci_io_readb(dev, ide_bar, reg_status); 725 assert_bit_set(data, BSY | DRDY); 726 assert_bit_clear(data, DF | ERR | DRQ); 727 728 qmp_eventwait("STOP"); 729 730 /* Complete the command */ 731 qmp_discard_response("{'execute':'cont' }"); 732 733 /* Check registers */ 734 data = qpci_io_readb(dev, ide_bar, reg_device); 735 g_assert_cmpint(data & DEV, ==, 0); 736 737 do { 738 data = qpci_io_readb(dev, ide_bar, reg_status); 739 } while (data & BSY); 740 741 assert_bit_set(data, DRDY); 742 assert_bit_clear(data, BSY | DF | ERR | DRQ); 743 744 ide_test_quit(); 745 free_pci_device(dev); 746 } 747 748 static void test_flush_nodev(void) 749 { 750 QPCIDevice *dev; 751 QPCIBar bmdma_bar, ide_bar; 752 753 ide_test_start(""); 754 755 dev = get_pci_device(&bmdma_bar, &ide_bar); 756 757 /* FLUSH CACHE command on device 0*/ 758 qpci_io_writeb(dev, ide_bar, reg_device, 0); 759 qpci_io_writeb(dev, ide_bar, reg_command, CMD_FLUSH_CACHE); 760 761 /* Just testing that qemu doesn't crash... */ 762 763 free_pci_device(dev); 764 ide_test_quit(); 765 } 766 767 static void test_flush_empty_drive(void) 768 { 769 QPCIDevice *dev; 770 QPCIBar bmdma_bar, ide_bar; 771 772 ide_test_start("-device ide-cd,bus=ide.0"); 773 dev = get_pci_device(&bmdma_bar, &ide_bar); 774 775 /* FLUSH CACHE command on device 0 */ 776 qpci_io_writeb(dev, ide_bar, reg_device, 0); 777 qpci_io_writeb(dev, ide_bar, reg_command, CMD_FLUSH_CACHE); 778 779 /* Just testing that qemu doesn't crash... */ 780 781 free_pci_device(dev); 782 ide_test_quit(); 783 } 784 785 static void test_pci_retry_flush(void) 786 { 787 test_retry_flush("pc"); 788 } 789 790 static void test_isa_retry_flush(void) 791 { 792 test_retry_flush("isapc"); 793 } 794 795 typedef struct Read10CDB { 796 uint8_t opcode; 797 uint8_t flags; 798 uint32_t lba; 799 uint8_t reserved; 800 uint16_t nblocks; 801 uint8_t control; 802 uint16_t padding; 803 } __attribute__((__packed__)) Read10CDB; 804 805 static void send_scsi_cdb_read10(QPCIDevice *dev, QPCIBar ide_bar, 806 uint64_t lba, int nblocks) 807 { 808 Read10CDB pkt = { .padding = 0 }; 809 int i; 810 811 g_assert_cmpint(lba, <=, UINT32_MAX); 812 g_assert_cmpint(nblocks, <=, UINT16_MAX); 813 g_assert_cmpint(nblocks, >=, 0); 814 815 /* Construct SCSI CDB packet */ 816 pkt.opcode = 0x28; 817 pkt.lba = cpu_to_be32(lba); 818 pkt.nblocks = cpu_to_be16(nblocks); 819 820 /* Send Packet */ 821 for (i = 0; i < sizeof(Read10CDB)/2; i++) { 822 qpci_io_writew(dev, ide_bar, reg_data, 823 le16_to_cpu(((uint16_t *)&pkt)[i])); 824 } 825 } 826 827 static void nsleep(int64_t nsecs) 828 { 829 const struct timespec val = { .tv_nsec = nsecs }; 830 nanosleep(&val, NULL); 831 clock_set(nsecs); 832 } 833 834 static uint8_t ide_wait_clear(uint8_t flag) 835 { 836 QPCIDevice *dev; 837 QPCIBar bmdma_bar, ide_bar; 838 uint8_t data; 839 time_t st; 840 841 dev = get_pci_device(&bmdma_bar, &ide_bar); 842 843 /* Wait with a 5 second timeout */ 844 time(&st); 845 while (true) { 846 data = qpci_io_readb(dev, ide_bar, reg_status); 847 if (!(data & flag)) { 848 free_pci_device(dev); 849 return data; 850 } 851 if (difftime(time(NULL), st) > 5.0) { 852 break; 853 } 854 nsleep(400); 855 } 856 g_assert_not_reached(); 857 } 858 859 static void ide_wait_intr(int irq) 860 { 861 time_t st; 862 bool intr; 863 864 time(&st); 865 while (true) { 866 intr = get_irq(irq); 867 if (intr) { 868 return; 869 } 870 if (difftime(time(NULL), st) > 5.0) { 871 break; 872 } 873 nsleep(400); 874 } 875 876 g_assert_not_reached(); 877 } 878 879 static void cdrom_pio_impl(int nblocks) 880 { 881 QPCIDevice *dev; 882 QPCIBar bmdma_bar, ide_bar; 883 FILE *fh; 884 int patt_blocks = MAX(16, nblocks); 885 size_t patt_len = ATAPI_BLOCK_SIZE * patt_blocks; 886 char *pattern = g_malloc(patt_len); 887 size_t rxsize = ATAPI_BLOCK_SIZE * nblocks; 888 uint16_t *rx = g_malloc0(rxsize); 889 int i, j; 890 uint8_t data; 891 uint16_t limit; 892 size_t ret; 893 894 /* Prepopulate the CDROM with an interesting pattern */ 895 generate_pattern(pattern, patt_len, ATAPI_BLOCK_SIZE); 896 fh = fopen(tmp_path, "w+"); 897 ret = fwrite(pattern, ATAPI_BLOCK_SIZE, patt_blocks, fh); 898 g_assert_cmpint(ret, ==, patt_blocks); 899 fclose(fh); 900 901 ide_test_start("-drive if=none,file=%s,media=cdrom,format=raw,id=sr0,index=0 " 902 "-device ide-cd,drive=sr0,bus=ide.0", tmp_path); 903 dev = get_pci_device(&bmdma_bar, &ide_bar); 904 qtest_irq_intercept_in(global_qtest, "ioapic"); 905 906 /* PACKET command on device 0 */ 907 qpci_io_writeb(dev, ide_bar, reg_device, 0); 908 qpci_io_writeb(dev, ide_bar, reg_lba_middle, BYTE_COUNT_LIMIT & 0xFF); 909 qpci_io_writeb(dev, ide_bar, reg_lba_high, (BYTE_COUNT_LIMIT >> 8 & 0xFF)); 910 qpci_io_writeb(dev, ide_bar, reg_command, CMD_PACKET); 911 /* HP0: Check_Status_A State */ 912 nsleep(400); 913 data = ide_wait_clear(BSY); 914 /* HP1: Send_Packet State */ 915 assert_bit_set(data, DRQ | DRDY); 916 assert_bit_clear(data, ERR | DF | BSY); 917 918 /* SCSI CDB (READ10) -- read n*2048 bytes from block 0 */ 919 send_scsi_cdb_read10(dev, ide_bar, 0, nblocks); 920 921 /* Read data back: occurs in bursts of 'BYTE_COUNT_LIMIT' bytes. 922 * If BYTE_COUNT_LIMIT is odd, we transfer BYTE_COUNT_LIMIT - 1 bytes. 923 * We allow an odd limit only when the remaining transfer size is 924 * less than BYTE_COUNT_LIMIT. However, SCSI's read10 command can only 925 * request n blocks, so our request size is always even. 926 * For this reason, we assume there is never a hanging byte to fetch. */ 927 g_assert(!(rxsize & 1)); 928 limit = BYTE_COUNT_LIMIT & ~1; 929 for (i = 0; i < DIV_ROUND_UP(rxsize, limit); i++) { 930 size_t offset = i * (limit / 2); 931 size_t rem = (rxsize / 2) - offset; 932 933 /* HP3: INTRQ_Wait */ 934 ide_wait_intr(IDE_PRIMARY_IRQ); 935 936 /* HP2: Check_Status_B (and clear IRQ) */ 937 data = ide_wait_clear(BSY); 938 assert_bit_set(data, DRQ | DRDY); 939 assert_bit_clear(data, ERR | DF | BSY); 940 941 /* HP4: Transfer_Data */ 942 for (j = 0; j < MIN((limit / 2), rem); j++) { 943 rx[offset + j] = cpu_to_le16(qpci_io_readw(dev, ide_bar, 944 reg_data)); 945 } 946 } 947 948 /* Check for final completion IRQ */ 949 ide_wait_intr(IDE_PRIMARY_IRQ); 950 951 /* Sanity check final state */ 952 data = ide_wait_clear(DRQ); 953 assert_bit_set(data, DRDY); 954 assert_bit_clear(data, DRQ | ERR | DF | BSY); 955 956 g_assert_cmpint(memcmp(pattern, rx, rxsize), ==, 0); 957 g_free(pattern); 958 g_free(rx); 959 test_bmdma_teardown(); 960 free_pci_device(dev); 961 } 962 963 static void test_cdrom_pio(void) 964 { 965 cdrom_pio_impl(1); 966 } 967 968 static void test_cdrom_pio_large(void) 969 { 970 /* Test a few loops of the PIO DRQ mechanism. */ 971 cdrom_pio_impl(BYTE_COUNT_LIMIT * 4 / ATAPI_BLOCK_SIZE); 972 } 973 974 975 static void test_cdrom_dma(void) 976 { 977 static const size_t len = ATAPI_BLOCK_SIZE; 978 size_t ret; 979 char *pattern = g_malloc(ATAPI_BLOCK_SIZE * 16); 980 char *rx = g_malloc0(len); 981 uintptr_t guest_buf; 982 PrdtEntry prdt[1]; 983 FILE *fh; 984 985 ide_test_start("-drive if=none,file=%s,media=cdrom,format=raw,id=sr0,index=0 " 986 "-device ide-cd,drive=sr0,bus=ide.0", tmp_path); 987 qtest_irq_intercept_in(global_qtest, "ioapic"); 988 989 guest_buf = guest_alloc(guest_malloc, len); 990 prdt[0].addr = cpu_to_le32(guest_buf); 991 prdt[0].size = cpu_to_le32(len | PRDT_EOT); 992 993 generate_pattern(pattern, ATAPI_BLOCK_SIZE * 16, ATAPI_BLOCK_SIZE); 994 fh = fopen(tmp_path, "w+"); 995 ret = fwrite(pattern, ATAPI_BLOCK_SIZE, 16, fh); 996 g_assert_cmpint(ret, ==, 16); 997 fclose(fh); 998 999 send_dma_request(CMD_PACKET, 0, 1, prdt, 1, send_scsi_cdb_read10); 1000 1001 /* Read back data from guest memory into local qtest memory */ 1002 memread(guest_buf, rx, len); 1003 g_assert_cmpint(memcmp(pattern, rx, len), ==, 0); 1004 1005 g_free(pattern); 1006 g_free(rx); 1007 test_bmdma_teardown(); 1008 } 1009 1010 int main(int argc, char **argv) 1011 { 1012 int fd; 1013 int ret; 1014 1015 /* Create temporary blkdebug instructions */ 1016 fd = mkstemp(debug_path); 1017 g_assert(fd >= 0); 1018 close(fd); 1019 1020 /* Create a temporary raw image */ 1021 fd = mkstemp(tmp_path); 1022 g_assert(fd >= 0); 1023 ret = ftruncate(fd, TEST_IMAGE_SIZE); 1024 g_assert(ret == 0); 1025 close(fd); 1026 1027 /* Run the tests */ 1028 g_test_init(&argc, &argv, NULL); 1029 1030 qtest_add_func("/ide/identify", test_identify); 1031 1032 qtest_add_func("/ide/bmdma/setup", test_bmdma_setup); 1033 qtest_add_func("/ide/bmdma/simple_rw", test_bmdma_simple_rw); 1034 qtest_add_func("/ide/bmdma/trim", test_bmdma_trim); 1035 qtest_add_func("/ide/bmdma/short_prdt", test_bmdma_short_prdt); 1036 qtest_add_func("/ide/bmdma/one_sector_short_prdt", 1037 test_bmdma_one_sector_short_prdt); 1038 qtest_add_func("/ide/bmdma/long_prdt", test_bmdma_long_prdt); 1039 qtest_add_func("/ide/bmdma/no_busmaster", test_bmdma_no_busmaster); 1040 qtest_add_func("/ide/bmdma/teardown", test_bmdma_teardown); 1041 1042 qtest_add_func("/ide/flush", test_flush); 1043 qtest_add_func("/ide/flush/nodev", test_flush_nodev); 1044 qtest_add_func("/ide/flush/empty_drive", test_flush_empty_drive); 1045 qtest_add_func("/ide/flush/retry_pci", test_pci_retry_flush); 1046 qtest_add_func("/ide/flush/retry_isa", test_isa_retry_flush); 1047 1048 qtest_add_func("/ide/cdrom/pio", test_cdrom_pio); 1049 qtest_add_func("/ide/cdrom/pio_large", test_cdrom_pio_large); 1050 qtest_add_func("/ide/cdrom/dma", test_cdrom_dma); 1051 1052 ret = g_test_run(); 1053 1054 /* Cleanup */ 1055 unlink(tmp_path); 1056 unlink(debug_path); 1057 1058 return ret; 1059 } 1060