1 /* 2 * IDE test cases 3 * 4 * Copyright (c) 2013 Kevin Wolf <kwolf@redhat.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include <stdint.h> 26 #include <string.h> 27 #include <stdio.h> 28 29 #include <glib.h> 30 31 #include "libqtest.h" 32 #include "libqos/pci-pc.h" 33 #include "libqos/malloc-pc.h" 34 35 #include "qemu-common.h" 36 #include "hw/pci/pci_ids.h" 37 #include "hw/pci/pci_regs.h" 38 39 #define TEST_IMAGE_SIZE 64 * 1024 * 1024 40 41 #define IDE_PCI_DEV 1 42 #define IDE_PCI_FUNC 1 43 44 #define IDE_BASE 0x1f0 45 #define IDE_PRIMARY_IRQ 14 46 47 enum { 48 reg_data = 0x0, 49 reg_nsectors = 0x2, 50 reg_lba_low = 0x3, 51 reg_lba_middle = 0x4, 52 reg_lba_high = 0x5, 53 reg_device = 0x6, 54 reg_status = 0x7, 55 reg_command = 0x7, 56 }; 57 58 enum { 59 BSY = 0x80, 60 DRDY = 0x40, 61 DF = 0x20, 62 DRQ = 0x08, 63 ERR = 0x01, 64 }; 65 66 enum { 67 DEV = 0x10, 68 LBA = 0x40, 69 }; 70 71 enum { 72 bmreg_cmd = 0x0, 73 bmreg_status = 0x2, 74 bmreg_prdt = 0x4, 75 }; 76 77 enum { 78 CMD_READ_DMA = 0xc8, 79 CMD_WRITE_DMA = 0xca, 80 CMD_FLUSH_CACHE = 0xe7, 81 CMD_IDENTIFY = 0xec, 82 83 CMDF_ABORT = 0x100, 84 CMDF_NO_BM = 0x200, 85 }; 86 87 enum { 88 BM_CMD_START = 0x1, 89 BM_CMD_WRITE = 0x8, /* write = from device to memory */ 90 }; 91 92 enum { 93 BM_STS_ACTIVE = 0x1, 94 BM_STS_ERROR = 0x2, 95 BM_STS_INTR = 0x4, 96 }; 97 98 enum { 99 PRDT_EOT = 0x80000000, 100 }; 101 102 #define assert_bit_set(data, mask) g_assert_cmphex((data) & (mask), ==, (mask)) 103 #define assert_bit_clear(data, mask) g_assert_cmphex((data) & (mask), ==, 0) 104 105 static QPCIBus *pcibus = NULL; 106 static QGuestAllocator *guest_malloc; 107 108 static char tmp_path[] = "/tmp/qtest.XXXXXX"; 109 static char debug_path[] = "/tmp/qtest-blkdebug.XXXXXX"; 110 111 static void ide_test_start(const char *cmdline_fmt, ...) 112 { 113 va_list ap; 114 char *cmdline; 115 116 va_start(ap, cmdline_fmt); 117 cmdline = g_strdup_vprintf(cmdline_fmt, ap); 118 va_end(ap); 119 120 qtest_start(cmdline); 121 guest_malloc = pc_alloc_init(); 122 123 g_free(cmdline); 124 } 125 126 static void ide_test_quit(void) 127 { 128 pc_alloc_uninit(guest_malloc); 129 guest_malloc = NULL; 130 qtest_end(); 131 } 132 133 static QPCIDevice *get_pci_device(uint16_t *bmdma_base) 134 { 135 QPCIDevice *dev; 136 uint16_t vendor_id, device_id; 137 138 if (!pcibus) { 139 pcibus = qpci_init_pc(); 140 } 141 142 /* Find PCI device and verify it's the right one */ 143 dev = qpci_device_find(pcibus, QPCI_DEVFN(IDE_PCI_DEV, IDE_PCI_FUNC)); 144 g_assert(dev != NULL); 145 146 vendor_id = qpci_config_readw(dev, PCI_VENDOR_ID); 147 device_id = qpci_config_readw(dev, PCI_DEVICE_ID); 148 g_assert(vendor_id == PCI_VENDOR_ID_INTEL); 149 g_assert(device_id == PCI_DEVICE_ID_INTEL_82371SB_1); 150 151 /* Map bmdma BAR */ 152 *bmdma_base = (uint16_t)(uintptr_t) qpci_iomap(dev, 4, NULL); 153 154 qpci_device_enable(dev); 155 156 return dev; 157 } 158 159 static void free_pci_device(QPCIDevice *dev) 160 { 161 /* libqos doesn't have a function for this, so free it manually */ 162 g_free(dev); 163 } 164 165 typedef struct PrdtEntry { 166 uint32_t addr; 167 uint32_t size; 168 } QEMU_PACKED PrdtEntry; 169 170 #define assert_bit_set(data, mask) g_assert_cmphex((data) & (mask), ==, (mask)) 171 #define assert_bit_clear(data, mask) g_assert_cmphex((data) & (mask), ==, 0) 172 173 static int send_dma_request(int cmd, uint64_t sector, int nb_sectors, 174 PrdtEntry *prdt, int prdt_entries) 175 { 176 QPCIDevice *dev; 177 uint16_t bmdma_base; 178 uintptr_t guest_prdt; 179 size_t len; 180 bool from_dev; 181 uint8_t status; 182 int flags; 183 184 dev = get_pci_device(&bmdma_base); 185 186 flags = cmd & ~0xff; 187 cmd &= 0xff; 188 189 switch (cmd) { 190 case CMD_READ_DMA: 191 from_dev = true; 192 break; 193 case CMD_WRITE_DMA: 194 from_dev = false; 195 break; 196 default: 197 g_assert_not_reached(); 198 } 199 200 if (flags & CMDF_NO_BM) { 201 qpci_config_writew(dev, PCI_COMMAND, 202 PCI_COMMAND_IO | PCI_COMMAND_MEMORY); 203 } 204 205 /* Select device 0 */ 206 outb(IDE_BASE + reg_device, 0 | LBA); 207 208 /* Stop any running transfer, clear any pending interrupt */ 209 outb(bmdma_base + bmreg_cmd, 0); 210 outb(bmdma_base + bmreg_status, BM_STS_INTR); 211 212 /* Setup PRDT */ 213 len = sizeof(*prdt) * prdt_entries; 214 guest_prdt = guest_alloc(guest_malloc, len); 215 memwrite(guest_prdt, prdt, len); 216 outl(bmdma_base + bmreg_prdt, guest_prdt); 217 218 /* ATA DMA command */ 219 outb(IDE_BASE + reg_nsectors, nb_sectors); 220 221 outb(IDE_BASE + reg_lba_low, sector & 0xff); 222 outb(IDE_BASE + reg_lba_middle, (sector >> 8) & 0xff); 223 outb(IDE_BASE + reg_lba_high, (sector >> 16) & 0xff); 224 225 outb(IDE_BASE + reg_command, cmd); 226 227 /* Start DMA transfer */ 228 outb(bmdma_base + bmreg_cmd, BM_CMD_START | (from_dev ? BM_CMD_WRITE : 0)); 229 230 if (flags & CMDF_ABORT) { 231 outb(bmdma_base + bmreg_cmd, 0); 232 } 233 234 /* Wait for the DMA transfer to complete */ 235 do { 236 status = inb(bmdma_base + bmreg_status); 237 } while ((status & (BM_STS_ACTIVE | BM_STS_INTR)) == BM_STS_ACTIVE); 238 239 g_assert_cmpint(get_irq(IDE_PRIMARY_IRQ), ==, !!(status & BM_STS_INTR)); 240 241 /* Check IDE status code */ 242 assert_bit_set(inb(IDE_BASE + reg_status), DRDY); 243 assert_bit_clear(inb(IDE_BASE + reg_status), BSY | DRQ); 244 245 /* Reading the status register clears the IRQ */ 246 g_assert(!get_irq(IDE_PRIMARY_IRQ)); 247 248 /* Stop DMA transfer if still active */ 249 if (status & BM_STS_ACTIVE) { 250 outb(bmdma_base + bmreg_cmd, 0); 251 } 252 253 free_pci_device(dev); 254 255 return status; 256 } 257 258 static void test_bmdma_simple_rw(void) 259 { 260 uint8_t status; 261 uint8_t *buf; 262 uint8_t *cmpbuf; 263 size_t len = 512; 264 uintptr_t guest_buf = guest_alloc(guest_malloc, len); 265 266 PrdtEntry prdt[] = { 267 { 268 .addr = cpu_to_le32(guest_buf), 269 .size = cpu_to_le32(len | PRDT_EOT), 270 }, 271 }; 272 273 buf = g_malloc(len); 274 cmpbuf = g_malloc(len); 275 276 /* Write 0x55 pattern to sector 0 */ 277 memset(buf, 0x55, len); 278 memwrite(guest_buf, buf, len); 279 280 status = send_dma_request(CMD_WRITE_DMA, 0, 1, prdt, ARRAY_SIZE(prdt)); 281 g_assert_cmphex(status, ==, BM_STS_INTR); 282 assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR); 283 284 /* Write 0xaa pattern to sector 1 */ 285 memset(buf, 0xaa, len); 286 memwrite(guest_buf, buf, len); 287 288 status = send_dma_request(CMD_WRITE_DMA, 1, 1, prdt, ARRAY_SIZE(prdt)); 289 g_assert_cmphex(status, ==, BM_STS_INTR); 290 assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR); 291 292 /* Read and verify 0x55 pattern in sector 0 */ 293 memset(cmpbuf, 0x55, len); 294 295 status = send_dma_request(CMD_READ_DMA, 0, 1, prdt, ARRAY_SIZE(prdt)); 296 g_assert_cmphex(status, ==, BM_STS_INTR); 297 assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR); 298 299 memread(guest_buf, buf, len); 300 g_assert(memcmp(buf, cmpbuf, len) == 0); 301 302 /* Read and verify 0xaa pattern in sector 1 */ 303 memset(cmpbuf, 0xaa, len); 304 305 status = send_dma_request(CMD_READ_DMA, 1, 1, prdt, ARRAY_SIZE(prdt)); 306 g_assert_cmphex(status, ==, BM_STS_INTR); 307 assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR); 308 309 memread(guest_buf, buf, len); 310 g_assert(memcmp(buf, cmpbuf, len) == 0); 311 312 313 g_free(buf); 314 g_free(cmpbuf); 315 } 316 317 static void test_bmdma_short_prdt(void) 318 { 319 uint8_t status; 320 321 PrdtEntry prdt[] = { 322 { 323 .addr = 0, 324 .size = cpu_to_le32(0x10 | PRDT_EOT), 325 }, 326 }; 327 328 /* Normal request */ 329 status = send_dma_request(CMD_READ_DMA, 0, 1, 330 prdt, ARRAY_SIZE(prdt)); 331 g_assert_cmphex(status, ==, 0); 332 assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR); 333 334 /* Abort the request before it completes */ 335 status = send_dma_request(CMD_READ_DMA | CMDF_ABORT, 0, 1, 336 prdt, ARRAY_SIZE(prdt)); 337 g_assert_cmphex(status, ==, 0); 338 assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR); 339 } 340 341 static void test_bmdma_long_prdt(void) 342 { 343 uint8_t status; 344 345 PrdtEntry prdt[] = { 346 { 347 .addr = 0, 348 .size = cpu_to_le32(0x1000 | PRDT_EOT), 349 }, 350 }; 351 352 /* Normal request */ 353 status = send_dma_request(CMD_READ_DMA, 0, 1, 354 prdt, ARRAY_SIZE(prdt)); 355 g_assert_cmphex(status, ==, BM_STS_ACTIVE | BM_STS_INTR); 356 assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR); 357 358 /* Abort the request before it completes */ 359 status = send_dma_request(CMD_READ_DMA | CMDF_ABORT, 0, 1, 360 prdt, ARRAY_SIZE(prdt)); 361 g_assert_cmphex(status, ==, BM_STS_INTR); 362 assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR); 363 } 364 365 static void test_bmdma_no_busmaster(void) 366 { 367 uint8_t status; 368 369 /* No PRDT_EOT, each entry addr 0/size 64k, and in theory qemu shouldn't be 370 * able to access it anyway because the Bus Master bit in the PCI command 371 * register isn't set. This is complete nonsense, but it used to be pretty 372 * good at confusing and occasionally crashing qemu. */ 373 PrdtEntry prdt[4096] = { }; 374 375 status = send_dma_request(CMD_READ_DMA | CMDF_NO_BM, 0, 512, 376 prdt, ARRAY_SIZE(prdt)); 377 378 /* Not entirely clear what the expected result is, but this is what we get 379 * in practice. At least we want to be aware of any changes. */ 380 g_assert_cmphex(status, ==, BM_STS_ACTIVE | BM_STS_INTR); 381 assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR); 382 } 383 384 static void test_bmdma_setup(void) 385 { 386 ide_test_start( 387 "-drive file=%s,if=ide,serial=%s,cache=writeback,format=raw " 388 "-global ide-hd.ver=%s", 389 tmp_path, "testdisk", "version"); 390 qtest_irq_intercept_in(global_qtest, "ioapic"); 391 } 392 393 static void test_bmdma_teardown(void) 394 { 395 ide_test_quit(); 396 } 397 398 static void string_cpu_to_be16(uint16_t *s, size_t bytes) 399 { 400 g_assert((bytes & 1) == 0); 401 bytes /= 2; 402 403 while (bytes--) { 404 *s = cpu_to_be16(*s); 405 s++; 406 } 407 } 408 409 static void test_identify(void) 410 { 411 uint8_t data; 412 uint16_t buf[256]; 413 int i; 414 int ret; 415 416 ide_test_start( 417 "-drive file=%s,if=ide,serial=%s,cache=writeback,format=raw " 418 "-global ide-hd.ver=%s", 419 tmp_path, "testdisk", "version"); 420 421 /* IDENTIFY command on device 0*/ 422 outb(IDE_BASE + reg_device, 0); 423 outb(IDE_BASE + reg_command, CMD_IDENTIFY); 424 425 /* Read in the IDENTIFY buffer and check registers */ 426 data = inb(IDE_BASE + reg_device); 427 g_assert_cmpint(data & DEV, ==, 0); 428 429 for (i = 0; i < 256; i++) { 430 data = inb(IDE_BASE + reg_status); 431 assert_bit_set(data, DRDY | DRQ); 432 assert_bit_clear(data, BSY | DF | ERR); 433 434 ((uint16_t*) buf)[i] = inw(IDE_BASE + reg_data); 435 } 436 437 data = inb(IDE_BASE + reg_status); 438 assert_bit_set(data, DRDY); 439 assert_bit_clear(data, BSY | DF | ERR | DRQ); 440 441 /* Check serial number/version in the buffer */ 442 string_cpu_to_be16(&buf[10], 20); 443 ret = memcmp(&buf[10], "testdisk ", 20); 444 g_assert(ret == 0); 445 446 string_cpu_to_be16(&buf[23], 8); 447 ret = memcmp(&buf[23], "version ", 8); 448 g_assert(ret == 0); 449 450 /* Write cache enabled bit */ 451 assert_bit_set(buf[85], 0x20); 452 453 ide_test_quit(); 454 } 455 456 static void test_flush(void) 457 { 458 uint8_t data; 459 460 ide_test_start( 461 "-drive file=blkdebug::%s,if=ide,cache=writeback,format=raw", 462 tmp_path); 463 464 /* Delay the completion of the flush request until we explicitly do it */ 465 qmp_discard_response("{'execute':'human-monitor-command', 'arguments': {" 466 " 'command-line':" 467 " 'qemu-io ide0-hd0 \"break flush_to_os A\"'} }"); 468 469 /* FLUSH CACHE command on device 0*/ 470 outb(IDE_BASE + reg_device, 0); 471 outb(IDE_BASE + reg_command, CMD_FLUSH_CACHE); 472 473 /* Check status while request is in flight*/ 474 data = inb(IDE_BASE + reg_status); 475 assert_bit_set(data, BSY | DRDY); 476 assert_bit_clear(data, DF | ERR | DRQ); 477 478 /* Complete the command */ 479 qmp_discard_response("{'execute':'human-monitor-command', 'arguments': {" 480 " 'command-line':" 481 " 'qemu-io ide0-hd0 \"resume A\"'} }"); 482 483 /* Check registers */ 484 data = inb(IDE_BASE + reg_device); 485 g_assert_cmpint(data & DEV, ==, 0); 486 487 do { 488 data = inb(IDE_BASE + reg_status); 489 } while (data & BSY); 490 491 assert_bit_set(data, DRDY); 492 assert_bit_clear(data, BSY | DF | ERR | DRQ); 493 494 ide_test_quit(); 495 } 496 497 static void prepare_blkdebug_script(const char *debug_fn, const char *event) 498 { 499 FILE *debug_file = fopen(debug_fn, "w"); 500 int ret; 501 502 fprintf(debug_file, "[inject-error]\n"); 503 fprintf(debug_file, "event = \"%s\"\n", event); 504 fprintf(debug_file, "errno = \"5\"\n"); 505 fprintf(debug_file, "state = \"1\"\n"); 506 fprintf(debug_file, "immediately = \"off\"\n"); 507 fprintf(debug_file, "once = \"on\"\n"); 508 509 fprintf(debug_file, "[set-state]\n"); 510 fprintf(debug_file, "event = \"%s\"\n", event); 511 fprintf(debug_file, "new_state = \"2\"\n"); 512 fflush(debug_file); 513 g_assert(!ferror(debug_file)); 514 515 ret = fclose(debug_file); 516 g_assert(ret == 0); 517 } 518 519 static void test_retry_flush(const char *machine) 520 { 521 uint8_t data; 522 const char *s; 523 524 prepare_blkdebug_script(debug_path, "flush_to_disk"); 525 526 ide_test_start( 527 "-vnc none " 528 "-drive file=blkdebug:%s:%s,if=ide,cache=writeback,format=raw," 529 "rerror=stop,werror=stop", 530 debug_path, tmp_path); 531 532 /* FLUSH CACHE command on device 0*/ 533 outb(IDE_BASE + reg_device, 0); 534 outb(IDE_BASE + reg_command, CMD_FLUSH_CACHE); 535 536 /* Check status while request is in flight*/ 537 data = inb(IDE_BASE + reg_status); 538 assert_bit_set(data, BSY | DRDY); 539 assert_bit_clear(data, DF | ERR | DRQ); 540 541 qmp_eventwait("STOP"); 542 543 /* Complete the command */ 544 s = "{'execute':'cont' }"; 545 qmp_discard_response(s); 546 547 /* Check registers */ 548 data = inb(IDE_BASE + reg_device); 549 g_assert_cmpint(data & DEV, ==, 0); 550 551 do { 552 data = inb(IDE_BASE + reg_status); 553 } while (data & BSY); 554 555 assert_bit_set(data, DRDY); 556 assert_bit_clear(data, BSY | DF | ERR | DRQ); 557 558 ide_test_quit(); 559 } 560 561 static void test_flush_nodev(void) 562 { 563 ide_test_start(""); 564 565 /* FLUSH CACHE command on device 0*/ 566 outb(IDE_BASE + reg_device, 0); 567 outb(IDE_BASE + reg_command, CMD_FLUSH_CACHE); 568 569 /* Just testing that qemu doesn't crash... */ 570 571 ide_test_quit(); 572 } 573 574 static void test_pci_retry_flush(const char *machine) 575 { 576 test_retry_flush("pc"); 577 } 578 579 static void test_isa_retry_flush(const char *machine) 580 { 581 test_retry_flush("isapc"); 582 } 583 584 int main(int argc, char **argv) 585 { 586 const char *arch = qtest_get_arch(); 587 int fd; 588 int ret; 589 590 /* Check architecture */ 591 if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) { 592 g_test_message("Skipping test for non-x86\n"); 593 return 0; 594 } 595 596 /* Create temporary blkdebug instructions */ 597 fd = mkstemp(debug_path); 598 g_assert(fd >= 0); 599 close(fd); 600 601 /* Create a temporary raw image */ 602 fd = mkstemp(tmp_path); 603 g_assert(fd >= 0); 604 ret = ftruncate(fd, TEST_IMAGE_SIZE); 605 g_assert(ret == 0); 606 close(fd); 607 608 /* Run the tests */ 609 g_test_init(&argc, &argv, NULL); 610 611 qtest_add_func("/ide/identify", test_identify); 612 613 qtest_add_func("/ide/bmdma/setup", test_bmdma_setup); 614 qtest_add_func("/ide/bmdma/simple_rw", test_bmdma_simple_rw); 615 qtest_add_func("/ide/bmdma/short_prdt", test_bmdma_short_prdt); 616 qtest_add_func("/ide/bmdma/long_prdt", test_bmdma_long_prdt); 617 qtest_add_func("/ide/bmdma/no_busmaster", test_bmdma_no_busmaster); 618 qtest_add_func("/ide/bmdma/teardown", test_bmdma_teardown); 619 620 qtest_add_func("/ide/flush", test_flush); 621 qtest_add_func("/ide/flush/nodev", test_flush_nodev); 622 qtest_add_func("/ide/flush/retry_pci", test_pci_retry_flush); 623 qtest_add_func("/ide/flush/retry_isa", test_isa_retry_flush); 624 625 ret = g_test_run(); 626 627 /* Cleanup */ 628 unlink(tmp_path); 629 unlink(debug_path); 630 631 return ret; 632 } 633