xref: /qemu/tests/qtest/cxl-test.c (revision 92fd46b68a0ca2f37d46fd69616034b2703966b2)
1 /*
2  * QTest testcase for CXL
3  *
4  * This work is licensed under the terms of the GNU GPL, version 2 or later.
5  * See the COPYING file in the top-level directory.
6  */
7 
8 #include "qemu/osdep.h"
9 #include "libqtest-single.h"
10 
11 #define QEMU_PXB_CMD "-machine q35,cxl=on " \
12                      "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 "
13 
14 #define QEMU_2PXB_CMD "-machine q35,cxl=on " \
15                       "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 "  \
16                       "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 "
17 
18 #define QEMU_RP "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 "
19 
20 /* Dual ports on first pxb */
21 #define QEMU_2RP "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " \
22                  "-device cxl-rp,id=rp1,bus=cxl.0,chassis=0,slot=1 "
23 
24 /* Dual ports on each of the pxb instances */
25 #define QEMU_4RP "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " \
26                  "-device cxl-rp,id=rp1,bus=cxl.0,chassis=0,slot=1 " \
27                  "-device cxl-rp,id=rp2,bus=cxl.1,chassis=0,slot=2 " \
28                  "-device cxl-rp,id=rp3,bus=cxl.1,chassis=0,slot=3 "
29 
30 #define QEMU_T3D "-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M " \
31                  "-object memory-backend-file,id=lsa0,mem-path=%s,size=256M "    \
32                  "-device cxl-type3,bus=rp0,memdev=cxl-mem0,lsa=lsa0,id=cxl-pmem0 "
33 
34 #define QEMU_2T3D "-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M "    \
35                   "-object memory-backend-file,id=lsa0,mem-path=%s,size=256M "    \
36                   "-device cxl-type3,bus=rp0,memdev=cxl-mem0,lsa=lsa0,id=cxl-pmem0 " \
37                   "-object memory-backend-file,id=cxl-mem1,mem-path=%s,size=256M "    \
38                   "-object memory-backend-file,id=lsa1,mem-path=%s,size=256M "    \
39                   "-device cxl-type3,bus=rp1,memdev=cxl-mem1,lsa=lsa1,id=cxl-pmem1 "
40 
41 #define QEMU_4T3D "-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M " \
42                   "-object memory-backend-file,id=lsa0,mem-path=%s,size=256M "    \
43                   "-device cxl-type3,bus=rp0,memdev=cxl-mem0,lsa=lsa0,id=cxl-pmem0 " \
44                   "-object memory-backend-file,id=cxl-mem1,mem-path=%s,size=256M "    \
45                   "-object memory-backend-file,id=lsa1,mem-path=%s,size=256M "    \
46                   "-device cxl-type3,bus=rp1,memdev=cxl-mem1,lsa=lsa1,id=cxl-pmem1 " \
47                   "-object memory-backend-file,id=cxl-mem2,mem-path=%s,size=256M "    \
48                   "-object memory-backend-file,id=lsa2,mem-path=%s,size=256M "    \
49                   "-device cxl-type3,bus=rp2,memdev=cxl-mem2,lsa=lsa2,id=cxl-pmem2 " \
50                   "-object memory-backend-file,id=cxl-mem3,mem-path=%s,size=256M "    \
51                   "-object memory-backend-file,id=lsa3,mem-path=%s,size=256M "    \
52                   "-device cxl-type3,bus=rp3,memdev=cxl-mem3,lsa=lsa3,id=cxl-pmem3 "
53 
54 static void cxl_basic_hb(void)
55 {
56     qtest_start("-machine q35,cxl=on");
57     qtest_end();
58 }
59 
60 static void cxl_basic_pxb(void)
61 {
62     qtest_start("-machine q35,cxl=on -device pxb-cxl,bus=pcie.0");
63     qtest_end();
64 }
65 
66 static void cxl_pxb_with_window(void)
67 {
68     qtest_start(QEMU_PXB_CMD);
69     qtest_end();
70 }
71 
72 static void cxl_2pxb_with_window(void)
73 {
74     qtest_start(QEMU_2PXB_CMD);
75     qtest_end();
76 }
77 
78 static void cxl_root_port(void)
79 {
80     qtest_start(QEMU_PXB_CMD QEMU_RP);
81     qtest_end();
82 }
83 
84 static void cxl_2root_port(void)
85 {
86     qtest_start(QEMU_PXB_CMD QEMU_2RP);
87     qtest_end();
88 }
89 
90 static void cxl_t3d(void)
91 {
92     g_autoptr(GString) cmdline = g_string_new(NULL);
93     char template[] = "/tmp/cxl-test-XXXXXX";
94     const char *tmpfs;
95 
96     tmpfs = mkdtemp(template);
97 
98     g_string_printf(cmdline, QEMU_PXB_CMD QEMU_RP QEMU_T3D, tmpfs, tmpfs);
99 
100     qtest_start(cmdline->str);
101     qtest_end();
102 }
103 
104 static void cxl_1pxb_2rp_2t3d(void)
105 {
106     g_autoptr(GString) cmdline = g_string_new(NULL);
107     char template[] = "/tmp/cxl-test-XXXXXX";
108     const char *tmpfs;
109 
110     tmpfs = mkdtemp(template);
111 
112     g_string_printf(cmdline, QEMU_PXB_CMD QEMU_2RP QEMU_2T3D,
113                     tmpfs, tmpfs, tmpfs, tmpfs);
114 
115     qtest_start(cmdline->str);
116     qtest_end();
117 }
118 
119 static void cxl_2pxb_4rp_4t3d(void)
120 {
121     g_autoptr(GString) cmdline = g_string_new(NULL);
122     char template[] = "/tmp/cxl-test-XXXXXX";
123     const char *tmpfs;
124 
125     tmpfs = mkdtemp(template);
126 
127     g_string_printf(cmdline, QEMU_2PXB_CMD QEMU_4RP QEMU_4T3D,
128                     tmpfs, tmpfs, tmpfs, tmpfs, tmpfs, tmpfs,
129                     tmpfs, tmpfs);
130 
131     qtest_start(cmdline->str);
132     qtest_end();
133 }
134 
135 int main(int argc, char **argv)
136 {
137     g_test_init(&argc, &argv, NULL);
138 
139     qtest_add_func("/pci/cxl/basic_hostbridge", cxl_basic_hb);
140     qtest_add_func("/pci/cxl/basic_pxb", cxl_basic_pxb);
141     qtest_add_func("/pci/cxl/pxb_with_window", cxl_pxb_with_window);
142     qtest_add_func("/pci/cxl/pxb_x2_with_window", cxl_2pxb_with_window);
143     qtest_add_func("/pci/cxl/rp", cxl_root_port);
144     qtest_add_func("/pci/cxl/rp_x2", cxl_2root_port);
145     qtest_add_func("/pci/cxl/type3_device", cxl_t3d);
146     qtest_add_func("/pci/cxl/rp_x2_type3_x2", cxl_1pxb_2rp_2t3d);
147     qtest_add_func("/pci/cxl/pxb_x2_root_port_x4_type3_x4", cxl_2pxb_4rp_4t3d);
148     return g_test_run();
149 }
150