1 /* 2 * QTest testcase for the ASPEED Hash and Crypto Engine 3 * 4 * SPDX-License-Identifier: GPL-2.0-or-later 5 * Copyright 2021 IBM Corp. 6 */ 7 8 #include "qemu/osdep.h" 9 #include "libqtest.h" 10 #include "qemu/bitops.h" 11 #include "aspeed-hace-utils.h" 12 13 /* 14 * Test vector is the ascii "abc" 15 * 16 * Expected results were generated using command line utitiles: 17 * 18 * echo -n -e 'abc' | dd of=/tmp/test 19 * for hash in sha512sum sha384sum sha256sum md5sum; do $hash /tmp/test; done 20 * 21 */ 22 static const uint8_t test_vector[3] = {0x61, 0x62, 0x63}; 23 24 static const uint8_t test_result_sha512[64] = { 25 0xdd, 0xaf, 0x35, 0xa1, 0x93, 0x61, 0x7a, 0xba, 0xcc, 0x41, 0x73, 0x49, 26 0xae, 0x20, 0x41, 0x31, 0x12, 0xe6, 0xfa, 0x4e, 0x89, 0xa9, 0x7e, 0xa2, 27 0x0a, 0x9e, 0xee, 0xe6, 0x4b, 0x55, 0xd3, 0x9a, 0x21, 0x92, 0x99, 0x2a, 28 0x27, 0x4f, 0xc1, 0xa8, 0x36, 0xba, 0x3c, 0x23, 0xa3, 0xfe, 0xeb, 0xbd, 29 0x45, 0x4d, 0x44, 0x23, 0x64, 0x3c, 0xe8, 0x0e, 0x2a, 0x9a, 0xc9, 0x4f, 30 0xa5, 0x4c, 0xa4, 0x9f}; 31 32 static const uint8_t test_result_sha384[48] = { 33 0xcb, 0x00, 0x75, 0x3f, 0x45, 0xa3, 0x5e, 0x8b, 0xb5, 0xa0, 0x3d, 0x69, 34 0x9a, 0xc6, 0x50, 0x07, 0x27, 0x2c, 0x32, 0xab, 0x0e, 0xde, 0xd1, 0x63, 35 0x1a, 0x8b, 0x60, 0x5a, 0x43, 0xff, 0x5b, 0xed, 0x80, 0x86, 0x07, 0x2b, 36 0xa1, 0xe7, 0xcc, 0x23, 0x58, 0xba, 0xec, 0xa1, 0x34, 0xc8, 0x25, 0xa7}; 37 38 static const uint8_t test_result_sha256[32] = { 39 0xba, 0x78, 0x16, 0xbf, 0x8f, 0x01, 0xcf, 0xea, 0x41, 0x41, 0x40, 0xde, 40 0x5d, 0xae, 0x22, 0x23, 0xb0, 0x03, 0x61, 0xa3, 0x96, 0x17, 0x7a, 0x9c, 41 0xb4, 0x10, 0xff, 0x61, 0xf2, 0x00, 0x15, 0xad}; 42 43 static const uint8_t test_result_md5[16] = { 44 0x90, 0x01, 0x50, 0x98, 0x3c, 0xd2, 0x4f, 0xb0, 0xd6, 0x96, 0x3f, 0x7d, 45 0x28, 0xe1, 0x7f, 0x72}; 46 47 /* 48 * The Scatter-Gather Test vector is the ascii "abc" "def" "ghi", broken 49 * into blocks of 3 characters as shown 50 * 51 * Expected results were generated using command line utitiles: 52 * 53 * echo -n -e 'abcdefghijkl' | dd of=/tmp/test 54 * for hash in sha512sum sha384sum sha256sum; do $hash /tmp/test; done 55 * 56 */ 57 static const uint8_t test_vector_sg1[6] = {0x61, 0x62, 0x63, 0x64, 0x65, 0x66}; 58 static const uint8_t test_vector_sg2[3] = {0x67, 0x68, 0x69}; 59 static const uint8_t test_vector_sg3[3] = {0x6a, 0x6b, 0x6c}; 60 61 static const uint8_t test_result_sg_sha512[64] = { 62 0x17, 0x80, 0x7c, 0x72, 0x8e, 0xe3, 0xba, 0x35, 0xe7, 0xcf, 0x7a, 0xf8, 63 0x23, 0x11, 0x6d, 0x26, 0xe4, 0x1e, 0x5d, 0x4d, 0x6c, 0x2f, 0xf1, 0xf3, 64 0x72, 0x0d, 0x3d, 0x96, 0xaa, 0xcb, 0x6f, 0x69, 0xde, 0x64, 0x2e, 0x63, 65 0xd5, 0xb7, 0x3f, 0xc3, 0x96, 0xc1, 0x2b, 0xe3, 0x8b, 0x2b, 0xd5, 0xd8, 66 0x84, 0x25, 0x7c, 0x32, 0xc8, 0xf6, 0xd0, 0x85, 0x4a, 0xe6, 0xb5, 0x40, 67 0xf8, 0x6d, 0xda, 0x2e}; 68 69 static const uint8_t test_result_sg_sha384[48] = { 70 0x10, 0x3c, 0xa9, 0x6c, 0x06, 0xa1, 0xce, 0x79, 0x8f, 0x08, 0xf8, 0xef, 71 0xf0, 0xdf, 0xb0, 0xcc, 0xdb, 0x56, 0x7d, 0x48, 0xb2, 0x85, 0xb2, 0x3d, 72 0x0c, 0xd7, 0x73, 0x45, 0x46, 0x67, 0xa3, 0xc2, 0xfa, 0x5f, 0x1b, 0x58, 73 0xd9, 0xcd, 0xf2, 0x32, 0x9b, 0xd9, 0x97, 0x97, 0x30, 0xbf, 0xaa, 0xff}; 74 75 static const uint8_t test_result_sg_sha256[32] = { 76 0xd6, 0x82, 0xed, 0x4c, 0xa4, 0xd9, 0x89, 0xc1, 0x34, 0xec, 0x94, 0xf1, 77 0x55, 0x1e, 0x1e, 0xc5, 0x80, 0xdd, 0x6d, 0x5a, 0x6e, 0xcd, 0xe9, 0xf3, 78 0xd3, 0x5e, 0x6e, 0x4a, 0x71, 0x7f, 0xbd, 0xe4}; 79 80 /* 81 * The accumulative mode requires firmware to provide internal initial state 82 * and message padding (including length L at the end of padding). 83 * 84 * This test vector is a ascii text "abc" with padding message. 85 * 86 * Expected results were generated using command line utitiles: 87 * 88 * echo -n -e 'abc' | dd of=/tmp/test 89 * for hash in sha512sum sha384sum sha256sum; do $hash /tmp/test; done 90 */ 91 static const uint8_t test_vector_accum_512[128] = { 92 0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00, 93 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 94 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 95 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 96 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 97 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 98 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 99 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 100 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 101 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 102 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 103 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 104 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 105 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 106 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 107 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18}; 108 109 static const uint8_t test_vector_accum_384[128] = { 110 0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00, 111 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 112 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 113 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 114 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 115 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 116 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 117 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 118 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 119 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 120 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 121 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 122 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 123 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 124 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 125 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18}; 126 127 static const uint8_t test_vector_accum_256[64] = { 128 0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00, 129 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 130 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 131 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 132 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 133 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 134 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 135 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18}; 136 137 static const uint8_t test_result_accum_sha512[64] = { 138 0xdd, 0xaf, 0x35, 0xa1, 0x93, 0x61, 0x7a, 0xba, 0xcc, 0x41, 0x73, 0x49, 139 0xae, 0x20, 0x41, 0x31, 0x12, 0xe6, 0xfa, 0x4e, 0x89, 0xa9, 0x7e, 0xa2, 140 0x0a, 0x9e, 0xee, 0xe6, 0x4b, 0x55, 0xd3, 0x9a, 0x21, 0x92, 0x99, 0x2a, 141 0x27, 0x4f, 0xc1, 0xa8, 0x36, 0xba, 0x3c, 0x23, 0xa3, 0xfe, 0xeb, 0xbd, 142 0x45, 0x4d, 0x44, 0x23, 0x64, 0x3c, 0xe8, 0x0e, 0x2a, 0x9a, 0xc9, 0x4f, 143 0xa5, 0x4c, 0xa4, 0x9f}; 144 145 static const uint8_t test_result_accum_sha384[48] = { 146 0xcb, 0x00, 0x75, 0x3f, 0x45, 0xa3, 0x5e, 0x8b, 0xb5, 0xa0, 0x3d, 0x69, 147 0x9a, 0xc6, 0x50, 0x07, 0x27, 0x2c, 0x32, 0xab, 0x0e, 0xde, 0xd1, 0x63, 148 0x1a, 0x8b, 0x60, 0x5a, 0x43, 0xff, 0x5b, 0xed, 0x80, 0x86, 0x07, 0x2b, 149 0xa1, 0xe7, 0xcc, 0x23, 0x58, 0xba, 0xec, 0xa1, 0x34, 0xc8, 0x25, 0xa7}; 150 151 static const uint8_t test_result_accum_sha256[32] = { 152 0xba, 0x78, 0x16, 0xbf, 0x8f, 0x01, 0xcf, 0xea, 0x41, 0x41, 0x40, 0xde, 153 0x5d, 0xae, 0x22, 0x23, 0xb0, 0x03, 0x61, 0xa3, 0x96, 0x17, 0x7a, 0x9c, 154 0xb4, 0x10, 0xff, 0x61, 0xf2, 0x00, 0x15, 0xad}; 155 156 static void write_regs(QTestState *s, uint32_t base, uint64_t src, 157 uint32_t length, uint64_t out, uint32_t method) 158 { 159 qtest_writel(s, base + HACE_HASH_SRC, extract64(src, 0, 32)); 160 qtest_writel(s, base + HACE_HASH_SRC_HI, extract64(src, 32, 32)); 161 qtest_writel(s, base + HACE_HASH_DIGEST, extract64(out, 0, 32)); 162 qtest_writel(s, base + HACE_HASH_DIGEST_HI, extract64(out, 32, 32)); 163 qtest_writel(s, base + HACE_HASH_DATA_LEN, length); 164 qtest_writel(s, base + HACE_HASH_CMD, HACE_SHA_BE_EN | method); 165 } 166 167 void aspeed_test_md5(const char *machine, const uint32_t base, 168 const uint64_t src_addr) 169 170 { 171 QTestState *s = qtest_init(machine); 172 173 uint64_t digest_addr = src_addr + 0x010000; 174 uint8_t digest[16] = {0}; 175 176 /* Check engine is idle, no busy or irq bits set */ 177 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 178 179 /* Write test vector into memory */ 180 qtest_memwrite(s, src_addr, test_vector, sizeof(test_vector)); 181 182 write_regs(s, base, src_addr, sizeof(test_vector), 183 digest_addr, HACE_ALGO_MD5); 184 185 /* Check hash IRQ status is asserted */ 186 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); 187 188 /* Clear IRQ status and check status is deasserted */ 189 qtest_writel(s, base + HACE_STS, 0x00000200); 190 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 191 192 /* Read computed digest from memory */ 193 qtest_memread(s, digest_addr, digest, sizeof(digest)); 194 195 /* Check result of computation */ 196 g_assert_cmpmem(digest, sizeof(digest), 197 test_result_md5, sizeof(digest)); 198 199 qtest_quit(s); 200 } 201 202 void aspeed_test_sha256(const char *machine, const uint32_t base, 203 const uint64_t src_addr) 204 { 205 QTestState *s = qtest_init(machine); 206 207 const uint64_t digest_addr = src_addr + 0x10000; 208 uint8_t digest[32] = {0}; 209 210 /* Check engine is idle, no busy or irq bits set */ 211 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 212 213 /* Write test vector into memory */ 214 qtest_memwrite(s, src_addr, test_vector, sizeof(test_vector)); 215 216 write_regs(s, base, src_addr, sizeof(test_vector), digest_addr, 217 HACE_ALGO_SHA256); 218 219 /* Check hash IRQ status is asserted */ 220 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); 221 222 /* Clear IRQ status and check status is deasserted */ 223 qtest_writel(s, base + HACE_STS, 0x00000200); 224 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 225 226 /* Read computed digest from memory */ 227 qtest_memread(s, digest_addr, digest, sizeof(digest)); 228 229 /* Check result of computation */ 230 g_assert_cmpmem(digest, sizeof(digest), 231 test_result_sha256, sizeof(digest)); 232 233 qtest_quit(s); 234 } 235 236 void aspeed_test_sha384(const char *machine, const uint32_t base, 237 const uint64_t src_addr) 238 { 239 QTestState *s = qtest_init(machine); 240 241 const uint64_t digest_addr = src_addr + 0x10000; 242 uint8_t digest[48] = {0}; 243 244 /* Check engine is idle, no busy or irq bits set */ 245 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 246 247 /* Write test vector into memory */ 248 qtest_memwrite(s, src_addr, test_vector, sizeof(test_vector)); 249 250 write_regs(s, base, src_addr, sizeof(test_vector), digest_addr, 251 HACE_ALGO_SHA384); 252 253 /* Check hash IRQ status is asserted */ 254 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); 255 256 /* Clear IRQ status and check status is deasserted */ 257 qtest_writel(s, base + HACE_STS, 0x00000200); 258 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 259 260 /* Read computed digest from memory */ 261 qtest_memread(s, digest_addr, digest, sizeof(digest)); 262 263 /* Check result of computation */ 264 g_assert_cmpmem(digest, sizeof(digest), 265 test_result_sha384, sizeof(digest)); 266 267 qtest_quit(s); 268 } 269 270 void aspeed_test_sha512(const char *machine, const uint32_t base, 271 const uint64_t src_addr) 272 { 273 QTestState *s = qtest_init(machine); 274 275 const uint64_t digest_addr = src_addr + 0x10000; 276 uint8_t digest[64] = {0}; 277 278 /* Check engine is idle, no busy or irq bits set */ 279 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 280 281 /* Write test vector into memory */ 282 qtest_memwrite(s, src_addr, test_vector, sizeof(test_vector)); 283 284 write_regs(s, base, src_addr, sizeof(test_vector), digest_addr, 285 HACE_ALGO_SHA512); 286 287 /* Check hash IRQ status is asserted */ 288 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); 289 290 /* Clear IRQ status and check status is deasserted */ 291 qtest_writel(s, base + HACE_STS, 0x00000200); 292 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 293 294 /* Read computed digest from memory */ 295 qtest_memread(s, digest_addr, digest, sizeof(digest)); 296 297 /* Check result of computation */ 298 g_assert_cmpmem(digest, sizeof(digest), 299 test_result_sha512, sizeof(digest)); 300 301 qtest_quit(s); 302 } 303 304 void aspeed_test_sha256_sg(const char *machine, const uint32_t base, 305 const uint64_t src_addr) 306 { 307 QTestState *s = qtest_init(machine); 308 309 const uint64_t src_addr_1 = src_addr + 0x10000; 310 const uint64_t src_addr_2 = src_addr + 0x20000; 311 const uint64_t src_addr_3 = src_addr + 0x30000; 312 const uint64_t digest_addr = src_addr + 0x40000; 313 uint8_t digest[32] = {0}; 314 struct AspeedSgList array[] = { 315 { cpu_to_le32(sizeof(test_vector_sg1)), 316 cpu_to_le32(src_addr_1) }, 317 { cpu_to_le32(sizeof(test_vector_sg2)), 318 cpu_to_le32(src_addr_2) }, 319 { cpu_to_le32(sizeof(test_vector_sg3) | SG_LIST_LEN_LAST), 320 cpu_to_le32(src_addr_3) }, 321 }; 322 323 /* Check engine is idle, no busy or irq bits set */ 324 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 325 326 /* Write test vector into memory */ 327 qtest_memwrite(s, src_addr_1, test_vector_sg1, sizeof(test_vector_sg1)); 328 qtest_memwrite(s, src_addr_2, test_vector_sg2, sizeof(test_vector_sg2)); 329 qtest_memwrite(s, src_addr_3, test_vector_sg3, sizeof(test_vector_sg3)); 330 qtest_memwrite(s, src_addr, array, sizeof(array)); 331 332 write_regs(s, base, src_addr, 333 (sizeof(test_vector_sg1) 334 + sizeof(test_vector_sg2) 335 + sizeof(test_vector_sg3)), 336 digest_addr, HACE_ALGO_SHA256 | HACE_SG_EN); 337 338 /* Check hash IRQ status is asserted */ 339 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); 340 341 /* Clear IRQ status and check status is deasserted */ 342 qtest_writel(s, base + HACE_STS, 0x00000200); 343 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 344 345 /* Read computed digest from memory */ 346 qtest_memread(s, digest_addr, digest, sizeof(digest)); 347 348 /* Check result of computation */ 349 g_assert_cmpmem(digest, sizeof(digest), 350 test_result_sg_sha256, sizeof(digest)); 351 352 qtest_quit(s); 353 } 354 355 void aspeed_test_sha384_sg(const char *machine, const uint32_t base, 356 const uint64_t src_addr) 357 { 358 QTestState *s = qtest_init(machine); 359 360 const uint64_t src_addr_1 = src_addr + 0x10000; 361 const uint64_t src_addr_2 = src_addr + 0x20000; 362 const uint64_t src_addr_3 = src_addr + 0x30000; 363 const uint64_t digest_addr = src_addr + 0x40000; 364 uint8_t digest[48] = {0}; 365 struct AspeedSgList array[] = { 366 { cpu_to_le32(sizeof(test_vector_sg1)), 367 cpu_to_le32(src_addr_1) }, 368 { cpu_to_le32(sizeof(test_vector_sg2)), 369 cpu_to_le32(src_addr_2) }, 370 { cpu_to_le32(sizeof(test_vector_sg3) | SG_LIST_LEN_LAST), 371 cpu_to_le32(src_addr_3) }, 372 }; 373 374 /* Check engine is idle, no busy or irq bits set */ 375 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 376 377 /* Write test vector into memory */ 378 qtest_memwrite(s, src_addr_1, test_vector_sg1, sizeof(test_vector_sg1)); 379 qtest_memwrite(s, src_addr_2, test_vector_sg2, sizeof(test_vector_sg2)); 380 qtest_memwrite(s, src_addr_3, test_vector_sg3, sizeof(test_vector_sg3)); 381 qtest_memwrite(s, src_addr, array, sizeof(array)); 382 383 write_regs(s, base, src_addr, 384 (sizeof(test_vector_sg1) 385 + sizeof(test_vector_sg2) 386 + sizeof(test_vector_sg3)), 387 digest_addr, HACE_ALGO_SHA384 | HACE_SG_EN); 388 389 /* Check hash IRQ status is asserted */ 390 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); 391 392 /* Clear IRQ status and check status is deasserted */ 393 qtest_writel(s, base + HACE_STS, 0x00000200); 394 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 395 396 /* Read computed digest from memory */ 397 qtest_memread(s, digest_addr, digest, sizeof(digest)); 398 399 /* Check result of computation */ 400 g_assert_cmpmem(digest, sizeof(digest), 401 test_result_sg_sha384, sizeof(digest)); 402 403 qtest_quit(s); 404 } 405 406 void aspeed_test_sha512_sg(const char *machine, const uint32_t base, 407 const uint64_t src_addr) 408 { 409 QTestState *s = qtest_init(machine); 410 411 const uint64_t src_addr_1 = src_addr + 0x10000; 412 const uint64_t src_addr_2 = src_addr + 0x20000; 413 const uint64_t src_addr_3 = src_addr + 0x30000; 414 const uint64_t digest_addr = src_addr + 0x40000; 415 uint8_t digest[64] = {0}; 416 struct AspeedSgList array[] = { 417 { cpu_to_le32(sizeof(test_vector_sg1)), 418 cpu_to_le32(src_addr_1) }, 419 { cpu_to_le32(sizeof(test_vector_sg2)), 420 cpu_to_le32(src_addr_2) }, 421 { cpu_to_le32(sizeof(test_vector_sg3) | SG_LIST_LEN_LAST), 422 cpu_to_le32(src_addr_3) }, 423 }; 424 425 /* Check engine is idle, no busy or irq bits set */ 426 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 427 428 /* Write test vector into memory */ 429 qtest_memwrite(s, src_addr_1, test_vector_sg1, sizeof(test_vector_sg1)); 430 qtest_memwrite(s, src_addr_2, test_vector_sg2, sizeof(test_vector_sg2)); 431 qtest_memwrite(s, src_addr_3, test_vector_sg3, sizeof(test_vector_sg3)); 432 qtest_memwrite(s, src_addr, array, sizeof(array)); 433 434 write_regs(s, base, src_addr, 435 (sizeof(test_vector_sg1) 436 + sizeof(test_vector_sg2) 437 + sizeof(test_vector_sg3)), 438 digest_addr, HACE_ALGO_SHA512 | HACE_SG_EN); 439 440 /* Check hash IRQ status is asserted */ 441 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); 442 443 /* Clear IRQ status and check status is deasserted */ 444 qtest_writel(s, base + HACE_STS, 0x00000200); 445 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 446 447 /* Read computed digest from memory */ 448 qtest_memread(s, digest_addr, digest, sizeof(digest)); 449 450 /* Check result of computation */ 451 g_assert_cmpmem(digest, sizeof(digest), 452 test_result_sg_sha512, sizeof(digest)); 453 454 qtest_quit(s); 455 } 456 457 void aspeed_test_sha256_accum(const char *machine, const uint32_t base, 458 const uint64_t src_addr) 459 { 460 QTestState *s = qtest_init(machine); 461 462 const uint64_t buffer_addr = src_addr + 0x10000; 463 const uint64_t digest_addr = src_addr + 0x40000; 464 uint8_t digest[32] = {0}; 465 struct AspeedSgList array[] = { 466 { cpu_to_le32(sizeof(test_vector_accum_256) | SG_LIST_LEN_LAST), 467 cpu_to_le32(buffer_addr) }, 468 }; 469 470 /* Check engine is idle, no busy or irq bits set */ 471 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 472 473 /* Write test vector into memory */ 474 qtest_memwrite(s, buffer_addr, test_vector_accum_256, 475 sizeof(test_vector_accum_256)); 476 qtest_memwrite(s, src_addr, array, sizeof(array)); 477 478 write_regs(s, base, src_addr, sizeof(test_vector_accum_256), 479 digest_addr, HACE_ALGO_SHA256 | HACE_SG_EN | HACE_ACCUM_EN); 480 481 /* Check hash IRQ status is asserted */ 482 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); 483 484 /* Clear IRQ status and check status is deasserted */ 485 qtest_writel(s, base + HACE_STS, 0x00000200); 486 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 487 488 /* Read computed digest from memory */ 489 qtest_memread(s, digest_addr, digest, sizeof(digest)); 490 491 /* Check result of computation */ 492 g_assert_cmpmem(digest, sizeof(digest), 493 test_result_accum_sha256, sizeof(digest)); 494 495 qtest_quit(s); 496 } 497 498 void aspeed_test_sha384_accum(const char *machine, const uint32_t base, 499 const uint64_t src_addr) 500 { 501 QTestState *s = qtest_init(machine); 502 503 const uint64_t buffer_addr = src_addr + 0x10000; 504 const uint64_t digest_addr = src_addr + 0x40000; 505 uint8_t digest[48] = {0}; 506 struct AspeedSgList array[] = { 507 { cpu_to_le32(sizeof(test_vector_accum_384) | SG_LIST_LEN_LAST), 508 cpu_to_le32(buffer_addr) }, 509 }; 510 511 /* Check engine is idle, no busy or irq bits set */ 512 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 513 514 /* Write test vector into memory */ 515 qtest_memwrite(s, buffer_addr, test_vector_accum_384, 516 sizeof(test_vector_accum_384)); 517 qtest_memwrite(s, src_addr, array, sizeof(array)); 518 519 write_regs(s, base, src_addr, sizeof(test_vector_accum_384), 520 digest_addr, HACE_ALGO_SHA384 | HACE_SG_EN | HACE_ACCUM_EN); 521 522 /* Check hash IRQ status is asserted */ 523 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); 524 525 /* Clear IRQ status and check status is deasserted */ 526 qtest_writel(s, base + HACE_STS, 0x00000200); 527 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 528 529 /* Read computed digest from memory */ 530 qtest_memread(s, digest_addr, digest, sizeof(digest)); 531 532 /* Check result of computation */ 533 g_assert_cmpmem(digest, sizeof(digest), 534 test_result_accum_sha384, sizeof(digest)); 535 536 qtest_quit(s); 537 } 538 539 void aspeed_test_sha512_accum(const char *machine, const uint32_t base, 540 const uint64_t src_addr) 541 { 542 QTestState *s = qtest_init(machine); 543 544 const uint64_t buffer_addr = src_addr + 0x10000; 545 const uint64_t digest_addr = src_addr + 0x40000; 546 uint8_t digest[64] = {0}; 547 struct AspeedSgList array[] = { 548 { cpu_to_le32(sizeof(test_vector_accum_512) | SG_LIST_LEN_LAST), 549 cpu_to_le32(buffer_addr) }, 550 }; 551 552 /* Check engine is idle, no busy or irq bits set */ 553 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 554 555 /* Write test vector into memory */ 556 qtest_memwrite(s, buffer_addr, test_vector_accum_512, 557 sizeof(test_vector_accum_512)); 558 qtest_memwrite(s, src_addr, array, sizeof(array)); 559 560 write_regs(s, base, src_addr, sizeof(test_vector_accum_512), 561 digest_addr, HACE_ALGO_SHA512 | HACE_SG_EN | HACE_ACCUM_EN); 562 563 /* Check hash IRQ status is asserted */ 564 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); 565 566 /* Clear IRQ status and check status is deasserted */ 567 qtest_writel(s, base + HACE_STS, 0x00000200); 568 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 569 570 /* Read computed digest from memory */ 571 qtest_memread(s, digest_addr, digest, sizeof(digest)); 572 573 /* Check result of computation */ 574 g_assert_cmpmem(digest, sizeof(digest), 575 test_result_accum_sha512, sizeof(digest)); 576 577 qtest_quit(s); 578 } 579 580 void aspeed_test_addresses(const char *machine, const uint32_t base, 581 const struct AspeedMasks *expected) 582 { 583 QTestState *s = qtest_init(machine); 584 585 /* 586 * Check command mode is zero, meaning engine is in direct access mode, 587 * as this affects the masking behavior of the HASH_SRC register. 588 */ 589 g_assert_cmphex(qtest_readl(s, base + HACE_CMD), ==, 0); 590 g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), ==, 0); 591 g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC_HI), ==, 0); 592 g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), ==, 0); 593 g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST_HI), ==, 0); 594 g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF), ==, 0); 595 g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF_HI), ==, 0); 596 g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), ==, 0); 597 598 /* Check that the address masking is correct */ 599 qtest_writel(s, base + HACE_HASH_SRC, 0xffffffff); 600 g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), ==, expected->src); 601 602 qtest_writel(s, base + HACE_HASH_SRC_HI, 0xffffffff); 603 g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC_HI), 604 ==, expected->src_hi); 605 606 qtest_writel(s, base + HACE_HASH_DIGEST, 0xffffffff); 607 g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), ==, 608 expected->dest); 609 610 qtest_writel(s, base + HACE_HASH_DIGEST_HI, 0xffffffff); 611 g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST_HI), ==, 612 expected->dest_hi); 613 614 qtest_writel(s, base + HACE_HASH_KEY_BUFF, 0xffffffff); 615 g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF), ==, 616 expected->key); 617 618 qtest_writel(s, base + HACE_HASH_KEY_BUFF_HI, 0xffffffff); 619 g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF_HI), ==, 620 expected->key_hi); 621 622 qtest_writel(s, base + HACE_HASH_DATA_LEN, 0xffffffff); 623 g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), ==, 624 expected->len); 625 626 /* Reset to zero */ 627 qtest_writel(s, base + HACE_HASH_SRC, 0); 628 qtest_writel(s, base + HACE_HASH_SRC_HI, 0); 629 qtest_writel(s, base + HACE_HASH_DIGEST, 0); 630 qtest_writel(s, base + HACE_HASH_DIGEST_HI, 0); 631 qtest_writel(s, base + HACE_HASH_KEY_BUFF, 0); 632 qtest_writel(s, base + HACE_HASH_KEY_BUFF_HI, 0); 633 qtest_writel(s, base + HACE_HASH_DATA_LEN, 0); 634 635 /* Check that all bits are now zero */ 636 g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), ==, 0); 637 g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC_HI), ==, 0); 638 g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), ==, 0); 639 g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST_HI), ==, 0); 640 g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF), ==, 0); 641 g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF_HI), ==, 0); 642 g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), ==, 0); 643 644 qtest_quit(s); 645 } 646 647