xref: /qemu/tcg/tci/tcg-target-has.h (revision c334de110ea93108feeddce11bd302146d1520f8)
1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Define target-specific opcode support
4  * Copyright (c) 2009, 2011 Stefan Weil
5  */
6 
7 #ifndef TCG_TARGET_HAS_H
8 #define TCG_TARGET_HAS_H
9 
10 #define TCG_TARGET_HAS_bswap16_i32      1
11 #define TCG_TARGET_HAS_bswap32_i32      1
12 #define TCG_TARGET_HAS_div_i32          1
13 #define TCG_TARGET_HAS_rem_i32          1
14 #define TCG_TARGET_HAS_ext8s_i32        1
15 #define TCG_TARGET_HAS_ext16s_i32       1
16 #define TCG_TARGET_HAS_ext8u_i32        1
17 #define TCG_TARGET_HAS_ext16u_i32       1
18 #define TCG_TARGET_HAS_andc_i32         1
19 #define TCG_TARGET_HAS_deposit_i32      1
20 #define TCG_TARGET_HAS_extract2_i32     0
21 #define TCG_TARGET_HAS_eqv_i32          1
22 #define TCG_TARGET_HAS_nand_i32         1
23 #define TCG_TARGET_HAS_nor_i32          1
24 #define TCG_TARGET_HAS_clz_i32          1
25 #define TCG_TARGET_HAS_ctz_i32          1
26 #define TCG_TARGET_HAS_ctpop_i32        1
27 #define TCG_TARGET_HAS_not_i32          1
28 #define TCG_TARGET_HAS_orc_i32          1
29 #define TCG_TARGET_HAS_rot_i32          1
30 #define TCG_TARGET_HAS_negsetcond_i32   0
31 #define TCG_TARGET_HAS_muls2_i32        1
32 #define TCG_TARGET_HAS_muluh_i32        0
33 #define TCG_TARGET_HAS_mulsh_i32        0
34 #define TCG_TARGET_HAS_qemu_st8_i32     0
35 
36 #if TCG_TARGET_REG_BITS == 64
37 #define TCG_TARGET_HAS_extr_i64_i32     0
38 #define TCG_TARGET_HAS_bswap16_i64      1
39 #define TCG_TARGET_HAS_bswap32_i64      1
40 #define TCG_TARGET_HAS_bswap64_i64      1
41 #define TCG_TARGET_HAS_deposit_i64      1
42 #define TCG_TARGET_HAS_extract2_i64     0
43 #define TCG_TARGET_HAS_div_i64          1
44 #define TCG_TARGET_HAS_rem_i64          1
45 #define TCG_TARGET_HAS_ext8s_i64        1
46 #define TCG_TARGET_HAS_ext16s_i64       1
47 #define TCG_TARGET_HAS_ext32s_i64       1
48 #define TCG_TARGET_HAS_ext8u_i64        1
49 #define TCG_TARGET_HAS_ext16u_i64       1
50 #define TCG_TARGET_HAS_ext32u_i64       1
51 #define TCG_TARGET_HAS_andc_i64         1
52 #define TCG_TARGET_HAS_eqv_i64          1
53 #define TCG_TARGET_HAS_nand_i64         1
54 #define TCG_TARGET_HAS_nor_i64          1
55 #define TCG_TARGET_HAS_clz_i64          1
56 #define TCG_TARGET_HAS_ctz_i64          1
57 #define TCG_TARGET_HAS_ctpop_i64        1
58 #define TCG_TARGET_HAS_not_i64          1
59 #define TCG_TARGET_HAS_orc_i64          1
60 #define TCG_TARGET_HAS_rot_i64          1
61 #define TCG_TARGET_HAS_negsetcond_i64   0
62 #define TCG_TARGET_HAS_muls2_i64        1
63 #define TCG_TARGET_HAS_add2_i32         1
64 #define TCG_TARGET_HAS_sub2_i32         1
65 #define TCG_TARGET_HAS_mulu2_i32        1
66 #define TCG_TARGET_HAS_add2_i64         1
67 #define TCG_TARGET_HAS_sub2_i64         1
68 #define TCG_TARGET_HAS_mulu2_i64        1
69 #define TCG_TARGET_HAS_muluh_i64        0
70 #define TCG_TARGET_HAS_mulsh_i64        0
71 #else
72 #define TCG_TARGET_HAS_mulu2_i32        1
73 #endif /* TCG_TARGET_REG_BITS == 64 */
74 
75 #define TCG_TARGET_HAS_qemu_ldst_i128   0
76 
77 #define TCG_TARGET_HAS_tst              1
78 
79 #define TCG_TARGET_extract_valid(type, ofs, len)   1
80 #define TCG_TARGET_sextract_valid(type, ofs, len)  1
81 
82 #endif
83