xref: /qemu/tcg/tci/tcg-target-has.h (revision 03568c0d539581c6e86263d2fd7396f5a1e25a6b)
1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Define target-specific opcode support
4  * Copyright (c) 2009, 2011 Stefan Weil
5  */
6 
7 #ifndef TCG_TARGET_HAS_H
8 #define TCG_TARGET_HAS_H
9 
10 #define TCG_TARGET_HAS_bswap16_i32      1
11 #define TCG_TARGET_HAS_bswap32_i32      1
12 #define TCG_TARGET_HAS_extract2_i32     0
13 #define TCG_TARGET_HAS_clz_i32          1
14 #define TCG_TARGET_HAS_ctz_i32          1
15 #define TCG_TARGET_HAS_ctpop_i32        1
16 #define TCG_TARGET_HAS_negsetcond_i32   0
17 #define TCG_TARGET_HAS_muls2_i32        1
18 #define TCG_TARGET_HAS_qemu_st8_i32     0
19 
20 #if TCG_TARGET_REG_BITS == 64
21 #define TCG_TARGET_HAS_extr_i64_i32     0
22 #define TCG_TARGET_HAS_bswap16_i64      1
23 #define TCG_TARGET_HAS_bswap32_i64      1
24 #define TCG_TARGET_HAS_bswap64_i64      1
25 #define TCG_TARGET_HAS_extract2_i64     0
26 #define TCG_TARGET_HAS_clz_i64          1
27 #define TCG_TARGET_HAS_ctz_i64          1
28 #define TCG_TARGET_HAS_ctpop_i64        1
29 #define TCG_TARGET_HAS_negsetcond_i64   0
30 #define TCG_TARGET_HAS_muls2_i64        1
31 #define TCG_TARGET_HAS_add2_i32         1
32 #define TCG_TARGET_HAS_sub2_i32         1
33 #define TCG_TARGET_HAS_mulu2_i32        1
34 #define TCG_TARGET_HAS_add2_i64         1
35 #define TCG_TARGET_HAS_sub2_i64         1
36 #define TCG_TARGET_HAS_mulu2_i64        1
37 #else
38 #define TCG_TARGET_HAS_mulu2_i32        1
39 #endif /* TCG_TARGET_REG_BITS == 64 */
40 
41 #define TCG_TARGET_HAS_qemu_ldst_i128   0
42 
43 #define TCG_TARGET_HAS_tst              1
44 
45 #define TCG_TARGET_extract_valid(type, ofs, len)   1
46 #define TCG_TARGET_sextract_valid(type, ofs, len)  1
47 #define TCG_TARGET_deposit_valid(type, ofs, len)   1
48 
49 #endif
50