xref: /qemu/tcg/s390x/tcg-target-reg-bits.h (revision 369081c4558e7e940fa36ce59bf17b2e390f55d3)
1*d46259c0SRichard Henderson /* SPDX-License-Identifier: MIT */
2*d46259c0SRichard Henderson /*
3*d46259c0SRichard Henderson  * Define target-specific register size
4*d46259c0SRichard Henderson  * Copyright (c) 2009 Ulrich Hecht <uli@suse.de>
5*d46259c0SRichard Henderson  */
6*d46259c0SRichard Henderson 
7*d46259c0SRichard Henderson #ifndef TCG_TARGET_REG_BITS_H
8*d46259c0SRichard Henderson #define TCG_TARGET_REG_BITS_H
9*d46259c0SRichard Henderson 
10*d46259c0SRichard Henderson /* We only support generating code for 64-bit mode.  */
11*d46259c0SRichard Henderson #if UINTPTR_MAX == UINT64_MAX
12*d46259c0SRichard Henderson # define TCG_TARGET_REG_BITS 64
13*d46259c0SRichard Henderson #else
14*d46259c0SRichard Henderson # error "unsupported code generation mode"
15*d46259c0SRichard Henderson #endif
16*d46259c0SRichard Henderson 
17*d46259c0SRichard Henderson #endif
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