1*d46259c0SRichard Henderson /* SPDX-License-Identifier: MIT */ 2*d46259c0SRichard Henderson /* 3*d46259c0SRichard Henderson * Define target-specific register size 4*d46259c0SRichard Henderson * Copyright (c) 2018 SiFive, Inc 5*d46259c0SRichard Henderson */ 6*d46259c0SRichard Henderson 7*d46259c0SRichard Henderson #ifndef TCG_TARGET_REG_BITS_H 8*d46259c0SRichard Henderson #define TCG_TARGET_REG_BITS_H 9*d46259c0SRichard Henderson 10*d46259c0SRichard Henderson /* 11*d46259c0SRichard Henderson * We don't support oversize guests. 12*d46259c0SRichard Henderson * Since we will only build tcg once, this in turn requires a 64-bit host. 13*d46259c0SRichard Henderson */ 14*d46259c0SRichard Henderson #if __riscv_xlen != 64 15*d46259c0SRichard Henderson #error "unsupported code generation mode" 16*d46259c0SRichard Henderson #endif 17*d46259c0SRichard Henderson #define TCG_TARGET_REG_BITS 64 18*d46259c0SRichard Henderson 19*d46259c0SRichard Henderson #endif 20