1*fc63a4c5SRichard Henderson /* SPDX-License-Identifier: MIT */ 2*fc63a4c5SRichard Henderson /* 3*fc63a4c5SRichard Henderson * Define RISC-V target-specific operand constraints. 4*fc63a4c5SRichard Henderson * Copyright (c) 2021 Linaro 5*fc63a4c5SRichard Henderson */ 6*fc63a4c5SRichard Henderson 7*fc63a4c5SRichard Henderson /* 8*fc63a4c5SRichard Henderson * Define constraint letters for register sets: 9*fc63a4c5SRichard Henderson * REGS(letter, register_mask) 10*fc63a4c5SRichard Henderson */ 11*fc63a4c5SRichard Henderson REGS('r', ALL_GENERAL_REGS) 12*fc63a4c5SRichard Henderson REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) 13*fc63a4c5SRichard Henderson 14*fc63a4c5SRichard Henderson /* 15*fc63a4c5SRichard Henderson * Define constraint letters for constants: 16*fc63a4c5SRichard Henderson * CONST(letter, TCG_CT_CONST_* bit set) 17*fc63a4c5SRichard Henderson */ 18*fc63a4c5SRichard Henderson CONST('I', TCG_CT_CONST_S12) 19*fc63a4c5SRichard Henderson CONST('N', TCG_CT_CONST_N12) 20*fc63a4c5SRichard Henderson CONST('M', TCG_CT_CONST_M12) 21*fc63a4c5SRichard Henderson CONST('Z', TCG_CT_CONST_ZERO) 22