1fc63a4c5SRichard Henderson /* SPDX-License-Identifier: MIT */ 2fc63a4c5SRichard Henderson /* 3fc63a4c5SRichard Henderson * Define RISC-V target-specific operand constraints. 4fc63a4c5SRichard Henderson * Copyright (c) 2021 Linaro 5fc63a4c5SRichard Henderson */ 6fc63a4c5SRichard Henderson 7fc63a4c5SRichard Henderson /* 8fc63a4c5SRichard Henderson * Define constraint letters for register sets: 9fc63a4c5SRichard Henderson * REGS(letter, register_mask) 10fc63a4c5SRichard Henderson */ 11fc63a4c5SRichard Henderson REGS('r', ALL_GENERAL_REGS) 12*f63e7089SHuang Shiyuan REGS('v', ALL_VECTOR_REGS) 13fc63a4c5SRichard Henderson 14fc63a4c5SRichard Henderson /* 15fc63a4c5SRichard Henderson * Define constraint letters for constants: 16fc63a4c5SRichard Henderson * CONST(letter, TCG_CT_CONST_* bit set) 17fc63a4c5SRichard Henderson */ 18fc63a4c5SRichard Henderson CONST('I', TCG_CT_CONST_S12) 1999f4ec6eSRichard Henderson CONST('J', TCG_CT_CONST_J12) 20fc63a4c5SRichard Henderson CONST('N', TCG_CT_CONST_N12) 21fc63a4c5SRichard Henderson CONST('M', TCG_CT_CONST_M12) 22fc63a4c5SRichard Henderson CONST('Z', TCG_CT_CONST_ZERO) 23