1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef PPC_TCG_TARGET_H 26 #define PPC_TCG_TARGET_H 27 28 #ifdef _ARCH_PPC64 29 # define TCG_TARGET_REG_BITS 64 30 #else 31 # define TCG_TARGET_REG_BITS 32 32 #endif 33 34 #define TCG_TARGET_NB_REGS 64 35 #define TCG_TARGET_INSN_UNIT_SIZE 4 36 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16 37 38 typedef enum { 39 TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3, 40 TCG_REG_R4, TCG_REG_R5, TCG_REG_R6, TCG_REG_R7, 41 TCG_REG_R8, TCG_REG_R9, TCG_REG_R10, TCG_REG_R11, 42 TCG_REG_R12, TCG_REG_R13, TCG_REG_R14, TCG_REG_R15, 43 TCG_REG_R16, TCG_REG_R17, TCG_REG_R18, TCG_REG_R19, 44 TCG_REG_R20, TCG_REG_R21, TCG_REG_R22, TCG_REG_R23, 45 TCG_REG_R24, TCG_REG_R25, TCG_REG_R26, TCG_REG_R27, 46 TCG_REG_R28, TCG_REG_R29, TCG_REG_R30, TCG_REG_R31, 47 48 TCG_REG_V0, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3, 49 TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7, 50 TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11, 51 TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15, 52 TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19, 53 TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23, 54 TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27, 55 TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31, 56 57 TCG_REG_CALL_STACK = TCG_REG_R1, 58 TCG_AREG0 = TCG_REG_R27 59 } TCGReg; 60 61 typedef enum { 62 tcg_isa_base, 63 tcg_isa_2_06, 64 tcg_isa_3_00, 65 } TCGPowerISA; 66 67 extern TCGPowerISA have_isa; 68 extern bool have_altivec; 69 70 #define have_isa_2_06 (have_isa >= tcg_isa_2_06) 71 #define have_isa_3_00 (have_isa >= tcg_isa_3_00) 72 73 /* optional instructions automatically implemented */ 74 #define TCG_TARGET_HAS_ext8u_i32 0 /* andi */ 75 #define TCG_TARGET_HAS_ext16u_i32 0 76 77 /* optional instructions */ 78 #define TCG_TARGET_HAS_div_i32 1 79 #define TCG_TARGET_HAS_rem_i32 0 80 #define TCG_TARGET_HAS_rot_i32 1 81 #define TCG_TARGET_HAS_ext8s_i32 1 82 #define TCG_TARGET_HAS_ext16s_i32 1 83 #define TCG_TARGET_HAS_bswap16_i32 1 84 #define TCG_TARGET_HAS_bswap32_i32 1 85 #define TCG_TARGET_HAS_not_i32 1 86 #define TCG_TARGET_HAS_neg_i32 1 87 #define TCG_TARGET_HAS_andc_i32 1 88 #define TCG_TARGET_HAS_orc_i32 1 89 #define TCG_TARGET_HAS_eqv_i32 1 90 #define TCG_TARGET_HAS_nand_i32 1 91 #define TCG_TARGET_HAS_nor_i32 1 92 #define TCG_TARGET_HAS_clz_i32 1 93 #define TCG_TARGET_HAS_ctz_i32 have_isa_3_00 94 #define TCG_TARGET_HAS_ctpop_i32 have_isa_2_06 95 #define TCG_TARGET_HAS_deposit_i32 1 96 #define TCG_TARGET_HAS_extract_i32 1 97 #define TCG_TARGET_HAS_sextract_i32 0 98 #define TCG_TARGET_HAS_extract2_i32 0 99 #define TCG_TARGET_HAS_movcond_i32 1 100 #define TCG_TARGET_HAS_mulu2_i32 0 101 #define TCG_TARGET_HAS_muls2_i32 0 102 #define TCG_TARGET_HAS_muluh_i32 1 103 #define TCG_TARGET_HAS_mulsh_i32 1 104 #define TCG_TARGET_HAS_goto_ptr 1 105 #define TCG_TARGET_HAS_direct_jump 1 106 107 #if TCG_TARGET_REG_BITS == 64 108 #define TCG_TARGET_HAS_add2_i32 0 109 #define TCG_TARGET_HAS_sub2_i32 0 110 #define TCG_TARGET_HAS_extrl_i64_i32 0 111 #define TCG_TARGET_HAS_extrh_i64_i32 0 112 #define TCG_TARGET_HAS_div_i64 1 113 #define TCG_TARGET_HAS_rem_i64 0 114 #define TCG_TARGET_HAS_rot_i64 1 115 #define TCG_TARGET_HAS_ext8s_i64 1 116 #define TCG_TARGET_HAS_ext16s_i64 1 117 #define TCG_TARGET_HAS_ext32s_i64 1 118 #define TCG_TARGET_HAS_ext8u_i64 0 119 #define TCG_TARGET_HAS_ext16u_i64 0 120 #define TCG_TARGET_HAS_ext32u_i64 0 121 #define TCG_TARGET_HAS_bswap16_i64 1 122 #define TCG_TARGET_HAS_bswap32_i64 1 123 #define TCG_TARGET_HAS_bswap64_i64 1 124 #define TCG_TARGET_HAS_not_i64 1 125 #define TCG_TARGET_HAS_neg_i64 1 126 #define TCG_TARGET_HAS_andc_i64 1 127 #define TCG_TARGET_HAS_orc_i64 1 128 #define TCG_TARGET_HAS_eqv_i64 1 129 #define TCG_TARGET_HAS_nand_i64 1 130 #define TCG_TARGET_HAS_nor_i64 1 131 #define TCG_TARGET_HAS_clz_i64 1 132 #define TCG_TARGET_HAS_ctz_i64 have_isa_3_00 133 #define TCG_TARGET_HAS_ctpop_i64 have_isa_2_06 134 #define TCG_TARGET_HAS_deposit_i64 1 135 #define TCG_TARGET_HAS_extract_i64 1 136 #define TCG_TARGET_HAS_sextract_i64 0 137 #define TCG_TARGET_HAS_extract2_i64 0 138 #define TCG_TARGET_HAS_movcond_i64 1 139 #define TCG_TARGET_HAS_add2_i64 1 140 #define TCG_TARGET_HAS_sub2_i64 1 141 #define TCG_TARGET_HAS_mulu2_i64 0 142 #define TCG_TARGET_HAS_muls2_i64 0 143 #define TCG_TARGET_HAS_muluh_i64 1 144 #define TCG_TARGET_HAS_mulsh_i64 1 145 #endif 146 147 /* 148 * While technically Altivec could support V64, it has no 64-bit store 149 * instruction and substituting two 32-bit stores makes the generated 150 * code quite large. 151 */ 152 #define TCG_TARGET_HAS_v64 0 153 #define TCG_TARGET_HAS_v128 have_altivec 154 #define TCG_TARGET_HAS_v256 0 155 156 #define TCG_TARGET_HAS_andc_vec 1 157 #define TCG_TARGET_HAS_orc_vec 0 158 #define TCG_TARGET_HAS_not_vec 1 159 #define TCG_TARGET_HAS_neg_vec 0 160 #define TCG_TARGET_HAS_abs_vec 0 161 #define TCG_TARGET_HAS_shi_vec 0 162 #define TCG_TARGET_HAS_shs_vec 0 163 #define TCG_TARGET_HAS_shv_vec 0 164 #define TCG_TARGET_HAS_cmp_vec 1 165 #define TCG_TARGET_HAS_mul_vec 0 166 #define TCG_TARGET_HAS_sat_vec 0 167 #define TCG_TARGET_HAS_minmax_vec 0 168 #define TCG_TARGET_HAS_bitsel_vec 0 169 #define TCG_TARGET_HAS_cmpsel_vec 0 170 171 void flush_icache_range(uintptr_t start, uintptr_t stop); 172 void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); 173 174 #define TCG_TARGET_DEFAULT_MO (0) 175 #define TCG_TARGET_HAS_MEMORY_BSWAP 1 176 177 #ifdef CONFIG_SOFTMMU 178 #define TCG_TARGET_NEED_LDST_LABELS 179 #endif 180 #define TCG_TARGET_NEED_POOL_LABELS 181 182 #endif 183