12662e13fSbellard /* 22662e13fSbellard * Tiny Code Generator for QEMU 32662e13fSbellard * 42662e13fSbellard * Copyright (c) 2008 Fabrice Bellard 52662e13fSbellard * 62662e13fSbellard * Permission is hereby granted, free of charge, to any person obtaining a copy 72662e13fSbellard * of this software and associated documentation files (the "Software"), to deal 82662e13fSbellard * in the Software without restriction, including without limitation the rights 92662e13fSbellard * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 102662e13fSbellard * copies of the Software, and to permit persons to whom the Software is 112662e13fSbellard * furnished to do so, subject to the following conditions: 122662e13fSbellard * 132662e13fSbellard * The above copyright notice and this permission notice shall be included in 142662e13fSbellard * all copies or substantial portions of the Software. 152662e13fSbellard * 162662e13fSbellard * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 172662e13fSbellard * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 182662e13fSbellard * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 192662e13fSbellard * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 202662e13fSbellard * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 212662e13fSbellard * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 222662e13fSbellard * THE SOFTWARE. 232662e13fSbellard */ 242662e13fSbellard #define TCG_TARGET_PPC 1 252662e13fSbellard 262662e13fSbellard #define TCG_TARGET_REG_BITS 32 272662e13fSbellard #define TCG_TARGET_WORDS_BIGENDIAN 282662e13fSbellard #define TCG_TARGET_NB_REGS 32 292662e13fSbellard 302662e13fSbellard enum { 312662e13fSbellard TCG_REG_R0 = 0, 322662e13fSbellard TCG_REG_R1, 332662e13fSbellard TCG_REG_R2, 342662e13fSbellard TCG_REG_R3, 352662e13fSbellard TCG_REG_R4, 362662e13fSbellard TCG_REG_R5, 372662e13fSbellard TCG_REG_R6, 382662e13fSbellard TCG_REG_R7, 392662e13fSbellard TCG_REG_R8, 402662e13fSbellard TCG_REG_R9, 412662e13fSbellard TCG_REG_R10, 422662e13fSbellard TCG_REG_R11, 432662e13fSbellard TCG_REG_R12, 442662e13fSbellard TCG_REG_R13, 452662e13fSbellard TCG_REG_R14, 462662e13fSbellard TCG_REG_R15, 472662e13fSbellard TCG_REG_R16, 482662e13fSbellard TCG_REG_R17, 492662e13fSbellard TCG_REG_R18, 502662e13fSbellard TCG_REG_R19, 512662e13fSbellard TCG_REG_R20, 522662e13fSbellard TCG_REG_R21, 532662e13fSbellard TCG_REG_R22, 542662e13fSbellard TCG_REG_R23, 552662e13fSbellard TCG_REG_R24, 562662e13fSbellard TCG_REG_R25, 572662e13fSbellard TCG_REG_R26, 582662e13fSbellard TCG_REG_R27, 592662e13fSbellard TCG_REG_R28, 602662e13fSbellard TCG_REG_R29, 612662e13fSbellard TCG_REG_R30, 622662e13fSbellard TCG_REG_R31 632662e13fSbellard }; 642662e13fSbellard 652662e13fSbellard /* used for function call generation */ 662662e13fSbellard #define TCG_REG_CALL_STACK TCG_REG_R1 672662e13fSbellard #define TCG_TARGET_STACK_ALIGN 16 682662e13fSbellard #define TCG_TARGET_CALL_STACK_OFFSET 8 692662e13fSbellard #define TCG_TARGET_CALL_ALIGN_ARGS 1 702662e13fSbellard 712662e13fSbellard /* optional instructions */ 722662e13fSbellard #define TCG_TARGET_HAS_neg_i32 7377b73de6Smalc #define TCG_TARGET_HAS_div_i32 742662e13fSbellard 752662e13fSbellard #define TCG_AREG0 TCG_REG_R27 762662e13fSbellard #define TCG_AREG1 TCG_REG_R24 772662e13fSbellard #define TCG_AREG2 TCG_REG_R25 782662e13fSbellard #define TCG_AREG3 TCG_REG_R26 792662e13fSbellard 802662e13fSbellard /* taken directly from tcg-dyngen.c */ 812662e13fSbellard #define MIN_CACHE_LINE_SIZE 8 /* conservative value */ 822662e13fSbellard 832662e13fSbellard static inline void flush_icache_range(unsigned long start, unsigned long stop) 842662e13fSbellard { 852662e13fSbellard unsigned long p; 862662e13fSbellard 872662e13fSbellard start &= ~(MIN_CACHE_LINE_SIZE - 1); 882662e13fSbellard stop = (stop + MIN_CACHE_LINE_SIZE - 1) & ~(MIN_CACHE_LINE_SIZE - 1); 892662e13fSbellard 902662e13fSbellard for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) { 912662e13fSbellard asm volatile ("dcbst 0,%0" : : "r"(p) : "memory"); 922662e13fSbellard } 932662e13fSbellard asm volatile ("sync" : : : "memory"); 942662e13fSbellard for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) { 952662e13fSbellard asm volatile ("icbi 0,%0" : : "r"(p) : "memory"); 962662e13fSbellard } 972662e13fSbellard asm volatile ("sync" : : : "memory"); 982662e13fSbellard asm volatile ("isync" : : : "memory"); 992662e13fSbellard } 100