xref: /qemu/tcg/loongarch64/tcg-target-has.h (revision 6d1a2365eaee0603347fd2fabd89a8dc935c8ac7)
1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Define target-specific opcode support
4  * Copyright (c) 2021 WANG Xuerui <git@xen0n.name>
5  */
6 
7 #ifndef TCG_TARGET_HAS_H
8 #define TCG_TARGET_HAS_H
9 
10 #include "host/cpuinfo.h"
11 
12 /* optional instructions */
13 #define TCG_TARGET_HAS_negsetcond_i32   0
14 #define TCG_TARGET_HAS_rem_i32          1
15 #define TCG_TARGET_HAS_div2_i32         0
16 #define TCG_TARGET_HAS_rot_i32          1
17 #define TCG_TARGET_HAS_extract2_i32     0
18 #define TCG_TARGET_HAS_add2_i32         0
19 #define TCG_TARGET_HAS_sub2_i32         0
20 #define TCG_TARGET_HAS_mulu2_i32        0
21 #define TCG_TARGET_HAS_muls2_i32        0
22 #define TCG_TARGET_HAS_bswap16_i32      1
23 #define TCG_TARGET_HAS_bswap32_i32      1
24 #define TCG_TARGET_HAS_clz_i32          1
25 #define TCG_TARGET_HAS_ctz_i32          1
26 #define TCG_TARGET_HAS_ctpop_i32        0
27 #define TCG_TARGET_HAS_qemu_st8_i32     0
28 
29 /* 64-bit operations */
30 #define TCG_TARGET_HAS_negsetcond_i64   0
31 #define TCG_TARGET_HAS_rem_i64          1
32 #define TCG_TARGET_HAS_div2_i64         0
33 #define TCG_TARGET_HAS_rot_i64          1
34 #define TCG_TARGET_HAS_extract2_i64     0
35 #define TCG_TARGET_HAS_extr_i64_i32     1
36 #define TCG_TARGET_HAS_bswap16_i64      1
37 #define TCG_TARGET_HAS_bswap32_i64      1
38 #define TCG_TARGET_HAS_bswap64_i64      1
39 #define TCG_TARGET_HAS_clz_i64          1
40 #define TCG_TARGET_HAS_ctz_i64          1
41 #define TCG_TARGET_HAS_ctpop_i64        0
42 #define TCG_TARGET_HAS_add2_i64         0
43 #define TCG_TARGET_HAS_sub2_i64         0
44 #define TCG_TARGET_HAS_mulu2_i64        0
45 #define TCG_TARGET_HAS_muls2_i64        0
46 
47 #define TCG_TARGET_HAS_qemu_ldst_i128   (cpuinfo & CPUINFO_LSX)
48 
49 #define TCG_TARGET_HAS_tst              0
50 
51 #define TCG_TARGET_HAS_v64              (cpuinfo & CPUINFO_LSX)
52 #define TCG_TARGET_HAS_v128             (cpuinfo & CPUINFO_LSX)
53 #define TCG_TARGET_HAS_v256             (cpuinfo & CPUINFO_LASX)
54 
55 #define TCG_TARGET_HAS_not_vec          1
56 #define TCG_TARGET_HAS_neg_vec          1
57 #define TCG_TARGET_HAS_abs_vec          0
58 #define TCG_TARGET_HAS_andc_vec         1
59 #define TCG_TARGET_HAS_orc_vec          1
60 #define TCG_TARGET_HAS_nand_vec         0
61 #define TCG_TARGET_HAS_nor_vec          1
62 #define TCG_TARGET_HAS_eqv_vec          0
63 #define TCG_TARGET_HAS_mul_vec          1
64 #define TCG_TARGET_HAS_shi_vec          1
65 #define TCG_TARGET_HAS_shs_vec          0
66 #define TCG_TARGET_HAS_shv_vec          1
67 #define TCG_TARGET_HAS_roti_vec         1
68 #define TCG_TARGET_HAS_rots_vec         0
69 #define TCG_TARGET_HAS_rotv_vec         1
70 #define TCG_TARGET_HAS_sat_vec          1
71 #define TCG_TARGET_HAS_minmax_vec       1
72 #define TCG_TARGET_HAS_bitsel_vec       1
73 #define TCG_TARGET_HAS_cmpsel_vec       0
74 #define TCG_TARGET_HAS_tst_vec          0
75 
76 #define TCG_TARGET_extract_valid(type, ofs, len)   1
77 #define TCG_TARGET_deposit_valid(type, ofs, len)   1
78 
79 static inline bool
80 tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len)
81 {
82     if (type == TCG_TYPE_I64 && ofs + len == 32) {
83         return true;
84     }
85     return ofs == 0 && (len == 8 || len == 16);
86 }
87 #define TCG_TARGET_sextract_valid  tcg_target_sextract_valid
88 
89 #endif
90