1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Define target-specific opcode support 4 * Copyright (c) 2021 WANG Xuerui <git@xen0n.name> 5 */ 6 7 #ifndef TCG_TARGET_HAS_H 8 #define TCG_TARGET_HAS_H 9 10 #include "host/cpuinfo.h" 11 12 /* optional instructions */ 13 #define TCG_TARGET_HAS_negsetcond_i32 0 14 #define TCG_TARGET_HAS_div_i32 1 15 #define TCG_TARGET_HAS_rem_i32 1 16 #define TCG_TARGET_HAS_div2_i32 0 17 #define TCG_TARGET_HAS_rot_i32 1 18 #define TCG_TARGET_HAS_extract2_i32 0 19 #define TCG_TARGET_HAS_add2_i32 0 20 #define TCG_TARGET_HAS_sub2_i32 0 21 #define TCG_TARGET_HAS_mulu2_i32 0 22 #define TCG_TARGET_HAS_muls2_i32 0 23 #define TCG_TARGET_HAS_muluh_i32 1 24 #define TCG_TARGET_HAS_mulsh_i32 1 25 #define TCG_TARGET_HAS_ext8s_i32 1 26 #define TCG_TARGET_HAS_ext16s_i32 1 27 #define TCG_TARGET_HAS_ext8u_i32 1 28 #define TCG_TARGET_HAS_ext16u_i32 1 29 #define TCG_TARGET_HAS_bswap16_i32 1 30 #define TCG_TARGET_HAS_bswap32_i32 1 31 #define TCG_TARGET_HAS_not_i32 1 32 #define TCG_TARGET_HAS_andc_i32 1 33 #define TCG_TARGET_HAS_orc_i32 1 34 #define TCG_TARGET_HAS_eqv_i32 0 35 #define TCG_TARGET_HAS_nand_i32 0 36 #define TCG_TARGET_HAS_nor_i32 1 37 #define TCG_TARGET_HAS_clz_i32 1 38 #define TCG_TARGET_HAS_ctz_i32 1 39 #define TCG_TARGET_HAS_ctpop_i32 0 40 #define TCG_TARGET_HAS_brcond2 0 41 #define TCG_TARGET_HAS_setcond2 0 42 #define TCG_TARGET_HAS_qemu_st8_i32 0 43 44 /* 64-bit operations */ 45 #define TCG_TARGET_HAS_negsetcond_i64 0 46 #define TCG_TARGET_HAS_div_i64 1 47 #define TCG_TARGET_HAS_rem_i64 1 48 #define TCG_TARGET_HAS_div2_i64 0 49 #define TCG_TARGET_HAS_rot_i64 1 50 #define TCG_TARGET_HAS_extract2_i64 0 51 #define TCG_TARGET_HAS_extr_i64_i32 1 52 #define TCG_TARGET_HAS_ext8s_i64 1 53 #define TCG_TARGET_HAS_ext16s_i64 1 54 #define TCG_TARGET_HAS_ext32s_i64 1 55 #define TCG_TARGET_HAS_ext8u_i64 1 56 #define TCG_TARGET_HAS_ext16u_i64 1 57 #define TCG_TARGET_HAS_ext32u_i64 1 58 #define TCG_TARGET_HAS_bswap16_i64 1 59 #define TCG_TARGET_HAS_bswap32_i64 1 60 #define TCG_TARGET_HAS_bswap64_i64 1 61 #define TCG_TARGET_HAS_not_i64 1 62 #define TCG_TARGET_HAS_andc_i64 1 63 #define TCG_TARGET_HAS_orc_i64 1 64 #define TCG_TARGET_HAS_eqv_i64 0 65 #define TCG_TARGET_HAS_nand_i64 0 66 #define TCG_TARGET_HAS_nor_i64 1 67 #define TCG_TARGET_HAS_clz_i64 1 68 #define TCG_TARGET_HAS_ctz_i64 1 69 #define TCG_TARGET_HAS_ctpop_i64 0 70 #define TCG_TARGET_HAS_add2_i64 0 71 #define TCG_TARGET_HAS_sub2_i64 0 72 #define TCG_TARGET_HAS_mulu2_i64 0 73 #define TCG_TARGET_HAS_muls2_i64 0 74 #define TCG_TARGET_HAS_muluh_i64 1 75 #define TCG_TARGET_HAS_mulsh_i64 1 76 77 #define TCG_TARGET_HAS_qemu_ldst_i128 (cpuinfo & CPUINFO_LSX) 78 79 #define TCG_TARGET_HAS_tst 0 80 81 #define TCG_TARGET_HAS_v64 (cpuinfo & CPUINFO_LSX) 82 #define TCG_TARGET_HAS_v128 (cpuinfo & CPUINFO_LSX) 83 #define TCG_TARGET_HAS_v256 (cpuinfo & CPUINFO_LASX) 84 85 #define TCG_TARGET_HAS_not_vec 1 86 #define TCG_TARGET_HAS_neg_vec 1 87 #define TCG_TARGET_HAS_abs_vec 0 88 #define TCG_TARGET_HAS_andc_vec 1 89 #define TCG_TARGET_HAS_orc_vec 1 90 #define TCG_TARGET_HAS_nand_vec 0 91 #define TCG_TARGET_HAS_nor_vec 1 92 #define TCG_TARGET_HAS_eqv_vec 0 93 #define TCG_TARGET_HAS_mul_vec 1 94 #define TCG_TARGET_HAS_shi_vec 1 95 #define TCG_TARGET_HAS_shs_vec 0 96 #define TCG_TARGET_HAS_shv_vec 1 97 #define TCG_TARGET_HAS_roti_vec 1 98 #define TCG_TARGET_HAS_rots_vec 0 99 #define TCG_TARGET_HAS_rotv_vec 1 100 #define TCG_TARGET_HAS_sat_vec 1 101 #define TCG_TARGET_HAS_minmax_vec 1 102 #define TCG_TARGET_HAS_bitsel_vec 1 103 #define TCG_TARGET_HAS_cmpsel_vec 0 104 #define TCG_TARGET_HAS_tst_vec 0 105 106 #define TCG_TARGET_extract_valid(type, ofs, len) 1 107 #define TCG_TARGET_deposit_valid(type, ofs, len) 1 108 109 static inline bool 110 tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len) 111 { 112 if (type == TCG_TYPE_I64 && ofs + len == 32) { 113 return true; 114 } 115 return ofs == 0 && (len == 8 || len == 16); 116 } 117 #define TCG_TARGET_sextract_valid tcg_target_sextract_valid 118 119 #endif 120