xref: /qemu/tcg/i386/tcg-target.h (revision 513823e7521a09ed7ad1e32e6454bac3b2cbf52d)
1 /*
2  * Tiny Code Generator for QEMU
3  *
4  * Copyright (c) 2008 Fabrice Bellard
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to deal
8  * in the Software without restriction, including without limitation the rights
9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10  * copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22  * THE SOFTWARE.
23  */
24 
25 #ifndef I386_TCG_TARGET_H
26 #define I386_TCG_TARGET_H
27 
28 #define TCG_TARGET_INSN_UNIT_SIZE  1
29 
30 #ifdef __x86_64__
31 # define TCG_TARGET_NB_REGS   32
32 # define MAX_CODE_GEN_BUFFER_SIZE  (2 * GiB)
33 #else
34 # define TCG_TARGET_NB_REGS   24
35 # define MAX_CODE_GEN_BUFFER_SIZE  UINT32_MAX
36 #endif
37 
38 typedef enum {
39     TCG_REG_EAX = 0,
40     TCG_REG_ECX,
41     TCG_REG_EDX,
42     TCG_REG_EBX,
43     TCG_REG_ESP,
44     TCG_REG_EBP,
45     TCG_REG_ESI,
46     TCG_REG_EDI,
47 
48     /* 64-bit registers; always define the symbols to avoid
49        too much if-deffing.  */
50     TCG_REG_R8,
51     TCG_REG_R9,
52     TCG_REG_R10,
53     TCG_REG_R11,
54     TCG_REG_R12,
55     TCG_REG_R13,
56     TCG_REG_R14,
57     TCG_REG_R15,
58 
59     TCG_REG_XMM0,
60     TCG_REG_XMM1,
61     TCG_REG_XMM2,
62     TCG_REG_XMM3,
63     TCG_REG_XMM4,
64     TCG_REG_XMM5,
65     TCG_REG_XMM6,
66     TCG_REG_XMM7,
67 
68     /* 64-bit registers; likewise always define.  */
69     TCG_REG_XMM8,
70     TCG_REG_XMM9,
71     TCG_REG_XMM10,
72     TCG_REG_XMM11,
73     TCG_REG_XMM12,
74     TCG_REG_XMM13,
75     TCG_REG_XMM14,
76     TCG_REG_XMM15,
77 
78     TCG_REG_RAX = TCG_REG_EAX,
79     TCG_REG_RCX = TCG_REG_ECX,
80     TCG_REG_RDX = TCG_REG_EDX,
81     TCG_REG_RBX = TCG_REG_EBX,
82     TCG_REG_RSP = TCG_REG_ESP,
83     TCG_REG_RBP = TCG_REG_EBP,
84     TCG_REG_RSI = TCG_REG_ESI,
85     TCG_REG_RDI = TCG_REG_EDI,
86 
87     TCG_AREG0 = TCG_REG_EBP,
88     TCG_REG_CALL_STACK = TCG_REG_ESP
89 } TCGReg;
90 
91 #endif
92