1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Define target-specific memory model 4 * Copyright (c) 2008 Fabrice Bellard 5 */ 6 7 #ifndef TCG_TARGET_MO_H 8 #define TCG_TARGET_MO_H 9 10 /* 11 * This defines the natural memory order supported by this architecture 12 * before guarantees made by various barrier instructions. 13 * 14 * The x86 has a pretty strong memory ordering which only really 15 * allows for some stores to be re-ordered after loads. 16 */ 17 #define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) 18 19 #endif 20