xref: /qemu/tcg/arm/tcg-target.h (revision 513823e7521a09ed7ad1e32e6454bac3b2cbf52d)
1 /*
2  * Tiny Code Generator for QEMU
3  *
4  * Copyright (c) 2008 Fabrice Bellard
5  * Copyright (c) 2008 Andrzej Zaborowski
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a copy
8  * of this software and associated documentation files (the "Software"), to deal
9  * in the Software without restriction, including without limitation the rights
10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11  * copies of the Software, and to permit persons to whom the Software is
12  * furnished to do so, subject to the following conditions:
13  *
14  * The above copyright notice and this permission notice shall be included in
15  * all copies or substantial portions of the Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23  * THE SOFTWARE.
24  */
25 
26 #ifndef ARM_TCG_TARGET_H
27 #define ARM_TCG_TARGET_H
28 
29 #define TCG_TARGET_INSN_UNIT_SIZE 4
30 #define MAX_CODE_GEN_BUFFER_SIZE  UINT32_MAX
31 
32 typedef enum {
33     TCG_REG_R0 = 0,
34     TCG_REG_R1,
35     TCG_REG_R2,
36     TCG_REG_R3,
37     TCG_REG_R4,
38     TCG_REG_R5,
39     TCG_REG_R6,
40     TCG_REG_R7,
41     TCG_REG_R8,
42     TCG_REG_R9,
43     TCG_REG_R10,
44     TCG_REG_R11,
45     TCG_REG_R12,
46     TCG_REG_R13,
47     TCG_REG_R14,
48     TCG_REG_PC,
49 
50     TCG_REG_Q0,
51     TCG_REG_Q1,
52     TCG_REG_Q2,
53     TCG_REG_Q3,
54     TCG_REG_Q4,
55     TCG_REG_Q5,
56     TCG_REG_Q6,
57     TCG_REG_Q7,
58     TCG_REG_Q8,
59     TCG_REG_Q9,
60     TCG_REG_Q10,
61     TCG_REG_Q11,
62     TCG_REG_Q12,
63     TCG_REG_Q13,
64     TCG_REG_Q14,
65     TCG_REG_Q15,
66 
67     TCG_AREG0 = TCG_REG_R6,
68     TCG_REG_CALL_STACK = TCG_REG_R13,
69 } TCGReg;
70 
71 #define TCG_TARGET_NB_REGS 32
72 
73 #endif
74