13440d583SRichard Henderson /* SPDX-License-Identifier: MIT */ 23440d583SRichard Henderson /* 33440d583SRichard Henderson * Define Arm target-specific operand constraints. 43440d583SRichard Henderson * Copyright (c) 2021 Linaro 53440d583SRichard Henderson */ 63440d583SRichard Henderson 73440d583SRichard Henderson /* 83440d583SRichard Henderson * Define constraint letters for register sets: 93440d583SRichard Henderson * REGS(letter, register_mask) 103440d583SRichard Henderson */ 113440d583SRichard Henderson REGS('r', ALL_GENERAL_REGS) 123440d583SRichard Henderson REGS('l', ALL_QLOAD_REGS) 133440d583SRichard Henderson REGS('s', ALL_QSTORE_REGS) 14*000cf477SRichard Henderson REGS('w', ALL_VECTOR_REGS) 153440d583SRichard Henderson 163440d583SRichard Henderson /* 173440d583SRichard Henderson * Define constraint letters for constants: 183440d583SRichard Henderson * CONST(letter, TCG_CT_CONST_* bit set) 193440d583SRichard Henderson */ 203440d583SRichard Henderson CONST('I', TCG_CT_CONST_ARM) 213440d583SRichard Henderson CONST('K', TCG_CT_CONST_INV) 223440d583SRichard Henderson CONST('N', TCG_CT_CONST_NEG) 233440d583SRichard Henderson CONST('Z', TCG_CT_CONST_ZERO) 24