1 /* 2 * Initial TCG Implementation for aarch64 3 * 4 * Copyright (c) 2013 Huawei Technologies Duesseldorf GmbH 5 * Written by Claudio Fontana 6 * 7 * This work is licensed under the terms of the GNU GPL, version 2 or 8 * (at your option) any later version. 9 * 10 * See the COPYING file in the top-level directory for details. 11 */ 12 13 #ifndef AARCH64_TCG_TARGET_H 14 #define AARCH64_TCG_TARGET_H 15 16 #define TCG_TARGET_INSN_UNIT_SIZE 4 17 #define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) 18 19 typedef enum { 20 TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3, 21 TCG_REG_X4, TCG_REG_X5, TCG_REG_X6, TCG_REG_X7, 22 TCG_REG_X8, TCG_REG_X9, TCG_REG_X10, TCG_REG_X11, 23 TCG_REG_X12, TCG_REG_X13, TCG_REG_X14, TCG_REG_X15, 24 TCG_REG_X16, TCG_REG_X17, TCG_REG_X18, TCG_REG_X19, 25 TCG_REG_X20, TCG_REG_X21, TCG_REG_X22, TCG_REG_X23, 26 TCG_REG_X24, TCG_REG_X25, TCG_REG_X26, TCG_REG_X27, 27 TCG_REG_X28, TCG_REG_X29, TCG_REG_X30, 28 29 /* X31 is either the stack pointer or zero, depending on context. */ 30 TCG_REG_SP = 31, 31 TCG_REG_XZR = 31, 32 33 TCG_REG_V0 = 32, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3, 34 TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7, 35 TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11, 36 TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15, 37 TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19, 38 TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23, 39 TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27, 40 TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31, 41 42 /* Aliases. */ 43 TCG_REG_FP = TCG_REG_X29, 44 TCG_REG_LR = TCG_REG_X30, 45 TCG_AREG0 = TCG_REG_X19, 46 } TCGReg; 47 48 #define TCG_REG_ZERO TCG_REG_XZR 49 50 #define TCG_TARGET_NB_REGS 64 51 52 #endif /* AARCH64_TCG_TARGET_H */ 53