1 /* 2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * * Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * * Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * * Neither the name of the Open Source and Linux Lab nor the 13 * names of its contributors may be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include "qemu/osdep.h" 29 #include "cpu.h" 30 #include "exec/helper-proto.h" 31 #include "exec/page-protection.h" 32 #include "qemu/host-utils.h" 33 #include "exec/exec-all.h" 34 #include "system/memory.h" 35 #include "qemu/atomic.h" 36 #include "qemu/timer.h" 37 38 #ifndef CONFIG_USER_ONLY 39 40 void HELPER(update_ccount)(CPUXtensaState *env) 41 { 42 XtensaCPU *cpu = env_archcpu(env); 43 uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 44 45 env->ccount_time = now; 46 env->sregs[CCOUNT] = env->ccount_base + 47 (uint32_t)clock_ns_to_ticks(cpu->clock, now - env->time_base); 48 } 49 50 void HELPER(wsr_ccount)(CPUXtensaState *env, uint32_t v) 51 { 52 int i; 53 54 HELPER(update_ccount)(env); 55 env->ccount_base += v - env->sregs[CCOUNT]; 56 for (i = 0; i < env->config->nccompare; ++i) { 57 HELPER(update_ccompare)(env, i); 58 } 59 } 60 61 void HELPER(update_ccompare)(CPUXtensaState *env, uint32_t i) 62 { 63 XtensaCPU *cpu = env_archcpu(env); 64 uint64_t dcc; 65 66 qatomic_and(&env->sregs[INTSET], 67 ~(1u << env->config->timerint[i])); 68 HELPER(update_ccount)(env); 69 dcc = (uint64_t)(env->sregs[CCOMPARE + i] - env->sregs[CCOUNT] - 1) + 1; 70 timer_mod(env->ccompare[i].timer, 71 env->ccount_time + clock_ticks_to_ns(cpu->clock, dcc)); 72 env->yield_needed = 1; 73 } 74 75 /*! 76 * Check vaddr accessibility/cache attributes and raise an exception if 77 * specified by the ATOMCTL SR. 78 * 79 * Note: local memory exclusion is not implemented 80 */ 81 void HELPER(check_atomctl)(CPUXtensaState *env, uint32_t pc, uint32_t vaddr) 82 { 83 uint32_t paddr, page_size, access; 84 uint32_t atomctl = env->sregs[ATOMCTL]; 85 int rc = xtensa_get_physical_addr(env, true, vaddr, 1, 86 xtensa_get_cring(env), &paddr, &page_size, &access); 87 88 /* 89 * s32c1i never causes LOAD_PROHIBITED_CAUSE exceptions, 90 * see opcode description in the ISA 91 */ 92 if (rc == 0 && 93 (access & (PAGE_READ | PAGE_WRITE)) != (PAGE_READ | PAGE_WRITE)) { 94 rc = STORE_PROHIBITED_CAUSE; 95 } 96 97 if (rc) { 98 HELPER(exception_cause_vaddr)(env, pc, rc, vaddr); 99 } 100 101 /* 102 * When data cache is not configured use ATOMCTL bypass field. 103 * See ISA, 4.3.12.4 The Atomic Operation Control Register (ATOMCTL) 104 * under the Conditional Store Option. 105 */ 106 if (!xtensa_option_enabled(env->config, XTENSA_OPTION_DCACHE)) { 107 access = PAGE_CACHE_BYPASS; 108 } 109 110 switch (access & PAGE_CACHE_MASK) { 111 case PAGE_CACHE_WB: 112 atomctl >>= 2; 113 /* fall through */ 114 case PAGE_CACHE_WT: 115 atomctl >>= 2; 116 /* fall through */ 117 case PAGE_CACHE_BYPASS: 118 if ((atomctl & 0x3) == 0) { 119 HELPER(exception_cause_vaddr)(env, pc, 120 LOAD_STORE_ERROR_CAUSE, vaddr); 121 } 122 break; 123 124 case PAGE_CACHE_ISOLATE: 125 HELPER(exception_cause_vaddr)(env, pc, 126 LOAD_STORE_ERROR_CAUSE, vaddr); 127 break; 128 129 default: 130 break; 131 } 132 } 133 134 void HELPER(check_exclusive)(CPUXtensaState *env, uint32_t pc, uint32_t vaddr, 135 uint32_t is_write) 136 { 137 uint32_t paddr, page_size, access; 138 uint32_t atomctl = env->sregs[ATOMCTL]; 139 int rc = xtensa_get_physical_addr(env, true, vaddr, is_write, 140 xtensa_get_cring(env), &paddr, 141 &page_size, &access); 142 143 if (rc) { 144 HELPER(exception_cause_vaddr)(env, pc, rc, vaddr); 145 } 146 147 /* When data cache is not configured use ATOMCTL bypass field. */ 148 if (!xtensa_option_enabled(env->config, XTENSA_OPTION_DCACHE)) { 149 access = PAGE_CACHE_BYPASS; 150 } 151 152 switch (access & PAGE_CACHE_MASK) { 153 case PAGE_CACHE_WB: 154 atomctl >>= 2; 155 /* fall through */ 156 case PAGE_CACHE_WT: 157 atomctl >>= 2; 158 /* fall through */ 159 case PAGE_CACHE_BYPASS: 160 if ((atomctl & 0x3) == 0) { 161 HELPER(exception_cause_vaddr)(env, pc, 162 EXCLUSIVE_ERROR_CAUSE, vaddr); 163 } 164 break; 165 166 case PAGE_CACHE_ISOLATE: 167 HELPER(exception_cause_vaddr)(env, pc, 168 LOAD_STORE_ERROR_CAUSE, vaddr); 169 break; 170 171 default: 172 break; 173 } 174 } 175 176 void HELPER(wsr_memctl)(CPUXtensaState *env, uint32_t v) 177 { 178 if (xtensa_option_enabled(env->config, XTENSA_OPTION_ICACHE)) { 179 if (extract32(v, MEMCTL_IUSEWAYS_SHIFT, MEMCTL_IUSEWAYS_LEN) > 180 env->config->icache_ways) { 181 deposit32(v, MEMCTL_IUSEWAYS_SHIFT, MEMCTL_IUSEWAYS_LEN, 182 env->config->icache_ways); 183 } 184 } 185 if (xtensa_option_enabled(env->config, XTENSA_OPTION_DCACHE)) { 186 if (extract32(v, MEMCTL_DUSEWAYS_SHIFT, MEMCTL_DUSEWAYS_LEN) > 187 env->config->dcache_ways) { 188 deposit32(v, MEMCTL_DUSEWAYS_SHIFT, MEMCTL_DUSEWAYS_LEN, 189 env->config->dcache_ways); 190 } 191 if (extract32(v, MEMCTL_DALLOCWAYS_SHIFT, MEMCTL_DALLOCWAYS_LEN) > 192 env->config->dcache_ways) { 193 deposit32(v, MEMCTL_DALLOCWAYS_SHIFT, MEMCTL_DALLOCWAYS_LEN, 194 env->config->dcache_ways); 195 } 196 } 197 env->sregs[MEMCTL] = v & env->config->memctl_mask; 198 } 199 200 #endif 201 202 uint32_t HELPER(rer)(CPUXtensaState *env, uint32_t addr) 203 { 204 #ifndef CONFIG_USER_ONLY 205 return address_space_ldl(env->address_space_er, addr, 206 MEMTXATTRS_UNSPECIFIED, NULL); 207 #else 208 return 0; 209 #endif 210 } 211 212 void HELPER(wer)(CPUXtensaState *env, uint32_t data, uint32_t addr) 213 { 214 #ifndef CONFIG_USER_ONLY 215 address_space_stl(env->address_space_er, addr, data, 216 MEMTXATTRS_UNSPECIFIED, NULL); 217 #endif 218 } 219