1 /* 2 * Copyright (c) 2011 - 2019, Max Filippov, Open Source and Linux Lab. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * * Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * * Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * * Neither the name of the Open Source and Linux Lab nor the 13 * names of its contributors may be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include "qemu/osdep.h" 29 #include "qemu/log.h" 30 #include "qemu/qemu-print.h" 31 #include "qemu/units.h" 32 #include "cpu.h" 33 #include "exec/helper-proto.h" 34 #include "qemu/host-utils.h" 35 #include "exec/cputlb.h" 36 #include "exec/exec-all.h" 37 #include "exec/page-protection.h" 38 39 #define XTENSA_MPU_SEGMENT_MASK 0x0000001f 40 #define XTENSA_MPU_ACC_RIGHTS_MASK 0x00000f00 41 #define XTENSA_MPU_ACC_RIGHTS_SHIFT 8 42 #define XTENSA_MPU_MEM_TYPE_MASK 0x001ff000 43 #define XTENSA_MPU_MEM_TYPE_SHIFT 12 44 #define XTENSA_MPU_ATTR_MASK 0x001fff00 45 46 #define XTENSA_MPU_PROBE_B 0x40000000 47 #define XTENSA_MPU_PROBE_V 0x80000000 48 49 #define XTENSA_MPU_SYSTEM_TYPE_DEVICE 0x0001 50 #define XTENSA_MPU_SYSTEM_TYPE_NC 0x0002 51 #define XTENSA_MPU_SYSTEM_TYPE_C 0x0003 52 #define XTENSA_MPU_SYSTEM_TYPE_MASK 0x0003 53 54 #define XTENSA_MPU_TYPE_SYS_C 0x0010 55 #define XTENSA_MPU_TYPE_SYS_W 0x0020 56 #define XTENSA_MPU_TYPE_SYS_R 0x0040 57 #define XTENSA_MPU_TYPE_CPU_C 0x0100 58 #define XTENSA_MPU_TYPE_CPU_W 0x0200 59 #define XTENSA_MPU_TYPE_CPU_R 0x0400 60 #define XTENSA_MPU_TYPE_CPU_CACHE 0x0800 61 #define XTENSA_MPU_TYPE_B 0x1000 62 #define XTENSA_MPU_TYPE_INT 0x2000 63 64 void HELPER(itlb_hit_test)(CPUXtensaState *env, uint32_t vaddr) 65 { 66 /* 67 * Probe the memory; we don't care about the result but 68 * only the side-effects (ie any MMU or other exception) 69 */ 70 probe_access(env, vaddr, 1, MMU_INST_FETCH, 71 cpu_mmu_index(env_cpu(env), true), GETPC()); 72 } 73 74 void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v) 75 { 76 v = (v & 0xffffff00) | 0x1; 77 if (v != env->sregs[RASID]) { 78 env->sregs[RASID] = v; 79 tlb_flush(env_cpu(env)); 80 } 81 } 82 83 static uint32_t get_page_size(const CPUXtensaState *env, 84 bool dtlb, uint32_t way) 85 { 86 uint32_t tlbcfg = env->sregs[dtlb ? DTLBCFG : ITLBCFG]; 87 88 switch (way) { 89 case 4: 90 return (tlbcfg >> 16) & 0x3; 91 92 case 5: 93 return (tlbcfg >> 20) & 0x1; 94 95 case 6: 96 return (tlbcfg >> 24) & 0x1; 97 98 default: 99 return 0; 100 } 101 } 102 103 /*! 104 * Get bit mask for the virtual address bits translated by the TLB way 105 */ 106 static uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, 107 bool dtlb, uint32_t way) 108 { 109 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 110 bool varway56 = dtlb ? 111 env->config->dtlb.varway56 : 112 env->config->itlb.varway56; 113 114 switch (way) { 115 case 4: 116 return 0xfff00000 << get_page_size(env, dtlb, way) * 2; 117 118 case 5: 119 if (varway56) { 120 return 0xf8000000 << get_page_size(env, dtlb, way); 121 } else { 122 return 0xf8000000; 123 } 124 125 case 6: 126 if (varway56) { 127 return 0xf0000000 << (1 - get_page_size(env, dtlb, way)); 128 } else { 129 return 0xf0000000; 130 } 131 132 default: 133 return 0xfffff000; 134 } 135 } else { 136 return REGION_PAGE_MASK; 137 } 138 } 139 140 /*! 141 * Get bit mask for the 'VPN without index' field. 142 * See ISA, 4.6.5.6, data format for RxTLB0 143 */ 144 static uint32_t get_vpn_mask(const CPUXtensaState *env, bool dtlb, uint32_t way) 145 { 146 if (way < 4) { 147 bool is32 = (dtlb ? 148 env->config->dtlb.nrefillentries : 149 env->config->itlb.nrefillentries) == 32; 150 return is32 ? 0xffff8000 : 0xffffc000; 151 } else if (way == 4) { 152 return xtensa_tlb_get_addr_mask(env, dtlb, way) << 2; 153 } else if (way <= 6) { 154 uint32_t mask = xtensa_tlb_get_addr_mask(env, dtlb, way); 155 bool varway56 = dtlb ? 156 env->config->dtlb.varway56 : 157 env->config->itlb.varway56; 158 159 if (varway56) { 160 return mask << (way == 5 ? 2 : 3); 161 } else { 162 return mask << 1; 163 } 164 } else { 165 return 0xfffff000; 166 } 167 } 168 169 /*! 170 * Split virtual address into VPN (with index) and entry index 171 * for the given TLB way 172 */ 173 static void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, 174 bool dtlb, uint32_t *vpn, 175 uint32_t wi, uint32_t *ei) 176 { 177 bool varway56 = dtlb ? 178 env->config->dtlb.varway56 : 179 env->config->itlb.varway56; 180 181 if (!dtlb) { 182 wi &= 7; 183 } 184 185 if (wi < 4) { 186 bool is32 = (dtlb ? 187 env->config->dtlb.nrefillentries : 188 env->config->itlb.nrefillentries) == 32; 189 *ei = (v >> 12) & (is32 ? 0x7 : 0x3); 190 } else { 191 switch (wi) { 192 case 4: 193 { 194 uint32_t eibase = 20 + get_page_size(env, dtlb, wi) * 2; 195 *ei = (v >> eibase) & 0x3; 196 } 197 break; 198 199 case 5: 200 if (varway56) { 201 uint32_t eibase = 27 + get_page_size(env, dtlb, wi); 202 *ei = (v >> eibase) & 0x3; 203 } else { 204 *ei = (v >> 27) & 0x1; 205 } 206 break; 207 208 case 6: 209 if (varway56) { 210 uint32_t eibase = 29 - get_page_size(env, dtlb, wi); 211 *ei = (v >> eibase) & 0x7; 212 } else { 213 *ei = (v >> 28) & 0x1; 214 } 215 break; 216 217 default: 218 *ei = 0; 219 break; 220 } 221 } 222 *vpn = v & xtensa_tlb_get_addr_mask(env, dtlb, wi); 223 } 224 225 /*! 226 * Split TLB address into TLB way, entry index and VPN (with index). 227 * See ISA, 4.6.5.5 - 4.6.5.8 for the TLB addressing format 228 */ 229 static bool split_tlb_entry_spec(CPUXtensaState *env, uint32_t v, bool dtlb, 230 uint32_t *vpn, uint32_t *wi, uint32_t *ei) 231 { 232 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 233 *wi = v & (dtlb ? 0xf : 0x7); 234 if (*wi < (dtlb ? env->config->dtlb.nways : env->config->itlb.nways)) { 235 split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei); 236 return true; 237 } else { 238 return false; 239 } 240 } else { 241 *vpn = v & REGION_PAGE_MASK; 242 *wi = 0; 243 *ei = (v >> 29) & 0x7; 244 return true; 245 } 246 } 247 248 static xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env, bool dtlb, 249 unsigned wi, unsigned ei) 250 { 251 const xtensa_tlb *tlb = dtlb ? &env->config->dtlb : &env->config->itlb; 252 253 assert(wi < tlb->nways && ei < tlb->way_size[wi]); 254 return dtlb ? 255 env->dtlb[wi] + ei : 256 env->itlb[wi] + ei; 257 } 258 259 static xtensa_tlb_entry *get_tlb_entry(CPUXtensaState *env, 260 uint32_t v, bool dtlb, uint32_t *pwi) 261 { 262 uint32_t vpn; 263 uint32_t wi; 264 uint32_t ei; 265 266 if (split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei)) { 267 if (pwi) { 268 *pwi = wi; 269 } 270 return xtensa_tlb_get_entry(env, dtlb, wi, ei); 271 } else { 272 return NULL; 273 } 274 } 275 276 static void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env, 277 xtensa_tlb_entry *entry, bool dtlb, 278 unsigned wi, unsigned ei, uint32_t vpn, 279 uint32_t pte) 280 { 281 entry->vaddr = vpn; 282 entry->paddr = pte & xtensa_tlb_get_addr_mask(env, dtlb, wi); 283 entry->asid = (env->sregs[RASID] >> ((pte >> 1) & 0x18)) & 0xff; 284 entry->attr = pte & 0xf; 285 } 286 287 static void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb, 288 unsigned wi, unsigned ei, 289 uint32_t vpn, uint32_t pte) 290 { 291 CPUState *cs = env_cpu(env); 292 xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei); 293 294 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 295 if (entry->variable) { 296 if (entry->asid) { 297 tlb_flush_page(cs, entry->vaddr); 298 } 299 xtensa_tlb_set_entry_mmu(env, entry, dtlb, wi, ei, vpn, pte); 300 tlb_flush_page(cs, entry->vaddr); 301 } else { 302 qemu_log_mask(LOG_GUEST_ERROR, 303 "%s %d, %d, %d trying to set immutable entry\n", 304 __func__, dtlb, wi, ei); 305 } 306 } else { 307 tlb_flush_page(cs, entry->vaddr); 308 if (xtensa_option_enabled(env->config, 309 XTENSA_OPTION_REGION_TRANSLATION)) { 310 entry->paddr = pte & REGION_PAGE_MASK; 311 } 312 entry->attr = pte & 0xf; 313 } 314 } 315 316 hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 317 { 318 XtensaCPU *cpu = XTENSA_CPU(cs); 319 uint32_t paddr; 320 uint32_t page_size; 321 unsigned access; 322 323 if (xtensa_get_physical_addr(&cpu->env, false, addr, 0, 0, 324 &paddr, &page_size, &access) == 0) { 325 return paddr; 326 } 327 if (xtensa_get_physical_addr(&cpu->env, false, addr, 2, 0, 328 &paddr, &page_size, &access) == 0) { 329 return paddr; 330 } 331 return ~0; 332 } 333 334 static void reset_tlb_mmu_all_ways(CPUXtensaState *env, 335 const xtensa_tlb *tlb, 336 xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE]) 337 { 338 unsigned wi, ei; 339 340 for (wi = 0; wi < tlb->nways; ++wi) { 341 for (ei = 0; ei < tlb->way_size[wi]; ++ei) { 342 entry[wi][ei].asid = 0; 343 entry[wi][ei].variable = true; 344 } 345 } 346 } 347 348 static void reset_tlb_mmu_ways56(CPUXtensaState *env, 349 const xtensa_tlb *tlb, 350 xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE]) 351 { 352 if (!tlb->varway56) { 353 static const xtensa_tlb_entry way5[] = { 354 { 355 .vaddr = 0xd0000000, 356 .paddr = 0, 357 .asid = 1, 358 .attr = 7, 359 .variable = false, 360 }, { 361 .vaddr = 0xd8000000, 362 .paddr = 0, 363 .asid = 1, 364 .attr = 3, 365 .variable = false, 366 } 367 }; 368 static const xtensa_tlb_entry way6[] = { 369 { 370 .vaddr = 0xe0000000, 371 .paddr = 0xf0000000, 372 .asid = 1, 373 .attr = 7, 374 .variable = false, 375 }, { 376 .vaddr = 0xf0000000, 377 .paddr = 0xf0000000, 378 .asid = 1, 379 .attr = 3, 380 .variable = false, 381 } 382 }; 383 memcpy(entry[5], way5, sizeof(way5)); 384 memcpy(entry[6], way6, sizeof(way6)); 385 } else { 386 uint32_t ei; 387 for (ei = 0; ei < 8; ++ei) { 388 entry[6][ei].vaddr = ei << 29; 389 entry[6][ei].paddr = ei << 29; 390 entry[6][ei].asid = 1; 391 entry[6][ei].attr = 3; 392 } 393 } 394 } 395 396 static void reset_tlb_region_way0(CPUXtensaState *env, 397 xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE]) 398 { 399 unsigned ei; 400 401 for (ei = 0; ei < 8; ++ei) { 402 entry[0][ei].vaddr = ei << 29; 403 entry[0][ei].paddr = ei << 29; 404 entry[0][ei].asid = 1; 405 entry[0][ei].attr = 2; 406 entry[0][ei].variable = true; 407 } 408 } 409 410 void reset_mmu(CPUXtensaState *env) 411 { 412 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 413 env->sregs[RASID] = 0x04030201; 414 env->sregs[ITLBCFG] = 0; 415 env->sregs[DTLBCFG] = 0; 416 env->autorefill_idx = 0; 417 reset_tlb_mmu_all_ways(env, &env->config->itlb, env->itlb); 418 reset_tlb_mmu_all_ways(env, &env->config->dtlb, env->dtlb); 419 reset_tlb_mmu_ways56(env, &env->config->itlb, env->itlb); 420 reset_tlb_mmu_ways56(env, &env->config->dtlb, env->dtlb); 421 } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_MPU)) { 422 unsigned i; 423 424 env->sregs[MPUENB] = 0; 425 env->sregs[MPUCFG] = env->config->n_mpu_fg_segments; 426 env->sregs[CACHEADRDIS] = 0; 427 assert(env->config->n_mpu_bg_segments > 0 && 428 env->config->mpu_bg[0].vaddr == 0); 429 for (i = 1; i < env->config->n_mpu_bg_segments; ++i) { 430 assert(env->config->mpu_bg[i].vaddr >= 431 env->config->mpu_bg[i - 1].vaddr); 432 } 433 } else { 434 env->sregs[CACHEATTR] = 0x22222222; 435 reset_tlb_region_way0(env, env->itlb); 436 reset_tlb_region_way0(env, env->dtlb); 437 } 438 } 439 440 static unsigned get_ring(const CPUXtensaState *env, uint8_t asid) 441 { 442 unsigned i; 443 for (i = 0; i < 4; ++i) { 444 if (((env->sregs[RASID] >> i * 8) & 0xff) == asid) { 445 return i; 446 } 447 } 448 return 0xff; 449 } 450 451 /*! 452 * Lookup xtensa TLB for the given virtual address. 453 * See ISA, 4.6.2.2 454 * 455 * \param pwi: [out] way index 456 * \param pei: [out] entry index 457 * \param pring: [out] access ring 458 * \return 0 if ok, exception cause code otherwise 459 */ 460 static int xtensa_tlb_lookup(const CPUXtensaState *env, 461 uint32_t addr, bool dtlb, 462 uint32_t *pwi, uint32_t *pei, uint8_t *pring) 463 { 464 const xtensa_tlb *tlb = dtlb ? 465 &env->config->dtlb : &env->config->itlb; 466 const xtensa_tlb_entry (*entry)[MAX_TLB_WAY_SIZE] = dtlb ? 467 env->dtlb : env->itlb; 468 469 int nhits = 0; 470 unsigned wi; 471 472 for (wi = 0; wi < tlb->nways; ++wi) { 473 uint32_t vpn; 474 uint32_t ei; 475 split_tlb_entry_spec_way(env, addr, dtlb, &vpn, wi, &ei); 476 if (entry[wi][ei].vaddr == vpn && entry[wi][ei].asid) { 477 unsigned ring = get_ring(env, entry[wi][ei].asid); 478 if (ring < 4) { 479 if (++nhits > 1) { 480 return dtlb ? 481 LOAD_STORE_TLB_MULTI_HIT_CAUSE : 482 INST_TLB_MULTI_HIT_CAUSE; 483 } 484 *pwi = wi; 485 *pei = ei; 486 *pring = ring; 487 } 488 } 489 } 490 return nhits ? 0 : 491 (dtlb ? LOAD_STORE_TLB_MISS_CAUSE : INST_TLB_MISS_CAUSE); 492 } 493 494 uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) 495 { 496 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 497 uint32_t wi; 498 const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi); 499 500 if (entry) { 501 return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid; 502 } else { 503 return 0; 504 } 505 } else { 506 return v & REGION_PAGE_MASK; 507 } 508 } 509 510 uint32_t HELPER(rtlb1)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) 511 { 512 const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, NULL); 513 514 if (entry) { 515 return entry->paddr | entry->attr; 516 } else { 517 return 0; 518 } 519 } 520 521 void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) 522 { 523 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 524 uint32_t wi; 525 xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi); 526 if (entry && entry->variable && entry->asid) { 527 tlb_flush_page(env_cpu(env), entry->vaddr); 528 entry->asid = 0; 529 } 530 } 531 } 532 533 uint32_t HELPER(ptlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) 534 { 535 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 536 uint32_t wi; 537 uint32_t ei; 538 uint8_t ring; 539 int res = xtensa_tlb_lookup(env, v, dtlb, &wi, &ei, &ring); 540 541 switch (res) { 542 case 0: 543 if (ring >= xtensa_get_ring(env)) { 544 return (v & 0xfffff000) | wi | (dtlb ? 0x10 : 0x8); 545 } 546 break; 547 548 case INST_TLB_MULTI_HIT_CAUSE: 549 case LOAD_STORE_TLB_MULTI_HIT_CAUSE: 550 HELPER(exception_cause_vaddr)(env, env->pc, res, v); 551 break; 552 } 553 return 0; 554 } else { 555 return (v & REGION_PAGE_MASK) | 0x1; 556 } 557 } 558 559 void HELPER(wtlb)(CPUXtensaState *env, uint32_t p, uint32_t v, uint32_t dtlb) 560 { 561 uint32_t vpn; 562 uint32_t wi; 563 uint32_t ei; 564 if (split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei)) { 565 xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p); 566 } 567 } 568 569 /*! 570 * Convert MMU ATTR to PAGE_{READ,WRITE,EXEC} mask. 571 * See ISA, 4.6.5.10 572 */ 573 static unsigned mmu_attr_to_access(uint32_t attr) 574 { 575 unsigned access = 0; 576 577 if (attr < 12) { 578 access |= PAGE_READ; 579 if (attr & 0x1) { 580 access |= PAGE_EXEC; 581 } 582 if (attr & 0x2) { 583 access |= PAGE_WRITE; 584 } 585 586 switch (attr & 0xc) { 587 case 0: 588 access |= PAGE_CACHE_BYPASS; 589 break; 590 591 case 4: 592 access |= PAGE_CACHE_WB; 593 break; 594 595 case 8: 596 access |= PAGE_CACHE_WT; 597 break; 598 } 599 } else if (attr == 13) { 600 access |= PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE; 601 } 602 return access; 603 } 604 605 /*! 606 * Convert region protection ATTR to PAGE_{READ,WRITE,EXEC} mask. 607 * See ISA, 4.6.3.3 608 */ 609 static unsigned region_attr_to_access(uint32_t attr) 610 { 611 static const unsigned access[16] = { 612 [0] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_WT, 613 [1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT, 614 [2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS, 615 [3] = PAGE_EXEC | PAGE_CACHE_WB, 616 [4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB, 617 [5] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB, 618 [14] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE, 619 }; 620 621 return access[attr & 0xf]; 622 } 623 624 /*! 625 * Convert cacheattr to PAGE_{READ,WRITE,EXEC} mask. 626 * See ISA, A.2.14 The Cache Attribute Register 627 */ 628 static unsigned cacheattr_attr_to_access(uint32_t attr) 629 { 630 static const unsigned access[16] = { 631 [0] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_WT, 632 [1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT, 633 [2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS, 634 [3] = PAGE_EXEC | PAGE_CACHE_WB, 635 [4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB, 636 [14] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE, 637 }; 638 639 return access[attr & 0xf]; 640 } 641 642 struct attr_pattern { 643 uint32_t mask; 644 uint32_t value; 645 }; 646 647 static int attr_pattern_match(uint32_t attr, 648 const struct attr_pattern *pattern, 649 size_t n) 650 { 651 size_t i; 652 653 for (i = 0; i < n; ++i) { 654 if ((attr & pattern[i].mask) == pattern[i].value) { 655 return 1; 656 } 657 } 658 return 0; 659 } 660 661 static unsigned mpu_attr_to_cpu_cache(uint32_t attr) 662 { 663 static const struct attr_pattern cpu_c[] = { 664 { .mask = 0x18f, .value = 0x089 }, 665 { .mask = 0x188, .value = 0x080 }, 666 { .mask = 0x180, .value = 0x180 }, 667 }; 668 669 unsigned type = 0; 670 671 if (attr_pattern_match(attr, cpu_c, ARRAY_SIZE(cpu_c))) { 672 type |= XTENSA_MPU_TYPE_CPU_CACHE; 673 if (attr & 0x10) { 674 type |= XTENSA_MPU_TYPE_CPU_C; 675 } 676 if (attr & 0x20) { 677 type |= XTENSA_MPU_TYPE_CPU_W; 678 } 679 if (attr & 0x40) { 680 type |= XTENSA_MPU_TYPE_CPU_R; 681 } 682 } 683 return type; 684 } 685 686 static unsigned mpu_attr_to_type(uint32_t attr) 687 { 688 static const struct attr_pattern device_type[] = { 689 { .mask = 0x1f6, .value = 0x000 }, 690 { .mask = 0x1f6, .value = 0x006 }, 691 }; 692 static const struct attr_pattern sys_nc_type[] = { 693 { .mask = 0x1fe, .value = 0x018 }, 694 { .mask = 0x1fe, .value = 0x01e }, 695 { .mask = 0x18f, .value = 0x089 }, 696 }; 697 static const struct attr_pattern sys_c_type[] = { 698 { .mask = 0x1f8, .value = 0x010 }, 699 { .mask = 0x188, .value = 0x080 }, 700 { .mask = 0x1f0, .value = 0x030 }, 701 { .mask = 0x180, .value = 0x180 }, 702 }; 703 static const struct attr_pattern b[] = { 704 { .mask = 0x1f7, .value = 0x001 }, 705 { .mask = 0x1f7, .value = 0x007 }, 706 { .mask = 0x1ff, .value = 0x019 }, 707 { .mask = 0x1ff, .value = 0x01f }, 708 }; 709 710 unsigned type = 0; 711 712 attr = (attr & XTENSA_MPU_MEM_TYPE_MASK) >> XTENSA_MPU_MEM_TYPE_SHIFT; 713 if (attr_pattern_match(attr, device_type, ARRAY_SIZE(device_type))) { 714 type |= XTENSA_MPU_SYSTEM_TYPE_DEVICE; 715 if (attr & 0x80) { 716 type |= XTENSA_MPU_TYPE_INT; 717 } 718 } 719 if (attr_pattern_match(attr, sys_nc_type, ARRAY_SIZE(sys_nc_type))) { 720 type |= XTENSA_MPU_SYSTEM_TYPE_NC; 721 } 722 if (attr_pattern_match(attr, sys_c_type, ARRAY_SIZE(sys_c_type))) { 723 type |= XTENSA_MPU_SYSTEM_TYPE_C; 724 if (attr & 0x1) { 725 type |= XTENSA_MPU_TYPE_SYS_C; 726 } 727 if (attr & 0x2) { 728 type |= XTENSA_MPU_TYPE_SYS_W; 729 } 730 if (attr & 0x4) { 731 type |= XTENSA_MPU_TYPE_SYS_R; 732 } 733 } 734 if (attr_pattern_match(attr, b, ARRAY_SIZE(b))) { 735 type |= XTENSA_MPU_TYPE_B; 736 } 737 type |= mpu_attr_to_cpu_cache(attr); 738 739 return type; 740 } 741 742 static unsigned mpu_attr_to_access(uint32_t attr, unsigned ring) 743 { 744 static const unsigned access[2][16] = { 745 [0] = { 746 [4] = PAGE_READ, 747 [5] = PAGE_READ | PAGE_EXEC, 748 [6] = PAGE_READ | PAGE_WRITE, 749 [7] = PAGE_READ | PAGE_WRITE | PAGE_EXEC, 750 [8] = PAGE_WRITE, 751 [9] = PAGE_READ | PAGE_WRITE, 752 [10] = PAGE_READ | PAGE_WRITE, 753 [11] = PAGE_READ | PAGE_WRITE | PAGE_EXEC, 754 [12] = PAGE_READ, 755 [13] = PAGE_READ | PAGE_EXEC, 756 [14] = PAGE_READ | PAGE_WRITE, 757 [15] = PAGE_READ | PAGE_WRITE | PAGE_EXEC, 758 }, 759 [1] = { 760 [8] = PAGE_WRITE, 761 [9] = PAGE_READ | PAGE_WRITE | PAGE_EXEC, 762 [10] = PAGE_READ, 763 [11] = PAGE_READ | PAGE_EXEC, 764 [12] = PAGE_READ, 765 [13] = PAGE_READ | PAGE_EXEC, 766 [14] = PAGE_READ | PAGE_WRITE, 767 [15] = PAGE_READ | PAGE_WRITE | PAGE_EXEC, 768 }, 769 }; 770 unsigned rv; 771 unsigned type; 772 773 type = mpu_attr_to_cpu_cache(attr); 774 rv = access[ring != 0][(attr & XTENSA_MPU_ACC_RIGHTS_MASK) >> 775 XTENSA_MPU_ACC_RIGHTS_SHIFT]; 776 777 if (type & XTENSA_MPU_TYPE_CPU_CACHE) { 778 rv |= (type & XTENSA_MPU_TYPE_CPU_C) ? PAGE_CACHE_WB : PAGE_CACHE_WT; 779 } else { 780 rv |= PAGE_CACHE_BYPASS; 781 } 782 return rv; 783 } 784 785 static bool is_access_granted(unsigned access, int is_write) 786 { 787 switch (is_write) { 788 case 0: 789 return access & PAGE_READ; 790 791 case 1: 792 return access & PAGE_WRITE; 793 794 case 2: 795 return access & PAGE_EXEC; 796 797 default: 798 return 0; 799 } 800 } 801 802 static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte); 803 804 static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb, 805 uint32_t vaddr, int is_write, int mmu_idx, 806 uint32_t *paddr, uint32_t *page_size, 807 unsigned *access, bool may_lookup_pt) 808 { 809 bool dtlb = is_write != 2; 810 uint32_t wi; 811 uint32_t ei; 812 uint8_t ring; 813 uint32_t vpn; 814 uint32_t pte; 815 const xtensa_tlb_entry *entry = NULL; 816 xtensa_tlb_entry tmp_entry; 817 int ret = xtensa_tlb_lookup(env, vaddr, dtlb, &wi, &ei, &ring); 818 819 if ((ret == INST_TLB_MISS_CAUSE || ret == LOAD_STORE_TLB_MISS_CAUSE) && 820 may_lookup_pt && get_pte(env, vaddr, &pte)) { 821 ring = (pte >> 4) & 0x3; 822 wi = 0; 823 split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, wi, &ei); 824 825 if (update_tlb) { 826 wi = ++env->autorefill_idx & 0x3; 827 xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, pte); 828 env->sregs[EXCVADDR] = vaddr; 829 qemu_log_mask(CPU_LOG_MMU, "%s: autorefill(%08x): %08x -> %08x\n", 830 __func__, vaddr, vpn, pte); 831 } else { 832 xtensa_tlb_set_entry_mmu(env, &tmp_entry, dtlb, wi, ei, vpn, pte); 833 entry = &tmp_entry; 834 } 835 ret = 0; 836 } 837 if (ret != 0) { 838 return ret; 839 } 840 841 if (entry == NULL) { 842 entry = xtensa_tlb_get_entry(env, dtlb, wi, ei); 843 } 844 845 if (ring < mmu_idx) { 846 return dtlb ? 847 LOAD_STORE_PRIVILEGE_CAUSE : 848 INST_FETCH_PRIVILEGE_CAUSE; 849 } 850 851 *access = mmu_attr_to_access(entry->attr) & 852 ~(dtlb ? PAGE_EXEC : PAGE_READ | PAGE_WRITE); 853 if (!is_access_granted(*access, is_write)) { 854 return dtlb ? 855 (is_write ? 856 STORE_PROHIBITED_CAUSE : 857 LOAD_PROHIBITED_CAUSE) : 858 INST_FETCH_PROHIBITED_CAUSE; 859 } 860 861 *paddr = entry->paddr | (vaddr & ~xtensa_tlb_get_addr_mask(env, dtlb, wi)); 862 *page_size = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1; 863 864 return 0; 865 } 866 867 static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte) 868 { 869 CPUState *cs = env_cpu(env); 870 uint32_t paddr; 871 uint32_t page_size; 872 unsigned access; 873 uint32_t pt_vaddr = 874 (env->sregs[PTEVADDR] | (vaddr >> 10)) & 0xfffffffc; 875 int ret = get_physical_addr_mmu(env, false, pt_vaddr, 0, 0, 876 &paddr, &page_size, &access, false); 877 878 if (ret == 0) { 879 qemu_log_mask(CPU_LOG_MMU, 880 "%s: autorefill(%08x): PTE va = %08x, pa = %08x\n", 881 __func__, vaddr, pt_vaddr, paddr); 882 } else { 883 qemu_log_mask(CPU_LOG_MMU, 884 "%s: autorefill(%08x): PTE va = %08x, failed (%d)\n", 885 __func__, vaddr, pt_vaddr, ret); 886 } 887 888 if (ret == 0) { 889 MemTxResult result; 890 891 *pte = address_space_ldl(cs->as, paddr, MEMTXATTRS_UNSPECIFIED, 892 &result); 893 if (result != MEMTX_OK) { 894 qemu_log_mask(CPU_LOG_MMU, 895 "%s: couldn't load PTE: transaction failed (%u)\n", 896 __func__, (unsigned)result); 897 ret = 1; 898 } 899 } 900 return ret == 0; 901 } 902 903 static int get_physical_addr_region(CPUXtensaState *env, 904 uint32_t vaddr, int is_write, int mmu_idx, 905 uint32_t *paddr, uint32_t *page_size, 906 unsigned *access) 907 { 908 bool dtlb = is_write != 2; 909 uint32_t wi = 0; 910 uint32_t ei = (vaddr >> 29) & 0x7; 911 const xtensa_tlb_entry *entry = 912 xtensa_tlb_get_entry(env, dtlb, wi, ei); 913 914 *access = region_attr_to_access(entry->attr); 915 if (!is_access_granted(*access, is_write)) { 916 return dtlb ? 917 (is_write ? 918 STORE_PROHIBITED_CAUSE : 919 LOAD_PROHIBITED_CAUSE) : 920 INST_FETCH_PROHIBITED_CAUSE; 921 } 922 923 *paddr = entry->paddr | (vaddr & ~REGION_PAGE_MASK); 924 *page_size = ~REGION_PAGE_MASK + 1; 925 926 return 0; 927 } 928 929 static int xtensa_mpu_lookup(const xtensa_mpu_entry *entry, unsigned n, 930 uint32_t vaddr, unsigned *segment) 931 { 932 unsigned nhits = 0; 933 unsigned i; 934 935 for (i = 0; i < n; ++i) { 936 if (vaddr >= entry[i].vaddr && 937 (i == n - 1 || vaddr < entry[i + 1].vaddr)) { 938 if (nhits++) { 939 break; 940 } 941 *segment = i; 942 } 943 } 944 return nhits; 945 } 946 947 void HELPER(wsr_mpuenb)(CPUXtensaState *env, uint32_t v) 948 { 949 v &= (2u << (env->config->n_mpu_fg_segments - 1)) - 1; 950 951 if (v != env->sregs[MPUENB]) { 952 env->sregs[MPUENB] = v; 953 tlb_flush(env_cpu(env)); 954 } 955 } 956 957 void HELPER(wptlb)(CPUXtensaState *env, uint32_t p, uint32_t v) 958 { 959 unsigned segment = p & XTENSA_MPU_SEGMENT_MASK; 960 961 if (segment < env->config->n_mpu_fg_segments) { 962 env->mpu_fg[segment].vaddr = v & -env->config->mpu_align; 963 env->mpu_fg[segment].attr = p & XTENSA_MPU_ATTR_MASK; 964 env->sregs[MPUENB] = deposit32(env->sregs[MPUENB], segment, 1, v); 965 tlb_flush(env_cpu(env)); 966 } 967 } 968 969 uint32_t HELPER(rptlb0)(CPUXtensaState *env, uint32_t s) 970 { 971 unsigned segment = s & XTENSA_MPU_SEGMENT_MASK; 972 973 if (segment < env->config->n_mpu_fg_segments) { 974 return env->mpu_fg[segment].vaddr | 975 extract32(env->sregs[MPUENB], segment, 1); 976 } else { 977 return 0; 978 } 979 } 980 981 uint32_t HELPER(rptlb1)(CPUXtensaState *env, uint32_t s) 982 { 983 unsigned segment = s & XTENSA_MPU_SEGMENT_MASK; 984 985 if (segment < env->config->n_mpu_fg_segments) { 986 return env->mpu_fg[segment].attr; 987 } else { 988 return 0; 989 } 990 } 991 992 uint32_t HELPER(pptlb)(CPUXtensaState *env, uint32_t v) 993 { 994 unsigned nhits; 995 unsigned segment; 996 unsigned bg_segment; 997 998 nhits = xtensa_mpu_lookup(env->mpu_fg, env->config->n_mpu_fg_segments, 999 v, &segment); 1000 if (nhits > 1) { 1001 HELPER(exception_cause_vaddr)(env, env->pc, 1002 LOAD_STORE_TLB_MULTI_HIT_CAUSE, v); 1003 } else if (nhits == 1 && (env->sregs[MPUENB] & (1u << segment))) { 1004 return env->mpu_fg[segment].attr | segment | XTENSA_MPU_PROBE_V; 1005 } else { 1006 xtensa_mpu_lookup(env->config->mpu_bg, 1007 env->config->n_mpu_bg_segments, 1008 v, &bg_segment); 1009 return env->config->mpu_bg[bg_segment].attr | XTENSA_MPU_PROBE_B; 1010 } 1011 } 1012 1013 static int get_physical_addr_mpu(CPUXtensaState *env, 1014 uint32_t vaddr, int is_write, int mmu_idx, 1015 uint32_t *paddr, uint32_t *page_size, 1016 unsigned *access) 1017 { 1018 unsigned nhits; 1019 unsigned segment; 1020 uint32_t attr; 1021 1022 nhits = xtensa_mpu_lookup(env->mpu_fg, env->config->n_mpu_fg_segments, 1023 vaddr, &segment); 1024 if (nhits > 1) { 1025 return is_write < 2 ? 1026 LOAD_STORE_TLB_MULTI_HIT_CAUSE : 1027 INST_TLB_MULTI_HIT_CAUSE; 1028 } else if (nhits == 1 && (env->sregs[MPUENB] & (1u << segment))) { 1029 attr = env->mpu_fg[segment].attr; 1030 } else { 1031 xtensa_mpu_lookup(env->config->mpu_bg, 1032 env->config->n_mpu_bg_segments, 1033 vaddr, &segment); 1034 attr = env->config->mpu_bg[segment].attr; 1035 } 1036 1037 *access = mpu_attr_to_access(attr, mmu_idx); 1038 if (!is_access_granted(*access, is_write)) { 1039 return is_write < 2 ? 1040 (is_write ? 1041 STORE_PROHIBITED_CAUSE : 1042 LOAD_PROHIBITED_CAUSE) : 1043 INST_FETCH_PROHIBITED_CAUSE; 1044 } 1045 *paddr = vaddr; 1046 *page_size = env->config->mpu_align; 1047 return 0; 1048 } 1049 1050 /*! 1051 * Convert virtual address to physical addr. 1052 * MMU may issue pagewalk and change xtensa autorefill TLB way entry. 1053 * 1054 * \return 0 if ok, exception cause code otherwise 1055 */ 1056 int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb, 1057 uint32_t vaddr, int is_write, int mmu_idx, 1058 uint32_t *paddr, uint32_t *page_size, 1059 unsigned *access) 1060 { 1061 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 1062 return get_physical_addr_mmu(env, update_tlb, 1063 vaddr, is_write, mmu_idx, paddr, 1064 page_size, access, true); 1065 } else if (xtensa_option_bits_enabled(env->config, 1066 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) | 1067 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION))) { 1068 return get_physical_addr_region(env, vaddr, is_write, mmu_idx, 1069 paddr, page_size, access); 1070 } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_MPU)) { 1071 return get_physical_addr_mpu(env, vaddr, is_write, mmu_idx, 1072 paddr, page_size, access); 1073 } else { 1074 *paddr = vaddr; 1075 *page_size = TARGET_PAGE_SIZE; 1076 *access = cacheattr_attr_to_access(env->sregs[CACHEATTR] >> 1077 ((vaddr & 0xe0000000) >> 27)); 1078 return 0; 1079 } 1080 } 1081 1082 static void dump_tlb(CPUXtensaState *env, bool dtlb) 1083 { 1084 unsigned wi, ei; 1085 const xtensa_tlb *conf = 1086 dtlb ? &env->config->dtlb : &env->config->itlb; 1087 unsigned (*attr_to_access)(uint32_t) = 1088 xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) ? 1089 mmu_attr_to_access : region_attr_to_access; 1090 1091 for (wi = 0; wi < conf->nways; ++wi) { 1092 uint32_t sz = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1; 1093 const char *sz_text; 1094 bool print_header = true; 1095 1096 if (sz >= 0x100000) { 1097 sz /= MiB; 1098 sz_text = "MB"; 1099 } else { 1100 sz /= KiB; 1101 sz_text = "KB"; 1102 } 1103 1104 for (ei = 0; ei < conf->way_size[wi]; ++ei) { 1105 const xtensa_tlb_entry *entry = 1106 xtensa_tlb_get_entry(env, dtlb, wi, ei); 1107 1108 if (entry->asid) { 1109 static const char * const cache_text[8] = { 1110 [PAGE_CACHE_BYPASS >> PAGE_CACHE_SHIFT] = "Bypass", 1111 [PAGE_CACHE_WT >> PAGE_CACHE_SHIFT] = "WT", 1112 [PAGE_CACHE_WB >> PAGE_CACHE_SHIFT] = "WB", 1113 [PAGE_CACHE_ISOLATE >> PAGE_CACHE_SHIFT] = "Isolate", 1114 }; 1115 unsigned access = attr_to_access(entry->attr); 1116 unsigned cache_idx = (access & PAGE_CACHE_MASK) >> 1117 PAGE_CACHE_SHIFT; 1118 1119 if (print_header) { 1120 print_header = false; 1121 qemu_printf("Way %u (%d %s)\n", wi, sz, sz_text); 1122 qemu_printf("\tVaddr Paddr ASID Attr RWX Cache\n" 1123 "\t---------- ---------- ---- ---- --- -------\n"); 1124 } 1125 qemu_printf("\t0x%08x 0x%08x 0x%02x 0x%02x %c%c%c %s\n", 1126 entry->vaddr, 1127 entry->paddr, 1128 entry->asid, 1129 entry->attr, 1130 (access & PAGE_READ) ? 'R' : '-', 1131 (access & PAGE_WRITE) ? 'W' : '-', 1132 (access & PAGE_EXEC) ? 'X' : '-', 1133 cache_text[cache_idx] ? 1134 cache_text[cache_idx] : "Invalid"); 1135 } 1136 } 1137 } 1138 } 1139 1140 static void dump_mpu(CPUXtensaState *env, 1141 const xtensa_mpu_entry *entry, unsigned n) 1142 { 1143 unsigned i; 1144 1145 qemu_printf("\t%s Vaddr Attr Ring0 Ring1 System Type CPU cache\n" 1146 "\t%s ---------- ---------- ----- ----- ------------- ---------\n", 1147 env ? "En" : " ", 1148 env ? "--" : " "); 1149 1150 for (i = 0; i < n; ++i) { 1151 uint32_t attr = entry[i].attr; 1152 unsigned access0 = mpu_attr_to_access(attr, 0); 1153 unsigned access1 = mpu_attr_to_access(attr, 1); 1154 unsigned type = mpu_attr_to_type(attr); 1155 char cpu_cache = (type & XTENSA_MPU_TYPE_CPU_CACHE) ? '-' : ' '; 1156 1157 qemu_printf("\t %c 0x%08x 0x%08x %c%c%c %c%c%c ", 1158 env ? 1159 ((env->sregs[MPUENB] & (1u << i)) ? '+' : '-') : ' ', 1160 entry[i].vaddr, attr, 1161 (access0 & PAGE_READ) ? 'R' : '-', 1162 (access0 & PAGE_WRITE) ? 'W' : '-', 1163 (access0 & PAGE_EXEC) ? 'X' : '-', 1164 (access1 & PAGE_READ) ? 'R' : '-', 1165 (access1 & PAGE_WRITE) ? 'W' : '-', 1166 (access1 & PAGE_EXEC) ? 'X' : '-'); 1167 1168 switch (type & XTENSA_MPU_SYSTEM_TYPE_MASK) { 1169 case XTENSA_MPU_SYSTEM_TYPE_DEVICE: 1170 qemu_printf("Device %cB %3s\n", 1171 (type & XTENSA_MPU_TYPE_B) ? ' ' : 'n', 1172 (type & XTENSA_MPU_TYPE_INT) ? "int" : ""); 1173 break; 1174 case XTENSA_MPU_SYSTEM_TYPE_NC: 1175 qemu_printf("Sys NC %cB %c%c%c\n", 1176 (type & XTENSA_MPU_TYPE_B) ? ' ' : 'n', 1177 (type & XTENSA_MPU_TYPE_CPU_R) ? 'r' : cpu_cache, 1178 (type & XTENSA_MPU_TYPE_CPU_W) ? 'w' : cpu_cache, 1179 (type & XTENSA_MPU_TYPE_CPU_C) ? 'c' : cpu_cache); 1180 break; 1181 case XTENSA_MPU_SYSTEM_TYPE_C: 1182 qemu_printf("Sys C %c%c%c %c%c%c\n", 1183 (type & XTENSA_MPU_TYPE_SYS_R) ? 'R' : '-', 1184 (type & XTENSA_MPU_TYPE_SYS_W) ? 'W' : '-', 1185 (type & XTENSA_MPU_TYPE_SYS_C) ? 'C' : '-', 1186 (type & XTENSA_MPU_TYPE_CPU_R) ? 'r' : cpu_cache, 1187 (type & XTENSA_MPU_TYPE_CPU_W) ? 'w' : cpu_cache, 1188 (type & XTENSA_MPU_TYPE_CPU_C) ? 'c' : cpu_cache); 1189 break; 1190 default: 1191 qemu_printf("Unknown\n"); 1192 break; 1193 } 1194 } 1195 } 1196 1197 void dump_mmu(CPUXtensaState *env) 1198 { 1199 if (xtensa_option_bits_enabled(env->config, 1200 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) | 1201 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION) | 1202 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU))) { 1203 1204 qemu_printf("ITLB:\n"); 1205 dump_tlb(env, false); 1206 qemu_printf("\nDTLB:\n"); 1207 dump_tlb(env, true); 1208 } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_MPU)) { 1209 qemu_printf("Foreground map:\n"); 1210 dump_mpu(env, env->mpu_fg, env->config->n_mpu_fg_segments); 1211 qemu_printf("\nBackground map:\n"); 1212 dump_mpu(NULL, env->config->mpu_bg, env->config->n_mpu_bg_segments); 1213 } else { 1214 qemu_printf("No TLB for this CPU core\n"); 1215 } 1216 } 1217