1 /* 2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * * Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * * Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * * Neither the name of the Open Source and Linux Lab nor the 13 * names of its contributors may be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include "qemu/osdep.h" 29 #include "qemu/log.h" 30 #include "cpu.h" 31 #include "exec/cputlb.h" 32 #include "exec/target_page.h" 33 #include "gdbstub/helpers.h" 34 #include "exec/helper-proto.h" 35 #include "qemu/error-report.h" 36 #include "qemu/qemu-print.h" 37 #include "qemu/host-utils.h" 38 39 static struct XtensaConfigList *xtensa_cores; 40 41 static void add_translator_to_hash(GHashTable *translator, 42 const char *name, 43 const XtensaOpcodeOps *opcode) 44 { 45 if (!g_hash_table_insert(translator, (void *)name, (void *)opcode)) { 46 error_report("Multiple definitions of '%s' opcode in a single table", 47 name); 48 } 49 } 50 51 static GHashTable *hash_opcode_translators(const XtensaOpcodeTranslators *t) 52 { 53 unsigned i, j; 54 GHashTable *translator = g_hash_table_new(g_str_hash, g_str_equal); 55 56 for (i = 0; i < t->num_opcodes; ++i) { 57 if (t->opcode[i].op_flags & XTENSA_OP_NAME_ARRAY) { 58 const char * const *name = t->opcode[i].name; 59 60 for (j = 0; name[j]; ++j) { 61 add_translator_to_hash(translator, 62 (void *)name[j], 63 (void *)(t->opcode + i)); 64 } 65 } else { 66 add_translator_to_hash(translator, 67 (void *)t->opcode[i].name, 68 (void *)(t->opcode + i)); 69 } 70 } 71 return translator; 72 } 73 74 static XtensaOpcodeOps * 75 xtensa_find_opcode_ops(const XtensaOpcodeTranslators *t, 76 const char *name) 77 { 78 static GHashTable *translators; 79 GHashTable *translator; 80 81 if (translators == NULL) { 82 translators = g_hash_table_new(g_direct_hash, g_direct_equal); 83 } 84 translator = g_hash_table_lookup(translators, t); 85 if (translator == NULL) { 86 translator = hash_opcode_translators(t); 87 g_hash_table_insert(translators, (void *)t, translator); 88 } 89 return g_hash_table_lookup(translator, name); 90 } 91 92 static void init_libisa(XtensaConfig *config) 93 { 94 unsigned i, j; 95 unsigned opcodes; 96 unsigned formats; 97 unsigned regfiles; 98 99 config->isa = xtensa_isa_init(config->isa_internal, NULL, NULL); 100 assert(xtensa_isa_maxlength(config->isa) <= MAX_INSN_LENGTH); 101 assert(xtensa_insnbuf_size(config->isa) <= MAX_INSNBUF_LENGTH); 102 opcodes = xtensa_isa_num_opcodes(config->isa); 103 formats = xtensa_isa_num_formats(config->isa); 104 regfiles = xtensa_isa_num_regfiles(config->isa); 105 config->opcode_ops = g_new(XtensaOpcodeOps *, opcodes); 106 107 for (i = 0; i < formats; ++i) { 108 assert(xtensa_format_num_slots(config->isa, i) <= MAX_INSN_SLOTS); 109 } 110 111 for (i = 0; i < opcodes; ++i) { 112 const char *opc_name = xtensa_opcode_name(config->isa, i); 113 XtensaOpcodeOps *ops = NULL; 114 115 assert(xtensa_opcode_num_operands(config->isa, i) <= MAX_OPCODE_ARGS); 116 if (!config->opcode_translators) { 117 ops = xtensa_find_opcode_ops(&xtensa_core_opcodes, opc_name); 118 } else { 119 for (j = 0; !ops && config->opcode_translators[j]; ++j) { 120 ops = xtensa_find_opcode_ops(config->opcode_translators[j], 121 opc_name); 122 } 123 } 124 #ifdef DEBUG 125 if (ops == NULL) { 126 fprintf(stderr, 127 "opcode translator not found for %s's opcode '%s'\n", 128 config->name, opc_name); 129 } 130 #endif 131 config->opcode_ops[i] = ops; 132 } 133 config->a_regfile = xtensa_regfile_lookup(config->isa, "AR"); 134 135 config->regfile = g_new(void **, regfiles); 136 for (i = 0; i < regfiles; ++i) { 137 const char *name = xtensa_regfile_name(config->isa, i); 138 int entries = xtensa_regfile_num_entries(config->isa, i); 139 int bits = xtensa_regfile_num_bits(config->isa, i); 140 141 config->regfile[i] = xtensa_get_regfile_by_name(name, entries, bits); 142 #ifdef DEBUG 143 if (config->regfile[i] == NULL) { 144 fprintf(stderr, "regfile '%s' not found for %s\n", 145 name, config->name); 146 } 147 #endif 148 } 149 xtensa_collect_sr_names(config); 150 } 151 152 static void xtensa_finalize_config(XtensaConfig *config) 153 { 154 if (config->isa_internal) { 155 init_libisa(config); 156 } 157 158 if (config->gdb_regmap.num_regs == 0 || 159 config->gdb_regmap.num_core_regs == 0) { 160 unsigned n_regs = 0; 161 unsigned n_core_regs = 0; 162 163 xtensa_count_regs(config, &n_regs, &n_core_regs); 164 if (config->gdb_regmap.num_regs == 0) { 165 config->gdb_regmap.num_regs = n_regs; 166 } 167 if (config->gdb_regmap.num_core_regs == 0) { 168 config->gdb_regmap.num_core_regs = n_core_regs; 169 } 170 } 171 } 172 173 static void xtensa_core_class_init(ObjectClass *oc, const void *data) 174 { 175 CPUClass *cc = CPU_CLASS(oc); 176 XtensaCPUClass *xcc = XTENSA_CPU_CLASS(oc); 177 const XtensaConfig *config = data; 178 179 xcc->config = config; 180 181 /* 182 * Use num_core_regs to see only non-privileged registers in an unmodified 183 * gdb. Use num_regs to see all registers. gdb modification is required 184 * for that: reset bit 0 in the 'flags' field of the registers definitions 185 * in the gdb/xtensa-config.c inside gdb source tree or inside gdb overlay. 186 */ 187 cc->gdb_num_core_regs = config->gdb_regmap.num_regs; 188 } 189 190 void xtensa_register_core(XtensaConfigList *node) 191 { 192 TypeInfo type = { 193 .parent = TYPE_XTENSA_CPU, 194 .class_init = xtensa_core_class_init, 195 .class_data = node->config, 196 }; 197 198 xtensa_finalize_config(node->config); 199 200 node->next = xtensa_cores; 201 xtensa_cores = node; 202 type.name = g_strdup_printf(XTENSA_CPU_TYPE_NAME("%s"), node->config->name); 203 type_register_static(&type); 204 g_free((gpointer)type.name); 205 } 206 207 static uint32_t check_hw_breakpoints(CPUXtensaState *env) 208 { 209 unsigned i; 210 211 for (i = 0; i < env->config->ndbreak; ++i) { 212 if (env->cpu_watchpoint[i] && 213 env->cpu_watchpoint[i]->flags & BP_WATCHPOINT_HIT) { 214 return DEBUGCAUSE_DB | (i << DEBUGCAUSE_DBNUM_SHIFT); 215 } 216 } 217 return 0; 218 } 219 220 void xtensa_breakpoint_handler(CPUState *cs) 221 { 222 CPUXtensaState *env = cpu_env(cs); 223 224 if (cs->watchpoint_hit) { 225 if (cs->watchpoint_hit->flags & BP_CPU) { 226 uint32_t cause; 227 228 cs->watchpoint_hit = NULL; 229 cause = check_hw_breakpoints(env); 230 if (cause) { 231 debug_exception_env(env, cause); 232 } 233 cpu_loop_exit_noexc(cs); 234 } 235 } else { 236 if (cpu_breakpoint_test(cs, env->pc, BP_GDB) 237 || !cpu_breakpoint_test(cs, env->pc, BP_CPU)) { 238 return; 239 } 240 if (env->sregs[ICOUNT] == 0xffffffff && 241 xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) { 242 debug_exception_env(env, DEBUGCAUSE_IC); 243 } else { 244 debug_exception_env(env, DEBUGCAUSE_IB); 245 } 246 cpu_loop_exit_noexc(cs); 247 } 248 } 249 250 #ifndef CONFIG_USER_ONLY 251 void xtensa_cpu_do_unaligned_access(CPUState *cs, 252 vaddr addr, MMUAccessType access_type, 253 int mmu_idx, uintptr_t retaddr) 254 { 255 XtensaCPU *cpu = XTENSA_CPU(cs); 256 CPUXtensaState *env = &cpu->env; 257 258 assert(xtensa_option_enabled(env->config, 259 XTENSA_OPTION_UNALIGNED_EXCEPTION)); 260 cpu_restore_state(CPU(cpu), retaddr); 261 HELPER(exception_cause_vaddr)(env, 262 env->pc, LOAD_STORE_ALIGNMENT_CAUSE, 263 addr); 264 } 265 266 bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 267 MMUAccessType access_type, int mmu_idx, 268 bool probe, uintptr_t retaddr) 269 { 270 CPUXtensaState *env = cpu_env(cs); 271 uint32_t paddr; 272 uint32_t page_size; 273 unsigned access; 274 int ret = xtensa_get_physical_addr(env, true, address, access_type, 275 mmu_idx, &paddr, &page_size, &access); 276 277 qemu_log_mask(CPU_LOG_MMU, "%s(%08" VADDR_PRIx 278 ", %d, %d) -> %08x, ret = %d\n", 279 __func__, address, access_type, mmu_idx, paddr, ret); 280 281 if (ret == 0) { 282 tlb_set_page(cs, 283 address & TARGET_PAGE_MASK, 284 paddr & TARGET_PAGE_MASK, 285 access, mmu_idx, page_size); 286 return true; 287 } else if (probe) { 288 return false; 289 } else { 290 cpu_restore_state(cs, retaddr); 291 HELPER(exception_cause_vaddr)(env, env->pc, ret, address); 292 } 293 } 294 295 void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, 296 unsigned size, MMUAccessType access_type, 297 int mmu_idx, MemTxAttrs attrs, 298 MemTxResult response, uintptr_t retaddr) 299 { 300 CPUXtensaState *env = cpu_env(cs); 301 302 cpu_restore_state(cs, retaddr); 303 HELPER(exception_cause_vaddr)(env, env->pc, 304 access_type == MMU_INST_FETCH ? 305 INSTR_PIF_ADDR_ERROR_CAUSE : 306 LOAD_STORE_PIF_ADDR_ERROR_CAUSE, 307 addr); 308 } 309 310 void xtensa_runstall(CPUXtensaState *env, bool runstall) 311 { 312 CPUState *cpu = env_cpu(env); 313 314 env->runstall = runstall; 315 cpu->halted = runstall; 316 if (runstall) { 317 cpu_interrupt(cpu, CPU_INTERRUPT_HALT); 318 } else { 319 qemu_cpu_kick(cpu); 320 } 321 } 322 #endif /* !CONFIG_USER_ONLY */ 323