1 /* 2 * TriCore emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2013-2014 Bastian Koppelmann C-Lab/University Paderborn 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "exec/exec-all.h" 24 #include "tcg/tcg-op.h" 25 #include "exec/cpu_ldst.h" 26 #include "qemu/qemu-print.h" 27 28 #include "exec/helper-proto.h" 29 #include "exec/helper-gen.h" 30 31 #include "tricore-opcodes.h" 32 #include "exec/translator.h" 33 #include "exec/translation-block.h" 34 #include "exec/target_page.h" 35 #include "exec/log.h" 36 37 #define HELPER_H "helper.h" 38 #include "exec/helper-info.c.inc" 39 #undef HELPER_H 40 41 #define DISAS_EXIT DISAS_TARGET_0 42 #define DISAS_EXIT_UPDATE DISAS_TARGET_1 43 #define DISAS_JUMP DISAS_TARGET_2 44 45 /* 46 * TCG registers 47 */ 48 static TCGv cpu_PC; 49 static TCGv cpu_PCXI; 50 static TCGv cpu_PSW; 51 static TCGv cpu_ICR; 52 /* GPR registers */ 53 static TCGv cpu_gpr_a[16]; 54 static TCGv cpu_gpr_d[16]; 55 /* PSW Flag cache */ 56 static TCGv cpu_PSW_C; 57 static TCGv cpu_PSW_V; 58 static TCGv cpu_PSW_SV; 59 static TCGv cpu_PSW_AV; 60 static TCGv cpu_PSW_SAV; 61 62 static const char *regnames_a[] = { 63 "a0" , "a1" , "a2" , "a3" , "a4" , "a5" , 64 "a6" , "a7" , "a8" , "a9" , "sp" , "a11" , 65 "a12" , "a13" , "a14" , "a15", 66 }; 67 68 static const char *regnames_d[] = { 69 "d0" , "d1" , "d2" , "d3" , "d4" , "d5" , 70 "d6" , "d7" , "d8" , "d9" , "d10" , "d11" , 71 "d12" , "d13" , "d14" , "d15", 72 }; 73 74 typedef struct DisasContext { 75 DisasContextBase base; 76 target_ulong pc_succ_insn; 77 uint32_t opcode; 78 /* Routine used to access memory */ 79 int mem_idx; 80 int priv; 81 uint64_t features; 82 uint32_t icr_ie_mask, icr_ie_offset; 83 } DisasContext; 84 85 static int has_feature(DisasContext *ctx, int feature) 86 { 87 return (ctx->features & (1ULL << feature)) != 0; 88 } 89 90 enum { 91 MODE_LL = 0, 92 MODE_LU = 1, 93 MODE_UL = 2, 94 MODE_UU = 3, 95 }; 96 97 void tricore_cpu_dump_state(CPUState *cs, FILE *f, int flags) 98 { 99 CPUTriCoreState *env = cpu_env(cs); 100 uint32_t psw; 101 int i; 102 103 psw = psw_read(env); 104 105 qemu_fprintf(f, "PC: " TARGET_FMT_lx, env->PC); 106 qemu_fprintf(f, " PSW: " TARGET_FMT_lx, psw); 107 qemu_fprintf(f, " ICR: " TARGET_FMT_lx, env->ICR); 108 qemu_fprintf(f, "\nPCXI: " TARGET_FMT_lx, env->PCXI); 109 qemu_fprintf(f, " FCX: " TARGET_FMT_lx, env->FCX); 110 qemu_fprintf(f, " LCX: " TARGET_FMT_lx, env->LCX); 111 112 for (i = 0; i < 16; ++i) { 113 if ((i & 3) == 0) { 114 qemu_fprintf(f, "\nGPR A%02d:", i); 115 } 116 qemu_fprintf(f, " " TARGET_FMT_lx, env->gpr_a[i]); 117 } 118 for (i = 0; i < 16; ++i) { 119 if ((i & 3) == 0) { 120 qemu_fprintf(f, "\nGPR D%02d:", i); 121 } 122 qemu_fprintf(f, " " TARGET_FMT_lx, env->gpr_d[i]); 123 } 124 qemu_fprintf(f, "\n"); 125 } 126 127 /* 128 * Functions to generate micro-ops 129 */ 130 131 /* Macros for generating helpers */ 132 133 #define gen_helper_1arg(name, arg) do { \ 134 TCGv_i32 helper_tmp = tcg_constant_i32(arg); \ 135 gen_helper_##name(tcg_env, helper_tmp); \ 136 } while (0) 137 138 #define GEN_HELPER_LL(name, ret, arg0, arg1, n) do { \ 139 TCGv arg00 = tcg_temp_new(); \ 140 TCGv arg01 = tcg_temp_new(); \ 141 TCGv arg11 = tcg_temp_new(); \ 142 tcg_gen_sari_tl(arg00, arg0, 16); \ 143 tcg_gen_ext16s_tl(arg01, arg0); \ 144 tcg_gen_ext16s_tl(arg11, arg1); \ 145 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \ 146 } while (0) 147 148 #define GEN_HELPER_LU(name, ret, arg0, arg1, n) do { \ 149 TCGv arg00 = tcg_temp_new(); \ 150 TCGv arg01 = tcg_temp_new(); \ 151 TCGv arg10 = tcg_temp_new(); \ 152 TCGv arg11 = tcg_temp_new(); \ 153 tcg_gen_sari_tl(arg00, arg0, 16); \ 154 tcg_gen_ext16s_tl(arg01, arg0); \ 155 tcg_gen_sari_tl(arg11, arg1, 16); \ 156 tcg_gen_ext16s_tl(arg10, arg1); \ 157 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \ 158 } while (0) 159 160 #define GEN_HELPER_UL(name, ret, arg0, arg1, n) do { \ 161 TCGv arg00 = tcg_temp_new(); \ 162 TCGv arg01 = tcg_temp_new(); \ 163 TCGv arg10 = tcg_temp_new(); \ 164 TCGv arg11 = tcg_temp_new(); \ 165 tcg_gen_sari_tl(arg00, arg0, 16); \ 166 tcg_gen_ext16s_tl(arg01, arg0); \ 167 tcg_gen_sari_tl(arg10, arg1, 16); \ 168 tcg_gen_ext16s_tl(arg11, arg1); \ 169 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \ 170 } while (0) 171 172 #define GEN_HELPER_UU(name, ret, arg0, arg1, n) do { \ 173 TCGv arg00 = tcg_temp_new(); \ 174 TCGv arg01 = tcg_temp_new(); \ 175 TCGv arg11 = tcg_temp_new(); \ 176 tcg_gen_sari_tl(arg01, arg0, 16); \ 177 tcg_gen_ext16s_tl(arg00, arg0); \ 178 tcg_gen_sari_tl(arg11, arg1, 16); \ 179 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \ 180 } while (0) 181 182 #define GEN_HELPER_RRR(name, rl, rh, al1, ah1, arg2) do { \ 183 TCGv_i64 ret = tcg_temp_new_i64(); \ 184 TCGv_i64 arg1 = tcg_temp_new_i64(); \ 185 \ 186 tcg_gen_concat_i32_i64(arg1, al1, ah1); \ 187 gen_helper_##name(ret, arg1, arg2); \ 188 tcg_gen_extr_i64_i32(rl, rh, ret); \ 189 } while (0) 190 191 #define GEN_HELPER_RR(name, rl, rh, arg1, arg2) do { \ 192 TCGv_i64 ret = tcg_temp_new_i64(); \ 193 \ 194 gen_helper_##name(ret, tcg_env, arg1, arg2); \ 195 tcg_gen_extr_i64_i32(rl, rh, ret); \ 196 } while (0) 197 198 #define EA_ABS_FORMAT(con) (((con & 0x3C000) << 14) + (con & 0x3FFF)) 199 #define EA_B_ABSOLUT(con) (((offset & 0xf00000) << 8) | \ 200 ((offset & 0x0fffff) << 1)) 201 202 /* For two 32-bit registers used a 64-bit register, the first 203 registernumber needs to be even. Otherwise we trap. */ 204 static inline void generate_trap(DisasContext *ctx, int class, int tin); 205 #define CHECK_REG_PAIR(reg) do { \ 206 if (reg & 0x1) { \ 207 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_OPD); \ 208 } \ 209 } while (0) 210 211 /* Functions for load/save to/from memory */ 212 213 static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2, 214 int16_t con, MemOp mop) 215 { 216 TCGv temp = tcg_temp_new(); 217 tcg_gen_addi_tl(temp, r2, con); 218 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop); 219 } 220 221 static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2, 222 int16_t con, MemOp mop) 223 { 224 TCGv temp = tcg_temp_new(); 225 tcg_gen_addi_tl(temp, r2, con); 226 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop); 227 } 228 229 static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx) 230 { 231 TCGv_i64 temp = tcg_temp_new_i64(); 232 233 tcg_gen_concat_i32_i64(temp, rl, rh); 234 tcg_gen_qemu_st_i64(temp, address, ctx->mem_idx, MO_LEUQ); 235 } 236 237 static void gen_offset_st_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con, 238 DisasContext *ctx) 239 { 240 TCGv temp = tcg_temp_new(); 241 tcg_gen_addi_tl(temp, base, con); 242 gen_st_2regs_64(rh, rl, temp, ctx); 243 } 244 245 static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx) 246 { 247 TCGv_i64 temp = tcg_temp_new_i64(); 248 249 tcg_gen_qemu_ld_i64(temp, address, ctx->mem_idx, MO_LEUQ); 250 /* write back to two 32 bit regs */ 251 tcg_gen_extr_i64_i32(rl, rh, temp); 252 } 253 254 static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con, 255 DisasContext *ctx) 256 { 257 TCGv temp = tcg_temp_new(); 258 tcg_gen_addi_tl(temp, base, con); 259 gen_ld_2regs_64(rh, rl, temp, ctx); 260 } 261 262 static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off, 263 MemOp mop) 264 { 265 TCGv temp = tcg_temp_new(); 266 tcg_gen_addi_tl(temp, r2, off); 267 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop); 268 tcg_gen_mov_tl(r2, temp); 269 } 270 271 static void gen_ld_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off, 272 MemOp mop) 273 { 274 TCGv temp = tcg_temp_new(); 275 tcg_gen_addi_tl(temp, r2, off); 276 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop); 277 tcg_gen_mov_tl(r2, temp); 278 } 279 280 /* M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32]); */ 281 static void gen_ldmst(DisasContext *ctx, int ereg, TCGv ea) 282 { 283 TCGv temp = tcg_temp_new(); 284 TCGv temp2 = tcg_temp_new(); 285 286 CHECK_REG_PAIR(ereg); 287 /* temp = (M(EA, word) */ 288 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); 289 /* temp = temp & ~E[a][63:32]) */ 290 tcg_gen_andc_tl(temp, temp, cpu_gpr_d[ereg+1]); 291 /* temp2 = (E[a][31:0] & E[a][63:32]); */ 292 tcg_gen_and_tl(temp2, cpu_gpr_d[ereg], cpu_gpr_d[ereg+1]); 293 /* temp = temp | temp2; */ 294 tcg_gen_or_tl(temp, temp, temp2); 295 /* M(EA, word) = temp; */ 296 tcg_gen_qemu_st_tl(temp, ea, ctx->mem_idx, MO_LEUL); 297 } 298 299 /* tmp = M(EA, word); 300 M(EA, word) = D[a]; 301 D[a] = tmp[31:0];*/ 302 static void gen_swap(DisasContext *ctx, int reg, TCGv ea) 303 { 304 TCGv temp = tcg_temp_new(); 305 306 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); 307 tcg_gen_qemu_st_tl(cpu_gpr_d[reg], ea, ctx->mem_idx, MO_LEUL); 308 tcg_gen_mov_tl(cpu_gpr_d[reg], temp); 309 } 310 311 static void gen_cmpswap(DisasContext *ctx, int reg, TCGv ea) 312 { 313 TCGv temp = tcg_temp_new(); 314 TCGv temp2 = tcg_temp_new(); 315 CHECK_REG_PAIR(reg); 316 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); 317 tcg_gen_movcond_tl(TCG_COND_EQ, temp2, cpu_gpr_d[reg+1], temp, 318 cpu_gpr_d[reg], temp); 319 tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL); 320 tcg_gen_mov_tl(cpu_gpr_d[reg], temp); 321 } 322 323 static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea) 324 { 325 TCGv temp = tcg_temp_new(); 326 TCGv temp2 = tcg_temp_new(); 327 TCGv temp3 = tcg_temp_new(); 328 CHECK_REG_PAIR(reg); 329 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); 330 tcg_gen_and_tl(temp2, cpu_gpr_d[reg], cpu_gpr_d[reg+1]); 331 tcg_gen_andc_tl(temp3, temp, cpu_gpr_d[reg+1]); 332 tcg_gen_or_tl(temp2, temp2, temp3); 333 tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL); 334 tcg_gen_mov_tl(cpu_gpr_d[reg], temp); 335 } 336 337 /* We generate loads and store to core special function register (csfr) through 338 the function gen_mfcr and gen_mtcr. To handle access permissions, we use 3 339 macros R, A and E, which allow read-only, all and endinit protected access. 340 These macros also specify in which ISA version the csfr was introduced. */ 341 #define R(ADDRESS, REG, FEATURE) \ 342 case ADDRESS: \ 343 if (has_feature(ctx, FEATURE)) { \ 344 tcg_gen_ld_tl(ret, tcg_env, offsetof(CPUTriCoreState, REG)); \ 345 } \ 346 break; 347 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) 348 #define E(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) 349 static inline void gen_mfcr(DisasContext *ctx, TCGv ret, int32_t offset) 350 { 351 /* since we're caching PSW make this a special case */ 352 if (offset == 0xfe04) { 353 gen_helper_psw_read(ret, tcg_env); 354 } else { 355 switch (offset) { 356 #include "csfr.h.inc" 357 } 358 } 359 } 360 #undef R 361 #undef A 362 #undef E 363 364 #define R(ADDRESS, REG, FEATURE) /* don't gen writes to read-only reg, 365 since no exception occurs */ 366 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \ 367 case ADDRESS: \ 368 if (has_feature(ctx, FEATURE)) { \ 369 tcg_gen_st_tl(r1, tcg_env, offsetof(CPUTriCoreState, REG)); \ 370 } \ 371 break; 372 /* Endinit protected registers 373 TODO: Since the endinit bit is in a register of a not yet implemented 374 watchdog device, we handle endinit protected registers like 375 all-access registers for now. */ 376 #define E(ADDRESS, REG, FEATURE) A(ADDRESS, REG, FEATURE) 377 static inline void gen_mtcr(DisasContext *ctx, TCGv r1, 378 int32_t offset) 379 { 380 if (ctx->priv == TRICORE_PRIV_SM) { 381 /* since we're caching PSW make this a special case */ 382 if (offset == 0xfe04) { 383 gen_helper_psw_write(tcg_env, r1); 384 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 385 } else { 386 switch (offset) { 387 #include "csfr.h.inc" 388 } 389 } 390 } else { 391 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); 392 } 393 } 394 395 /* Functions for arithmetic instructions */ 396 397 static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2) 398 { 399 TCGv t0 = tcg_temp_new_i32(); 400 TCGv result = tcg_temp_new_i32(); 401 /* Addition and set V/SV bits */ 402 tcg_gen_add_tl(result, r1, r2); 403 /* calc V bit */ 404 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 405 tcg_gen_xor_tl(t0, r1, r2); 406 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0); 407 /* Calc SV bit */ 408 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 409 /* Calc AV/SAV bits */ 410 tcg_gen_add_tl(cpu_PSW_AV, result, result); 411 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 412 /* calc SAV */ 413 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 414 /* write back result */ 415 tcg_gen_mov_tl(ret, result); 416 } 417 418 static inline void 419 gen_add64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2) 420 { 421 TCGv temp = tcg_temp_new(); 422 TCGv_i64 t0 = tcg_temp_new_i64(); 423 TCGv_i64 t1 = tcg_temp_new_i64(); 424 TCGv_i64 result = tcg_temp_new_i64(); 425 426 tcg_gen_add_i64(result, r1, r2); 427 /* calc v bit */ 428 tcg_gen_xor_i64(t1, result, r1); 429 tcg_gen_xor_i64(t0, r1, r2); 430 tcg_gen_andc_i64(t1, t1, t0); 431 tcg_gen_extrh_i64_i32(cpu_PSW_V, t1); 432 /* calc SV bit */ 433 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 434 /* calc AV/SAV bits */ 435 tcg_gen_extrh_i64_i32(temp, result); 436 tcg_gen_add_tl(cpu_PSW_AV, temp, temp); 437 tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV); 438 /* calc SAV */ 439 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 440 /* write back result */ 441 tcg_gen_mov_i64(ret, result); 442 } 443 444 static inline void 445 gen_addsub64_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 446 TCGv r3, void(*op1)(TCGv, TCGv, TCGv), 447 void(*op2)(TCGv, TCGv, TCGv)) 448 { 449 TCGv temp = tcg_temp_new(); 450 TCGv temp2 = tcg_temp_new(); 451 TCGv temp3 = tcg_temp_new(); 452 TCGv temp4 = tcg_temp_new(); 453 454 (*op1)(temp, r1_low, r2); 455 /* calc V0 bit */ 456 tcg_gen_xor_tl(temp2, temp, r1_low); 457 tcg_gen_xor_tl(temp3, r1_low, r2); 458 if (op1 == tcg_gen_add_tl) { 459 tcg_gen_andc_tl(temp2, temp2, temp3); 460 } else { 461 tcg_gen_and_tl(temp2, temp2, temp3); 462 } 463 464 (*op2)(temp3, r1_high, r3); 465 /* calc V1 bit */ 466 tcg_gen_xor_tl(cpu_PSW_V, temp3, r1_high); 467 tcg_gen_xor_tl(temp4, r1_high, r3); 468 if (op2 == tcg_gen_add_tl) { 469 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, temp4); 470 } else { 471 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp4); 472 } 473 /* combine V0/V1 bits */ 474 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp2); 475 /* calc sv bit */ 476 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 477 /* write result */ 478 tcg_gen_mov_tl(ret_low, temp); 479 tcg_gen_mov_tl(ret_high, temp3); 480 /* calc AV bit */ 481 tcg_gen_add_tl(temp, ret_low, ret_low); 482 tcg_gen_xor_tl(temp, temp, ret_low); 483 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 484 tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, ret_high); 485 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp); 486 /* calc SAV bit */ 487 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 488 } 489 490 /* ret = r2 + (r1 * r3); */ 491 static inline void gen_madd32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3) 492 { 493 TCGv_i64 t1 = tcg_temp_new_i64(); 494 TCGv_i64 t2 = tcg_temp_new_i64(); 495 TCGv_i64 t3 = tcg_temp_new_i64(); 496 497 tcg_gen_ext_i32_i64(t1, r1); 498 tcg_gen_ext_i32_i64(t2, r2); 499 tcg_gen_ext_i32_i64(t3, r3); 500 501 tcg_gen_mul_i64(t1, t1, t3); 502 tcg_gen_add_i64(t1, t2, t1); 503 504 tcg_gen_extrl_i64_i32(ret, t1); 505 /* calc V 506 t1 > 0x7fffffff */ 507 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); 508 /* t1 < -0x80000000 */ 509 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); 510 tcg_gen_or_i64(t2, t2, t3); 511 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2); 512 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 513 /* Calc SV bit */ 514 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 515 /* Calc AV/SAV bits */ 516 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 517 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 518 /* calc SAV */ 519 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 520 } 521 522 static inline void gen_maddi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con) 523 { 524 TCGv temp = tcg_constant_i32(con); 525 gen_madd32_d(ret, r1, r2, temp); 526 } 527 528 static inline void 529 gen_madd64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 530 TCGv r3) 531 { 532 TCGv t1 = tcg_temp_new(); 533 TCGv t2 = tcg_temp_new(); 534 TCGv t3 = tcg_temp_new(); 535 TCGv t4 = tcg_temp_new(); 536 537 tcg_gen_muls2_tl(t1, t2, r1, r3); 538 /* only the add can overflow */ 539 tcg_gen_add2_tl(t3, t4, r2_low, r2_high, t1, t2); 540 /* calc V bit */ 541 tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high); 542 tcg_gen_xor_tl(t1, r2_high, t2); 543 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t1); 544 /* Calc SV bit */ 545 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 546 /* Calc AV/SAV bits */ 547 tcg_gen_add_tl(cpu_PSW_AV, t4, t4); 548 tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV); 549 /* calc SAV */ 550 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 551 /* write back the result */ 552 tcg_gen_mov_tl(ret_low, t3); 553 tcg_gen_mov_tl(ret_high, t4); 554 } 555 556 static inline void 557 gen_maddu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 558 TCGv r3) 559 { 560 TCGv_i64 t1 = tcg_temp_new_i64(); 561 TCGv_i64 t2 = tcg_temp_new_i64(); 562 TCGv_i64 t3 = tcg_temp_new_i64(); 563 564 tcg_gen_extu_i32_i64(t1, r1); 565 tcg_gen_concat_i32_i64(t2, r2_low, r2_high); 566 tcg_gen_extu_i32_i64(t3, r3); 567 568 tcg_gen_mul_i64(t1, t1, t3); 569 tcg_gen_add_i64(t2, t2, t1); 570 /* write back result */ 571 tcg_gen_extr_i64_i32(ret_low, ret_high, t2); 572 /* only the add overflows, if t2 < t1 573 calc V bit */ 574 tcg_gen_setcond_i64(TCG_COND_LTU, t2, t2, t1); 575 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2); 576 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 577 /* Calc SV bit */ 578 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 579 /* Calc AV/SAV bits */ 580 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 581 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); 582 /* calc SAV */ 583 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 584 } 585 586 static inline void 587 gen_maddi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 588 int32_t con) 589 { 590 TCGv temp = tcg_constant_i32(con); 591 gen_madd64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); 592 } 593 594 static inline void 595 gen_maddui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 596 int32_t con) 597 { 598 TCGv temp = tcg_constant_i32(con); 599 gen_maddu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); 600 } 601 602 static inline void 603 gen_madd_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 604 TCGv r3, uint32_t n, uint32_t mode) 605 { 606 TCGv t_n = tcg_constant_i32(n); 607 TCGv temp = tcg_temp_new(); 608 TCGv temp2 = tcg_temp_new(); 609 TCGv_i64 temp64 = tcg_temp_new_i64(); 610 switch (mode) { 611 case MODE_LL: 612 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 613 break; 614 case MODE_LU: 615 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 616 break; 617 case MODE_UL: 618 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 619 break; 620 case MODE_UU: 621 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 622 break; 623 } 624 tcg_gen_extr_i64_i32(temp, temp2, temp64); 625 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, 626 tcg_gen_add_tl, tcg_gen_add_tl); 627 } 628 629 static inline void 630 gen_maddsu_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 631 TCGv r3, uint32_t n, uint32_t mode) 632 { 633 TCGv t_n = tcg_constant_i32(n); 634 TCGv temp = tcg_temp_new(); 635 TCGv temp2 = tcg_temp_new(); 636 TCGv_i64 temp64 = tcg_temp_new_i64(); 637 switch (mode) { 638 case MODE_LL: 639 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 640 break; 641 case MODE_LU: 642 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 643 break; 644 case MODE_UL: 645 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 646 break; 647 case MODE_UU: 648 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 649 break; 650 } 651 tcg_gen_extr_i64_i32(temp, temp2, temp64); 652 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, 653 tcg_gen_sub_tl, tcg_gen_add_tl); 654 } 655 656 static inline void 657 gen_maddsum_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 658 TCGv r3, uint32_t n, uint32_t mode) 659 { 660 TCGv t_n = tcg_constant_i32(n); 661 TCGv_i64 temp64 = tcg_temp_new_i64(); 662 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 663 TCGv_i64 temp64_3 = tcg_temp_new_i64(); 664 switch (mode) { 665 case MODE_LL: 666 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 667 break; 668 case MODE_LU: 669 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 670 break; 671 case MODE_UL: 672 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 673 break; 674 case MODE_UU: 675 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 676 break; 677 } 678 tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high); 679 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ 680 tcg_gen_ext32s_i64(temp64, temp64); /* low */ 681 tcg_gen_sub_i64(temp64, temp64_2, temp64); 682 tcg_gen_shli_i64(temp64, temp64, 16); 683 684 gen_add64_d(temp64_2, temp64_3, temp64); 685 /* write back result */ 686 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2); 687 } 688 689 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2); 690 691 static inline void 692 gen_madds_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 693 TCGv r3, uint32_t n, uint32_t mode) 694 { 695 TCGv t_n = tcg_constant_i32(n); 696 TCGv temp = tcg_temp_new(); 697 TCGv temp2 = tcg_temp_new(); 698 TCGv temp3 = tcg_temp_new(); 699 TCGv_i64 temp64 = tcg_temp_new_i64(); 700 701 switch (mode) { 702 case MODE_LL: 703 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 704 break; 705 case MODE_LU: 706 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 707 break; 708 case MODE_UL: 709 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 710 break; 711 case MODE_UU: 712 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 713 break; 714 } 715 tcg_gen_extr_i64_i32(temp, temp2, temp64); 716 gen_adds(ret_low, r1_low, temp); 717 tcg_gen_mov_tl(temp, cpu_PSW_V); 718 tcg_gen_mov_tl(temp3, cpu_PSW_AV); 719 gen_adds(ret_high, r1_high, temp2); 720 /* combine v bits */ 721 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); 722 /* combine av bits */ 723 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); 724 } 725 726 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2); 727 728 static inline void 729 gen_maddsus_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 730 TCGv r3, uint32_t n, uint32_t mode) 731 { 732 TCGv t_n = tcg_constant_i32(n); 733 TCGv temp = tcg_temp_new(); 734 TCGv temp2 = tcg_temp_new(); 735 TCGv temp3 = tcg_temp_new(); 736 TCGv_i64 temp64 = tcg_temp_new_i64(); 737 738 switch (mode) { 739 case MODE_LL: 740 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 741 break; 742 case MODE_LU: 743 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 744 break; 745 case MODE_UL: 746 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 747 break; 748 case MODE_UU: 749 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 750 break; 751 } 752 tcg_gen_extr_i64_i32(temp, temp2, temp64); 753 gen_subs(ret_low, r1_low, temp); 754 tcg_gen_mov_tl(temp, cpu_PSW_V); 755 tcg_gen_mov_tl(temp3, cpu_PSW_AV); 756 gen_adds(ret_high, r1_high, temp2); 757 /* combine v bits */ 758 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); 759 /* combine av bits */ 760 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); 761 } 762 763 static inline void 764 gen_maddsums_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 765 TCGv r3, uint32_t n, uint32_t mode) 766 { 767 TCGv t_n = tcg_constant_i32(n); 768 TCGv_i64 temp64 = tcg_temp_new_i64(); 769 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 770 771 switch (mode) { 772 case MODE_LL: 773 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 774 break; 775 case MODE_LU: 776 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 777 break; 778 case MODE_UL: 779 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 780 break; 781 case MODE_UU: 782 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 783 break; 784 } 785 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ 786 tcg_gen_ext32s_i64(temp64, temp64); /* low */ 787 tcg_gen_sub_i64(temp64, temp64_2, temp64); 788 tcg_gen_shli_i64(temp64, temp64, 16); 789 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 790 791 gen_helper_add64_ssov(temp64, tcg_env, temp64_2, temp64); 792 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 793 } 794 795 796 static inline void 797 gen_maddm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 798 TCGv r3, uint32_t n, uint32_t mode) 799 { 800 TCGv t_n = tcg_constant_i32(n); 801 TCGv_i64 temp64 = tcg_temp_new_i64(); 802 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 803 TCGv_i64 temp64_3 = tcg_temp_new_i64(); 804 switch (mode) { 805 case MODE_LL: 806 GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n); 807 break; 808 case MODE_LU: 809 GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n); 810 break; 811 case MODE_UL: 812 GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n); 813 break; 814 case MODE_UU: 815 GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n); 816 break; 817 } 818 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 819 gen_add64_d(temp64_3, temp64_2, temp64); 820 /* write back result */ 821 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3); 822 } 823 824 static inline void 825 gen_maddms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 826 TCGv r3, uint32_t n, uint32_t mode) 827 { 828 TCGv t_n = tcg_constant_i32(n); 829 TCGv_i64 temp64 = tcg_temp_new_i64(); 830 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 831 switch (mode) { 832 case MODE_LL: 833 GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n); 834 break; 835 case MODE_LU: 836 GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n); 837 break; 838 case MODE_UL: 839 GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n); 840 break; 841 case MODE_UU: 842 GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n); 843 break; 844 } 845 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 846 gen_helper_add64_ssov(temp64, tcg_env, temp64_2, temp64); 847 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 848 } 849 850 static inline void 851 gen_maddr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, 852 uint32_t mode) 853 { 854 TCGv t_n = tcg_constant_i32(n); 855 TCGv_i64 temp64 = tcg_temp_new_i64(); 856 switch (mode) { 857 case MODE_LL: 858 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 859 break; 860 case MODE_LU: 861 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 862 break; 863 case MODE_UL: 864 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 865 break; 866 case MODE_UU: 867 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 868 break; 869 } 870 gen_helper_addr_h(ret, tcg_env, temp64, r1_low, r1_high); 871 } 872 873 static inline void 874 gen_maddr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 875 { 876 TCGv temp = tcg_temp_new(); 877 TCGv temp2 = tcg_temp_new(); 878 879 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 880 tcg_gen_shli_tl(temp, r1, 16); 881 gen_maddr64_h(ret, temp, temp2, r2, r3, n, mode); 882 } 883 884 static inline void 885 gen_maddsur32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 886 { 887 TCGv t_n = tcg_constant_i32(n); 888 TCGv temp = tcg_temp_new(); 889 TCGv temp2 = tcg_temp_new(); 890 TCGv_i64 temp64 = tcg_temp_new_i64(); 891 switch (mode) { 892 case MODE_LL: 893 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 894 break; 895 case MODE_LU: 896 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 897 break; 898 case MODE_UL: 899 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 900 break; 901 case MODE_UU: 902 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 903 break; 904 } 905 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 906 tcg_gen_shli_tl(temp, r1, 16); 907 gen_helper_addsur_h(ret, tcg_env, temp64, temp, temp2); 908 } 909 910 911 static inline void 912 gen_maddr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, 913 uint32_t n, uint32_t mode) 914 { 915 TCGv t_n = tcg_constant_i32(n); 916 TCGv_i64 temp64 = tcg_temp_new_i64(); 917 switch (mode) { 918 case MODE_LL: 919 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 920 break; 921 case MODE_LU: 922 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 923 break; 924 case MODE_UL: 925 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 926 break; 927 case MODE_UU: 928 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 929 break; 930 } 931 gen_helper_addr_h_ssov(ret, tcg_env, temp64, r1_low, r1_high); 932 } 933 934 static inline void 935 gen_maddr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 936 { 937 TCGv temp = tcg_temp_new(); 938 TCGv temp2 = tcg_temp_new(); 939 940 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 941 tcg_gen_shli_tl(temp, r1, 16); 942 gen_maddr64s_h(ret, temp, temp2, r2, r3, n, mode); 943 } 944 945 static inline void 946 gen_maddsur32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 947 { 948 TCGv t_n = tcg_constant_i32(n); 949 TCGv temp = tcg_temp_new(); 950 TCGv temp2 = tcg_temp_new(); 951 TCGv_i64 temp64 = tcg_temp_new_i64(); 952 switch (mode) { 953 case MODE_LL: 954 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 955 break; 956 case MODE_LU: 957 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 958 break; 959 case MODE_UL: 960 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 961 break; 962 case MODE_UU: 963 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 964 break; 965 } 966 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 967 tcg_gen_shli_tl(temp, r1, 16); 968 gen_helper_addsur_h_ssov(ret, tcg_env, temp64, temp, temp2); 969 } 970 971 static inline void 972 gen_maddr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) 973 { 974 TCGv t_n = tcg_constant_i32(n); 975 gen_helper_maddr_q(ret, tcg_env, r1, r2, r3, t_n); 976 } 977 978 static inline void 979 gen_maddrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) 980 { 981 TCGv t_n = tcg_constant_i32(n); 982 gen_helper_maddr_q_ssov(ret, tcg_env, r1, r2, r3, t_n); 983 } 984 985 static inline void 986 gen_madd32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, 987 uint32_t up_shift) 988 { 989 TCGv temp = tcg_temp_new(); 990 TCGv temp2 = tcg_temp_new(); 991 TCGv temp3 = tcg_temp_new(); 992 TCGv_i64 t1 = tcg_temp_new_i64(); 993 TCGv_i64 t2 = tcg_temp_new_i64(); 994 TCGv_i64 t3 = tcg_temp_new_i64(); 995 996 tcg_gen_ext_i32_i64(t2, arg2); 997 tcg_gen_ext_i32_i64(t3, arg3); 998 999 tcg_gen_mul_i64(t2, t2, t3); 1000 tcg_gen_shli_i64(t2, t2, n); 1001 1002 tcg_gen_ext_i32_i64(t1, arg1); 1003 tcg_gen_sari_i64(t2, t2, up_shift); 1004 1005 tcg_gen_add_i64(t3, t1, t2); 1006 tcg_gen_extrl_i64_i32(temp3, t3); 1007 /* calc v bit */ 1008 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); 1009 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); 1010 tcg_gen_or_i64(t1, t1, t2); 1011 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1); 1012 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 1013 /* We produce an overflow on the host if the mul before was 1014 (0x80000000 * 0x80000000) << 1). If this is the 1015 case, we negate the ovf. */ 1016 if (n == 1) { 1017 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000); 1018 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3); 1019 tcg_gen_and_tl(temp, temp, temp2); 1020 tcg_gen_shli_tl(temp, temp, 31); 1021 /* negate v bit, if special condition */ 1022 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); 1023 } 1024 /* Calc SV bit */ 1025 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1026 /* Calc AV/SAV bits */ 1027 tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3); 1028 tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV); 1029 /* calc SAV */ 1030 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1031 /* write back result */ 1032 tcg_gen_mov_tl(ret, temp3); 1033 } 1034 1035 static inline void 1036 gen_m16add32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) 1037 { 1038 TCGv temp = tcg_temp_new(); 1039 TCGv temp2 = tcg_temp_new(); 1040 if (n == 0) { 1041 tcg_gen_mul_tl(temp, arg2, arg3); 1042 } else { /* n is expected to be 1 */ 1043 tcg_gen_mul_tl(temp, arg2, arg3); 1044 tcg_gen_shli_tl(temp, temp, 1); 1045 /* catch special case r1 = r2 = 0x8000 */ 1046 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1047 tcg_gen_sub_tl(temp, temp, temp2); 1048 } 1049 gen_add_d(ret, arg1, temp); 1050 } 1051 1052 static inline void 1053 gen_m16adds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) 1054 { 1055 TCGv temp = tcg_temp_new(); 1056 TCGv temp2 = tcg_temp_new(); 1057 if (n == 0) { 1058 tcg_gen_mul_tl(temp, arg2, arg3); 1059 } else { /* n is expected to be 1 */ 1060 tcg_gen_mul_tl(temp, arg2, arg3); 1061 tcg_gen_shli_tl(temp, temp, 1); 1062 /* catch special case r1 = r2 = 0x8000 */ 1063 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1064 tcg_gen_sub_tl(temp, temp, temp2); 1065 } 1066 gen_adds(ret, arg1, temp); 1067 } 1068 1069 static inline void 1070 gen_m16add64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1071 TCGv arg3, uint32_t n) 1072 { 1073 TCGv temp = tcg_temp_new(); 1074 TCGv temp2 = tcg_temp_new(); 1075 TCGv_i64 t1 = tcg_temp_new_i64(); 1076 TCGv_i64 t2 = tcg_temp_new_i64(); 1077 TCGv_i64 t3 = tcg_temp_new_i64(); 1078 1079 if (n == 0) { 1080 tcg_gen_mul_tl(temp, arg2, arg3); 1081 } else { /* n is expected to be 1 */ 1082 tcg_gen_mul_tl(temp, arg2, arg3); 1083 tcg_gen_shli_tl(temp, temp, 1); 1084 /* catch special case r1 = r2 = 0x8000 */ 1085 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1086 tcg_gen_sub_tl(temp, temp, temp2); 1087 } 1088 tcg_gen_ext_i32_i64(t2, temp); 1089 tcg_gen_shli_i64(t2, t2, 16); 1090 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1091 gen_add64_d(t3, t1, t2); 1092 /* write back result */ 1093 tcg_gen_extr_i64_i32(rl, rh, t3); 1094 } 1095 1096 static inline void 1097 gen_m16adds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1098 TCGv arg3, uint32_t n) 1099 { 1100 TCGv temp = tcg_temp_new(); 1101 TCGv temp2 = tcg_temp_new(); 1102 TCGv_i64 t1 = tcg_temp_new_i64(); 1103 TCGv_i64 t2 = tcg_temp_new_i64(); 1104 1105 if (n == 0) { 1106 tcg_gen_mul_tl(temp, arg2, arg3); 1107 } else { /* n is expected to be 1 */ 1108 tcg_gen_mul_tl(temp, arg2, arg3); 1109 tcg_gen_shli_tl(temp, temp, 1); 1110 /* catch special case r1 = r2 = 0x8000 */ 1111 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1112 tcg_gen_sub_tl(temp, temp, temp2); 1113 } 1114 tcg_gen_ext_i32_i64(t2, temp); 1115 tcg_gen_shli_i64(t2, t2, 16); 1116 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1117 1118 gen_helper_add64_ssov(t1, tcg_env, t1, t2); 1119 tcg_gen_extr_i64_i32(rl, rh, t1); 1120 } 1121 1122 static inline void 1123 gen_madd64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1124 TCGv arg3, uint32_t n) 1125 { 1126 TCGv_i64 t1 = tcg_temp_new_i64(); 1127 TCGv_i64 t2 = tcg_temp_new_i64(); 1128 TCGv_i64 t3 = tcg_temp_new_i64(); 1129 TCGv_i64 t4 = tcg_temp_new_i64(); 1130 TCGv temp, temp2; 1131 1132 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1133 tcg_gen_ext_i32_i64(t2, arg2); 1134 tcg_gen_ext_i32_i64(t3, arg3); 1135 1136 tcg_gen_mul_i64(t2, t2, t3); 1137 if (n != 0) { 1138 tcg_gen_shli_i64(t2, t2, 1); 1139 } 1140 tcg_gen_add_i64(t4, t1, t2); 1141 /* calc v bit */ 1142 tcg_gen_xor_i64(t3, t4, t1); 1143 tcg_gen_xor_i64(t2, t1, t2); 1144 tcg_gen_andc_i64(t3, t3, t2); 1145 tcg_gen_extrh_i64_i32(cpu_PSW_V, t3); 1146 /* We produce an overflow on the host if the mul before was 1147 (0x80000000 * 0x80000000) << 1). If this is the 1148 case, we negate the ovf. */ 1149 if (n == 1) { 1150 temp = tcg_temp_new(); 1151 temp2 = tcg_temp_new(); 1152 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000); 1153 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3); 1154 tcg_gen_and_tl(temp, temp, temp2); 1155 tcg_gen_shli_tl(temp, temp, 31); 1156 /* negate v bit, if special condition */ 1157 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); 1158 } 1159 /* write back result */ 1160 tcg_gen_extr_i64_i32(rl, rh, t4); 1161 /* Calc SV bit */ 1162 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1163 /* Calc AV/SAV bits */ 1164 tcg_gen_add_tl(cpu_PSW_AV, rh, rh); 1165 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV); 1166 /* calc SAV */ 1167 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1168 } 1169 1170 static inline void 1171 gen_madds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, 1172 uint32_t up_shift) 1173 { 1174 TCGv_i64 t1 = tcg_temp_new_i64(); 1175 TCGv_i64 t2 = tcg_temp_new_i64(); 1176 TCGv_i64 t3 = tcg_temp_new_i64(); 1177 1178 tcg_gen_ext_i32_i64(t1, arg1); 1179 tcg_gen_ext_i32_i64(t2, arg2); 1180 tcg_gen_ext_i32_i64(t3, arg3); 1181 1182 tcg_gen_mul_i64(t2, t2, t3); 1183 tcg_gen_sari_i64(t2, t2, up_shift - n); 1184 1185 gen_helper_madd32_q_add_ssov(ret, tcg_env, t1, t2); 1186 } 1187 1188 static inline void 1189 gen_madds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1190 TCGv arg3, uint32_t n) 1191 { 1192 TCGv_i64 r1 = tcg_temp_new_i64(); 1193 TCGv t_n = tcg_constant_i32(n); 1194 1195 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high); 1196 gen_helper_madd64_q_ssov(r1, tcg_env, r1, arg2, arg3, t_n); 1197 tcg_gen_extr_i64_i32(rl, rh, r1); 1198 } 1199 1200 /* ret = r2 - (r1 * r3); */ 1201 static inline void gen_msub32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3) 1202 { 1203 TCGv_i64 t1 = tcg_temp_new_i64(); 1204 TCGv_i64 t2 = tcg_temp_new_i64(); 1205 TCGv_i64 t3 = tcg_temp_new_i64(); 1206 1207 tcg_gen_ext_i32_i64(t1, r1); 1208 tcg_gen_ext_i32_i64(t2, r2); 1209 tcg_gen_ext_i32_i64(t3, r3); 1210 1211 tcg_gen_mul_i64(t1, t1, t3); 1212 tcg_gen_sub_i64(t1, t2, t1); 1213 1214 tcg_gen_extrl_i64_i32(ret, t1); 1215 /* calc V 1216 t2 > 0x7fffffff */ 1217 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); 1218 /* result < -0x80000000 */ 1219 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); 1220 tcg_gen_or_i64(t2, t2, t3); 1221 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2); 1222 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 1223 1224 /* Calc SV bit */ 1225 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1226 /* Calc AV/SAV bits */ 1227 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 1228 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 1229 /* calc SAV */ 1230 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1231 } 1232 1233 static inline void gen_msubi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con) 1234 { 1235 TCGv temp = tcg_constant_i32(con); 1236 gen_msub32_d(ret, r1, r2, temp); 1237 } 1238 1239 static inline void 1240 gen_msub64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 1241 TCGv r3) 1242 { 1243 TCGv t1 = tcg_temp_new(); 1244 TCGv t2 = tcg_temp_new(); 1245 TCGv t3 = tcg_temp_new(); 1246 TCGv t4 = tcg_temp_new(); 1247 1248 tcg_gen_muls2_tl(t1, t2, r1, r3); 1249 /* only the sub can overflow */ 1250 tcg_gen_sub2_tl(t3, t4, r2_low, r2_high, t1, t2); 1251 /* calc V bit */ 1252 tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high); 1253 tcg_gen_xor_tl(t1, r2_high, t2); 1254 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, t1); 1255 /* Calc SV bit */ 1256 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1257 /* Calc AV/SAV bits */ 1258 tcg_gen_add_tl(cpu_PSW_AV, t4, t4); 1259 tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV); 1260 /* calc SAV */ 1261 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1262 /* write back the result */ 1263 tcg_gen_mov_tl(ret_low, t3); 1264 tcg_gen_mov_tl(ret_high, t4); 1265 } 1266 1267 static inline void 1268 gen_msubi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 1269 int32_t con) 1270 { 1271 TCGv temp = tcg_constant_i32(con); 1272 gen_msub64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); 1273 } 1274 1275 static inline void 1276 gen_msubu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 1277 TCGv r3) 1278 { 1279 TCGv_i64 t1 = tcg_temp_new_i64(); 1280 TCGv_i64 t2 = tcg_temp_new_i64(); 1281 TCGv_i64 t3 = tcg_temp_new_i64(); 1282 1283 tcg_gen_extu_i32_i64(t1, r1); 1284 tcg_gen_concat_i32_i64(t2, r2_low, r2_high); 1285 tcg_gen_extu_i32_i64(t3, r3); 1286 1287 tcg_gen_mul_i64(t1, t1, t3); 1288 tcg_gen_sub_i64(t3, t2, t1); 1289 tcg_gen_extr_i64_i32(ret_low, ret_high, t3); 1290 /* calc V bit, only the sub can overflow, if t1 > t2 */ 1291 tcg_gen_setcond_i64(TCG_COND_GTU, t1, t1, t2); 1292 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1); 1293 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 1294 /* Calc SV bit */ 1295 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1296 /* Calc AV/SAV bits */ 1297 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 1298 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); 1299 /* calc SAV */ 1300 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1301 } 1302 1303 static inline void 1304 gen_msubui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 1305 int32_t con) 1306 { 1307 TCGv temp = tcg_constant_i32(con); 1308 gen_msubu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); 1309 } 1310 1311 static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2) 1312 { 1313 TCGv temp = tcg_constant_i32(r2); 1314 gen_add_d(ret, r1, temp); 1315 } 1316 1317 /* calculate the carry bit too */ 1318 static inline void gen_add_CC(TCGv ret, TCGv r1, TCGv r2) 1319 { 1320 TCGv t0 = tcg_temp_new_i32(); 1321 TCGv result = tcg_temp_new_i32(); 1322 1323 tcg_gen_movi_tl(t0, 0); 1324 /* Addition and set C/V/SV bits */ 1325 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, r2, t0); 1326 /* calc V bit */ 1327 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 1328 tcg_gen_xor_tl(t0, r1, r2); 1329 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0); 1330 /* Calc SV bit */ 1331 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1332 /* Calc AV/SAV bits */ 1333 tcg_gen_add_tl(cpu_PSW_AV, result, result); 1334 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 1335 /* calc SAV */ 1336 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1337 /* write back result */ 1338 tcg_gen_mov_tl(ret, result); 1339 } 1340 1341 static inline void gen_addi_CC(TCGv ret, TCGv r1, int32_t con) 1342 { 1343 TCGv temp = tcg_constant_i32(con); 1344 gen_add_CC(ret, r1, temp); 1345 } 1346 1347 static inline void gen_addc_CC(TCGv ret, TCGv r1, TCGv r2) 1348 { 1349 TCGv carry = tcg_temp_new_i32(); 1350 TCGv t0 = tcg_temp_new_i32(); 1351 TCGv result = tcg_temp_new_i32(); 1352 1353 tcg_gen_movi_tl(t0, 0); 1354 tcg_gen_setcondi_tl(TCG_COND_NE, carry, cpu_PSW_C, 0); 1355 /* Addition, carry and set C/V/SV bits */ 1356 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, carry, t0); 1357 tcg_gen_add2_i32(result, cpu_PSW_C, result, cpu_PSW_C, r2, t0); 1358 /* calc V bit */ 1359 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 1360 tcg_gen_xor_tl(t0, r1, r2); 1361 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0); 1362 /* Calc SV bit */ 1363 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1364 /* Calc AV/SAV bits */ 1365 tcg_gen_add_tl(cpu_PSW_AV, result, result); 1366 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 1367 /* calc SAV */ 1368 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1369 /* write back result */ 1370 tcg_gen_mov_tl(ret, result); 1371 } 1372 1373 static inline void gen_addci_CC(TCGv ret, TCGv r1, int32_t con) 1374 { 1375 TCGv temp = tcg_constant_i32(con); 1376 gen_addc_CC(ret, r1, temp); 1377 } 1378 1379 static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3, 1380 TCGv r4) 1381 { 1382 TCGv temp = tcg_temp_new(); 1383 TCGv temp2 = tcg_temp_new(); 1384 TCGv result = tcg_temp_new(); 1385 TCGv mask = tcg_temp_new(); 1386 TCGv t0 = tcg_constant_i32(0); 1387 1388 /* create mask for sticky bits */ 1389 tcg_gen_setcond_tl(cond, mask, r4, t0); 1390 tcg_gen_shli_tl(mask, mask, 31); 1391 1392 tcg_gen_add_tl(result, r1, r2); 1393 /* Calc PSW_V */ 1394 tcg_gen_xor_tl(temp, result, r1); 1395 tcg_gen_xor_tl(temp2, r1, r2); 1396 tcg_gen_andc_tl(temp, temp, temp2); 1397 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V); 1398 /* Set PSW_SV */ 1399 tcg_gen_and_tl(temp, temp, mask); 1400 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV); 1401 /* calc AV bit */ 1402 tcg_gen_add_tl(temp, result, result); 1403 tcg_gen_xor_tl(temp, temp, result); 1404 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV); 1405 /* calc SAV bit */ 1406 tcg_gen_and_tl(temp, temp, mask); 1407 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV); 1408 /* write back result */ 1409 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1); 1410 } 1411 1412 static inline void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2, 1413 TCGv r3, TCGv r4) 1414 { 1415 TCGv temp = tcg_constant_i32(r2); 1416 gen_cond_add(cond, r1, temp, r3, r4); 1417 } 1418 1419 static inline void gen_sub_d(TCGv ret, TCGv r1, TCGv r2) 1420 { 1421 TCGv temp = tcg_temp_new_i32(); 1422 TCGv result = tcg_temp_new_i32(); 1423 1424 tcg_gen_sub_tl(result, r1, r2); 1425 /* calc V bit */ 1426 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 1427 tcg_gen_xor_tl(temp, r1, r2); 1428 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp); 1429 /* calc SV bit */ 1430 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1431 /* Calc AV bit */ 1432 tcg_gen_add_tl(cpu_PSW_AV, result, result); 1433 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 1434 /* calc SAV bit */ 1435 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1436 /* write back result */ 1437 tcg_gen_mov_tl(ret, result); 1438 } 1439 1440 static inline void 1441 gen_sub64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2) 1442 { 1443 TCGv temp = tcg_temp_new(); 1444 TCGv_i64 t0 = tcg_temp_new_i64(); 1445 TCGv_i64 t1 = tcg_temp_new_i64(); 1446 TCGv_i64 result = tcg_temp_new_i64(); 1447 1448 tcg_gen_sub_i64(result, r1, r2); 1449 /* calc v bit */ 1450 tcg_gen_xor_i64(t1, result, r1); 1451 tcg_gen_xor_i64(t0, r1, r2); 1452 tcg_gen_and_i64(t1, t1, t0); 1453 tcg_gen_extrh_i64_i32(cpu_PSW_V, t1); 1454 /* calc SV bit */ 1455 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1456 /* calc AV/SAV bits */ 1457 tcg_gen_extrh_i64_i32(temp, result); 1458 tcg_gen_add_tl(cpu_PSW_AV, temp, temp); 1459 tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV); 1460 /* calc SAV */ 1461 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1462 /* write back result */ 1463 tcg_gen_mov_i64(ret, result); 1464 } 1465 1466 static inline void gen_sub_CC(TCGv ret, TCGv r1, TCGv r2) 1467 { 1468 TCGv result = tcg_temp_new(); 1469 TCGv temp = tcg_temp_new(); 1470 1471 tcg_gen_sub_tl(result, r1, r2); 1472 /* calc C bit */ 1473 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_PSW_C, r1, r2); 1474 /* calc V bit */ 1475 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 1476 tcg_gen_xor_tl(temp, r1, r2); 1477 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp); 1478 /* calc SV bit */ 1479 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1480 /* Calc AV bit */ 1481 tcg_gen_add_tl(cpu_PSW_AV, result, result); 1482 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 1483 /* calc SAV bit */ 1484 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1485 /* write back result */ 1486 tcg_gen_mov_tl(ret, result); 1487 } 1488 1489 static inline void gen_subc_CC(TCGv ret, TCGv r1, TCGv r2) 1490 { 1491 TCGv temp = tcg_temp_new(); 1492 tcg_gen_not_tl(temp, r2); 1493 gen_addc_CC(ret, r1, temp); 1494 } 1495 1496 static inline void gen_cond_sub(TCGCond cond, TCGv r1, TCGv r2, TCGv r3, 1497 TCGv r4) 1498 { 1499 TCGv temp = tcg_temp_new(); 1500 TCGv temp2 = tcg_temp_new(); 1501 TCGv result = tcg_temp_new(); 1502 TCGv mask = tcg_temp_new(); 1503 TCGv t0 = tcg_constant_i32(0); 1504 1505 /* create mask for sticky bits */ 1506 tcg_gen_setcond_tl(cond, mask, r4, t0); 1507 tcg_gen_shli_tl(mask, mask, 31); 1508 1509 tcg_gen_sub_tl(result, r1, r2); 1510 /* Calc PSW_V */ 1511 tcg_gen_xor_tl(temp, result, r1); 1512 tcg_gen_xor_tl(temp2, r1, r2); 1513 tcg_gen_and_tl(temp, temp, temp2); 1514 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V); 1515 /* Set PSW_SV */ 1516 tcg_gen_and_tl(temp, temp, mask); 1517 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV); 1518 /* calc AV bit */ 1519 tcg_gen_add_tl(temp, result, result); 1520 tcg_gen_xor_tl(temp, temp, result); 1521 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV); 1522 /* calc SAV bit */ 1523 tcg_gen_and_tl(temp, temp, mask); 1524 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV); 1525 /* write back result */ 1526 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1); 1527 } 1528 1529 static inline void 1530 gen_msub_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1531 TCGv r3, uint32_t n, uint32_t mode) 1532 { 1533 TCGv t_n = tcg_constant_i32(n); 1534 TCGv temp = tcg_temp_new(); 1535 TCGv temp2 = tcg_temp_new(); 1536 TCGv_i64 temp64 = tcg_temp_new_i64(); 1537 switch (mode) { 1538 case MODE_LL: 1539 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 1540 break; 1541 case MODE_LU: 1542 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 1543 break; 1544 case MODE_UL: 1545 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 1546 break; 1547 case MODE_UU: 1548 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 1549 break; 1550 } 1551 tcg_gen_extr_i64_i32(temp, temp2, temp64); 1552 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, 1553 tcg_gen_sub_tl, tcg_gen_sub_tl); 1554 } 1555 1556 static inline void 1557 gen_msubs_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1558 TCGv r3, uint32_t n, uint32_t mode) 1559 { 1560 TCGv t_n = tcg_constant_i32(n); 1561 TCGv temp = tcg_temp_new(); 1562 TCGv temp2 = tcg_temp_new(); 1563 TCGv temp3 = tcg_temp_new(); 1564 TCGv_i64 temp64 = tcg_temp_new_i64(); 1565 1566 switch (mode) { 1567 case MODE_LL: 1568 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 1569 break; 1570 case MODE_LU: 1571 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 1572 break; 1573 case MODE_UL: 1574 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 1575 break; 1576 case MODE_UU: 1577 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 1578 break; 1579 } 1580 tcg_gen_extr_i64_i32(temp, temp2, temp64); 1581 gen_subs(ret_low, r1_low, temp); 1582 tcg_gen_mov_tl(temp, cpu_PSW_V); 1583 tcg_gen_mov_tl(temp3, cpu_PSW_AV); 1584 gen_subs(ret_high, r1_high, temp2); 1585 /* combine v bits */ 1586 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); 1587 /* combine av bits */ 1588 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); 1589 } 1590 1591 static inline void 1592 gen_msubm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1593 TCGv r3, uint32_t n, uint32_t mode) 1594 { 1595 TCGv t_n = tcg_constant_i32(n); 1596 TCGv_i64 temp64 = tcg_temp_new_i64(); 1597 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 1598 TCGv_i64 temp64_3 = tcg_temp_new_i64(); 1599 switch (mode) { 1600 case MODE_LL: 1601 GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n); 1602 break; 1603 case MODE_LU: 1604 GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n); 1605 break; 1606 case MODE_UL: 1607 GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n); 1608 break; 1609 case MODE_UU: 1610 GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n); 1611 break; 1612 } 1613 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 1614 gen_sub64_d(temp64_3, temp64_2, temp64); 1615 /* write back result */ 1616 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3); 1617 } 1618 1619 static inline void 1620 gen_msubms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1621 TCGv r3, uint32_t n, uint32_t mode) 1622 { 1623 TCGv t_n = tcg_constant_i32(n); 1624 TCGv_i64 temp64 = tcg_temp_new_i64(); 1625 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 1626 switch (mode) { 1627 case MODE_LL: 1628 GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n); 1629 break; 1630 case MODE_LU: 1631 GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n); 1632 break; 1633 case MODE_UL: 1634 GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n); 1635 break; 1636 case MODE_UU: 1637 GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n); 1638 break; 1639 } 1640 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 1641 gen_helper_sub64_ssov(temp64, tcg_env, temp64_2, temp64); 1642 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 1643 } 1644 1645 static inline void 1646 gen_msubr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, 1647 uint32_t mode) 1648 { 1649 TCGv t_n = tcg_constant_i32(n); 1650 TCGv_i64 temp64 = tcg_temp_new_i64(); 1651 switch (mode) { 1652 case MODE_LL: 1653 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 1654 break; 1655 case MODE_LU: 1656 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 1657 break; 1658 case MODE_UL: 1659 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 1660 break; 1661 case MODE_UU: 1662 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 1663 break; 1664 } 1665 gen_helper_subr_h(ret, tcg_env, temp64, r1_low, r1_high); 1666 } 1667 1668 static inline void 1669 gen_msubr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 1670 { 1671 TCGv temp = tcg_temp_new(); 1672 TCGv temp2 = tcg_temp_new(); 1673 1674 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 1675 tcg_gen_shli_tl(temp, r1, 16); 1676 gen_msubr64_h(ret, temp, temp2, r2, r3, n, mode); 1677 } 1678 1679 static inline void 1680 gen_msubr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, 1681 uint32_t n, uint32_t mode) 1682 { 1683 TCGv t_n = tcg_constant_i32(n); 1684 TCGv_i64 temp64 = tcg_temp_new_i64(); 1685 switch (mode) { 1686 case MODE_LL: 1687 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 1688 break; 1689 case MODE_LU: 1690 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 1691 break; 1692 case MODE_UL: 1693 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 1694 break; 1695 case MODE_UU: 1696 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 1697 break; 1698 } 1699 gen_helper_subr_h_ssov(ret, tcg_env, temp64, r1_low, r1_high); 1700 } 1701 1702 static inline void 1703 gen_msubr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 1704 { 1705 TCGv temp = tcg_temp_new(); 1706 TCGv temp2 = tcg_temp_new(); 1707 1708 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 1709 tcg_gen_shli_tl(temp, r1, 16); 1710 gen_msubr64s_h(ret, temp, temp2, r2, r3, n, mode); 1711 } 1712 1713 static inline void 1714 gen_msubr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) 1715 { 1716 TCGv temp = tcg_constant_i32(n); 1717 gen_helper_msubr_q(ret, tcg_env, r1, r2, r3, temp); 1718 } 1719 1720 static inline void 1721 gen_msubrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) 1722 { 1723 TCGv temp = tcg_constant_i32(n); 1724 gen_helper_msubr_q_ssov(ret, tcg_env, r1, r2, r3, temp); 1725 } 1726 1727 static inline void 1728 gen_msub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, 1729 uint32_t up_shift) 1730 { 1731 TCGv temp3 = tcg_temp_new(); 1732 TCGv_i64 t1 = tcg_temp_new_i64(); 1733 TCGv_i64 t2 = tcg_temp_new_i64(); 1734 TCGv_i64 t3 = tcg_temp_new_i64(); 1735 TCGv_i64 t4 = tcg_temp_new_i64(); 1736 1737 tcg_gen_ext_i32_i64(t2, arg2); 1738 tcg_gen_ext_i32_i64(t3, arg3); 1739 1740 tcg_gen_mul_i64(t2, t2, t3); 1741 1742 tcg_gen_ext_i32_i64(t1, arg1); 1743 /* if we shift part of the fraction out, we need to round up */ 1744 tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1); 1745 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); 1746 tcg_gen_sari_i64(t2, t2, up_shift - n); 1747 tcg_gen_add_i64(t2, t2, t4); 1748 1749 tcg_gen_sub_i64(t3, t1, t2); 1750 tcg_gen_extrl_i64_i32(temp3, t3); 1751 /* calc v bit */ 1752 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); 1753 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); 1754 tcg_gen_or_i64(t1, t1, t2); 1755 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1); 1756 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 1757 /* Calc SV bit */ 1758 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1759 /* Calc AV/SAV bits */ 1760 tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3); 1761 tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV); 1762 /* calc SAV */ 1763 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1764 /* write back result */ 1765 tcg_gen_mov_tl(ret, temp3); 1766 } 1767 1768 static inline void 1769 gen_m16sub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) 1770 { 1771 TCGv temp = tcg_temp_new(); 1772 TCGv temp2 = tcg_temp_new(); 1773 if (n == 0) { 1774 tcg_gen_mul_tl(temp, arg2, arg3); 1775 } else { /* n is expected to be 1 */ 1776 tcg_gen_mul_tl(temp, arg2, arg3); 1777 tcg_gen_shli_tl(temp, temp, 1); 1778 /* catch special case r1 = r2 = 0x8000 */ 1779 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1780 tcg_gen_sub_tl(temp, temp, temp2); 1781 } 1782 gen_sub_d(ret, arg1, temp); 1783 } 1784 1785 static inline void 1786 gen_m16subs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) 1787 { 1788 TCGv temp = tcg_temp_new(); 1789 TCGv temp2 = tcg_temp_new(); 1790 if (n == 0) { 1791 tcg_gen_mul_tl(temp, arg2, arg3); 1792 } else { /* n is expected to be 1 */ 1793 tcg_gen_mul_tl(temp, arg2, arg3); 1794 tcg_gen_shli_tl(temp, temp, 1); 1795 /* catch special case r1 = r2 = 0x8000 */ 1796 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1797 tcg_gen_sub_tl(temp, temp, temp2); 1798 } 1799 gen_subs(ret, arg1, temp); 1800 } 1801 1802 static inline void 1803 gen_m16sub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1804 TCGv arg3, uint32_t n) 1805 { 1806 TCGv temp = tcg_temp_new(); 1807 TCGv temp2 = tcg_temp_new(); 1808 TCGv_i64 t1 = tcg_temp_new_i64(); 1809 TCGv_i64 t2 = tcg_temp_new_i64(); 1810 TCGv_i64 t3 = tcg_temp_new_i64(); 1811 1812 if (n == 0) { 1813 tcg_gen_mul_tl(temp, arg2, arg3); 1814 } else { /* n is expected to be 1 */ 1815 tcg_gen_mul_tl(temp, arg2, arg3); 1816 tcg_gen_shli_tl(temp, temp, 1); 1817 /* catch special case r1 = r2 = 0x8000 */ 1818 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1819 tcg_gen_sub_tl(temp, temp, temp2); 1820 } 1821 tcg_gen_ext_i32_i64(t2, temp); 1822 tcg_gen_shli_i64(t2, t2, 16); 1823 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1824 gen_sub64_d(t3, t1, t2); 1825 /* write back result */ 1826 tcg_gen_extr_i64_i32(rl, rh, t3); 1827 } 1828 1829 static inline void 1830 gen_m16subs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1831 TCGv arg3, uint32_t n) 1832 { 1833 TCGv temp = tcg_temp_new(); 1834 TCGv temp2 = tcg_temp_new(); 1835 TCGv_i64 t1 = tcg_temp_new_i64(); 1836 TCGv_i64 t2 = tcg_temp_new_i64(); 1837 1838 if (n == 0) { 1839 tcg_gen_mul_tl(temp, arg2, arg3); 1840 } else { /* n is expected to be 1 */ 1841 tcg_gen_mul_tl(temp, arg2, arg3); 1842 tcg_gen_shli_tl(temp, temp, 1); 1843 /* catch special case r1 = r2 = 0x8000 */ 1844 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1845 tcg_gen_sub_tl(temp, temp, temp2); 1846 } 1847 tcg_gen_ext_i32_i64(t2, temp); 1848 tcg_gen_shli_i64(t2, t2, 16); 1849 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1850 1851 gen_helper_sub64_ssov(t1, tcg_env, t1, t2); 1852 tcg_gen_extr_i64_i32(rl, rh, t1); 1853 } 1854 1855 static inline void 1856 gen_msub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1857 TCGv arg3, uint32_t n) 1858 { 1859 TCGv_i64 t1 = tcg_temp_new_i64(); 1860 TCGv_i64 t2 = tcg_temp_new_i64(); 1861 TCGv_i64 t3 = tcg_temp_new_i64(); 1862 TCGv_i64 t4 = tcg_temp_new_i64(); 1863 TCGv temp, temp2; 1864 1865 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1866 tcg_gen_ext_i32_i64(t2, arg2); 1867 tcg_gen_ext_i32_i64(t3, arg3); 1868 1869 tcg_gen_mul_i64(t2, t2, t3); 1870 if (n != 0) { 1871 tcg_gen_shli_i64(t2, t2, 1); 1872 } 1873 tcg_gen_sub_i64(t4, t1, t2); 1874 /* calc v bit */ 1875 tcg_gen_xor_i64(t3, t4, t1); 1876 tcg_gen_xor_i64(t2, t1, t2); 1877 tcg_gen_and_i64(t3, t3, t2); 1878 tcg_gen_extrh_i64_i32(cpu_PSW_V, t3); 1879 /* We produce an overflow on the host if the mul before was 1880 (0x80000000 * 0x80000000) << 1). If this is the 1881 case, we negate the ovf. */ 1882 if (n == 1) { 1883 temp = tcg_temp_new(); 1884 temp2 = tcg_temp_new(); 1885 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000); 1886 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3); 1887 tcg_gen_and_tl(temp, temp, temp2); 1888 tcg_gen_shli_tl(temp, temp, 31); 1889 /* negate v bit, if special condition */ 1890 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); 1891 } 1892 /* write back result */ 1893 tcg_gen_extr_i64_i32(rl, rh, t4); 1894 /* Calc SV bit */ 1895 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1896 /* Calc AV/SAV bits */ 1897 tcg_gen_add_tl(cpu_PSW_AV, rh, rh); 1898 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV); 1899 /* calc SAV */ 1900 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1901 } 1902 1903 static inline void 1904 gen_msubs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, 1905 uint32_t up_shift) 1906 { 1907 TCGv_i64 t1 = tcg_temp_new_i64(); 1908 TCGv_i64 t2 = tcg_temp_new_i64(); 1909 TCGv_i64 t3 = tcg_temp_new_i64(); 1910 TCGv_i64 t4 = tcg_temp_new_i64(); 1911 1912 tcg_gen_ext_i32_i64(t1, arg1); 1913 tcg_gen_ext_i32_i64(t2, arg2); 1914 tcg_gen_ext_i32_i64(t3, arg3); 1915 1916 tcg_gen_mul_i64(t2, t2, t3); 1917 /* if we shift part of the fraction out, we need to round up */ 1918 tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1); 1919 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); 1920 tcg_gen_sari_i64(t3, t2, up_shift - n); 1921 tcg_gen_add_i64(t3, t3, t4); 1922 1923 gen_helper_msub32_q_sub_ssov(ret, tcg_env, t1, t3); 1924 } 1925 1926 static inline void 1927 gen_msubs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1928 TCGv arg3, uint32_t n) 1929 { 1930 TCGv_i64 r1 = tcg_temp_new_i64(); 1931 TCGv t_n = tcg_constant_i32(n); 1932 1933 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high); 1934 gen_helper_msub64_q_ssov(r1, tcg_env, r1, arg2, arg3, t_n); 1935 tcg_gen_extr_i64_i32(rl, rh, r1); 1936 } 1937 1938 static inline void 1939 gen_msubad_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1940 TCGv r3, uint32_t n, uint32_t mode) 1941 { 1942 TCGv t_n = tcg_constant_i32(n); 1943 TCGv temp = tcg_temp_new(); 1944 TCGv temp2 = tcg_temp_new(); 1945 TCGv_i64 temp64 = tcg_temp_new_i64(); 1946 switch (mode) { 1947 case MODE_LL: 1948 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 1949 break; 1950 case MODE_LU: 1951 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 1952 break; 1953 case MODE_UL: 1954 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 1955 break; 1956 case MODE_UU: 1957 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 1958 break; 1959 } 1960 tcg_gen_extr_i64_i32(temp, temp2, temp64); 1961 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, 1962 tcg_gen_add_tl, tcg_gen_sub_tl); 1963 } 1964 1965 static inline void 1966 gen_msubadm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1967 TCGv r3, uint32_t n, uint32_t mode) 1968 { 1969 TCGv t_n = tcg_constant_i32(n); 1970 TCGv_i64 temp64 = tcg_temp_new_i64(); 1971 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 1972 TCGv_i64 temp64_3 = tcg_temp_new_i64(); 1973 switch (mode) { 1974 case MODE_LL: 1975 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 1976 break; 1977 case MODE_LU: 1978 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 1979 break; 1980 case MODE_UL: 1981 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 1982 break; 1983 case MODE_UU: 1984 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 1985 break; 1986 } 1987 tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high); 1988 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ 1989 tcg_gen_ext32s_i64(temp64, temp64); /* low */ 1990 tcg_gen_sub_i64(temp64, temp64_2, temp64); 1991 tcg_gen_shli_i64(temp64, temp64, 16); 1992 1993 gen_sub64_d(temp64_2, temp64_3, temp64); 1994 /* write back result */ 1995 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2); 1996 } 1997 1998 static inline void 1999 gen_msubadr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 2000 { 2001 TCGv t_n = tcg_constant_i32(n); 2002 TCGv temp = tcg_temp_new(); 2003 TCGv temp2 = tcg_temp_new(); 2004 TCGv_i64 temp64 = tcg_temp_new_i64(); 2005 switch (mode) { 2006 case MODE_LL: 2007 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 2008 break; 2009 case MODE_LU: 2010 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 2011 break; 2012 case MODE_UL: 2013 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 2014 break; 2015 case MODE_UU: 2016 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 2017 break; 2018 } 2019 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 2020 tcg_gen_shli_tl(temp, r1, 16); 2021 gen_helper_subadr_h(ret, tcg_env, temp64, temp, temp2); 2022 } 2023 2024 static inline void 2025 gen_msubads_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 2026 TCGv r3, uint32_t n, uint32_t mode) 2027 { 2028 TCGv t_n = tcg_constant_i32(n); 2029 TCGv temp = tcg_temp_new(); 2030 TCGv temp2 = tcg_temp_new(); 2031 TCGv temp3 = tcg_temp_new(); 2032 TCGv_i64 temp64 = tcg_temp_new_i64(); 2033 2034 switch (mode) { 2035 case MODE_LL: 2036 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 2037 break; 2038 case MODE_LU: 2039 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 2040 break; 2041 case MODE_UL: 2042 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 2043 break; 2044 case MODE_UU: 2045 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 2046 break; 2047 } 2048 tcg_gen_extr_i64_i32(temp, temp2, temp64); 2049 gen_adds(ret_low, r1_low, temp); 2050 tcg_gen_mov_tl(temp, cpu_PSW_V); 2051 tcg_gen_mov_tl(temp3, cpu_PSW_AV); 2052 gen_subs(ret_high, r1_high, temp2); 2053 /* combine v bits */ 2054 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); 2055 /* combine av bits */ 2056 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); 2057 } 2058 2059 static inline void 2060 gen_msubadms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 2061 TCGv r3, uint32_t n, uint32_t mode) 2062 { 2063 TCGv t_n = tcg_constant_i32(n); 2064 TCGv_i64 temp64 = tcg_temp_new_i64(); 2065 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 2066 2067 switch (mode) { 2068 case MODE_LL: 2069 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 2070 break; 2071 case MODE_LU: 2072 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 2073 break; 2074 case MODE_UL: 2075 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 2076 break; 2077 case MODE_UU: 2078 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 2079 break; 2080 } 2081 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ 2082 tcg_gen_ext32s_i64(temp64, temp64); /* low */ 2083 tcg_gen_sub_i64(temp64, temp64_2, temp64); 2084 tcg_gen_shli_i64(temp64, temp64, 16); 2085 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 2086 2087 gen_helper_sub64_ssov(temp64, tcg_env, temp64_2, temp64); 2088 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2089 } 2090 2091 static inline void 2092 gen_msubadr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 2093 { 2094 TCGv t_n = tcg_constant_i32(n); 2095 TCGv temp = tcg_temp_new(); 2096 TCGv temp2 = tcg_temp_new(); 2097 TCGv_i64 temp64 = tcg_temp_new_i64(); 2098 switch (mode) { 2099 case MODE_LL: 2100 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 2101 break; 2102 case MODE_LU: 2103 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 2104 break; 2105 case MODE_UL: 2106 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 2107 break; 2108 case MODE_UU: 2109 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 2110 break; 2111 } 2112 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 2113 tcg_gen_shli_tl(temp, r1, 16); 2114 gen_helper_subadr_h_ssov(ret, tcg_env, temp64, temp, temp2); 2115 } 2116 2117 static inline void gen_abs(TCGv ret, TCGv r1) 2118 { 2119 tcg_gen_abs_tl(ret, r1); 2120 /* overflow can only happen, if r1 = 0x80000000 */ 2121 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, r1, 0x80000000); 2122 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 2123 /* calc SV bit */ 2124 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2125 /* Calc AV bit */ 2126 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2127 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2128 /* calc SAV bit */ 2129 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2130 } 2131 2132 static inline void gen_absdif(TCGv ret, TCGv r1, TCGv r2) 2133 { 2134 TCGv temp = tcg_temp_new_i32(); 2135 TCGv result = tcg_temp_new_i32(); 2136 2137 tcg_gen_sub_tl(result, r1, r2); 2138 tcg_gen_sub_tl(temp, r2, r1); 2139 tcg_gen_movcond_tl(TCG_COND_GT, result, r1, r2, result, temp); 2140 2141 /* calc V bit */ 2142 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 2143 tcg_gen_xor_tl(temp, result, r2); 2144 tcg_gen_movcond_tl(TCG_COND_GT, cpu_PSW_V, r1, r2, cpu_PSW_V, temp); 2145 tcg_gen_xor_tl(temp, r1, r2); 2146 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp); 2147 /* calc SV bit */ 2148 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2149 /* Calc AV bit */ 2150 tcg_gen_add_tl(cpu_PSW_AV, result, result); 2151 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 2152 /* calc SAV bit */ 2153 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2154 /* write back result */ 2155 tcg_gen_mov_tl(ret, result); 2156 } 2157 2158 static inline void gen_absdifi(TCGv ret, TCGv r1, int32_t con) 2159 { 2160 TCGv temp = tcg_constant_i32(con); 2161 gen_absdif(ret, r1, temp); 2162 } 2163 2164 static inline void gen_absdifsi(TCGv ret, TCGv r1, int32_t con) 2165 { 2166 TCGv temp = tcg_constant_i32(con); 2167 gen_helper_absdif_ssov(ret, tcg_env, r1, temp); 2168 } 2169 2170 static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2) 2171 { 2172 TCGv high = tcg_temp_new(); 2173 TCGv low = tcg_temp_new(); 2174 2175 tcg_gen_muls2_tl(low, high, r1, r2); 2176 tcg_gen_mov_tl(ret, low); 2177 /* calc V bit */ 2178 tcg_gen_sari_tl(low, low, 31); 2179 tcg_gen_setcond_tl(TCG_COND_NE, cpu_PSW_V, high, low); 2180 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 2181 /* calc SV bit */ 2182 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2183 /* Calc AV bit */ 2184 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2185 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2186 /* calc SAV bit */ 2187 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2188 } 2189 2190 static inline void gen_muli_i32s(TCGv ret, TCGv r1, int32_t con) 2191 { 2192 TCGv temp = tcg_constant_i32(con); 2193 gen_mul_i32s(ret, r1, temp); 2194 } 2195 2196 static inline void gen_mul_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2) 2197 { 2198 tcg_gen_muls2_tl(ret_low, ret_high, r1, r2); 2199 /* clear V bit */ 2200 tcg_gen_movi_tl(cpu_PSW_V, 0); 2201 /* calc SV bit */ 2202 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2203 /* Calc AV bit */ 2204 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 2205 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); 2206 /* calc SAV bit */ 2207 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2208 } 2209 2210 static inline void gen_muli_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, 2211 int32_t con) 2212 { 2213 TCGv temp = tcg_constant_i32(con); 2214 gen_mul_i64s(ret_low, ret_high, r1, temp); 2215 } 2216 2217 static inline void gen_mul_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2) 2218 { 2219 tcg_gen_mulu2_tl(ret_low, ret_high, r1, r2); 2220 /* clear V bit */ 2221 tcg_gen_movi_tl(cpu_PSW_V, 0); 2222 /* calc SV bit */ 2223 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2224 /* Calc AV bit */ 2225 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 2226 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); 2227 /* calc SAV bit */ 2228 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2229 } 2230 2231 static inline void gen_muli_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, 2232 int32_t con) 2233 { 2234 TCGv temp = tcg_constant_i32(con); 2235 gen_mul_i64u(ret_low, ret_high, r1, temp); 2236 } 2237 2238 static inline void gen_mulsi_i32(TCGv ret, TCGv r1, int32_t con) 2239 { 2240 TCGv temp = tcg_constant_i32(con); 2241 gen_helper_mul_ssov(ret, tcg_env, r1, temp); 2242 } 2243 2244 static inline void gen_mulsui_i32(TCGv ret, TCGv r1, int32_t con) 2245 { 2246 TCGv temp = tcg_constant_i32(con); 2247 gen_helper_mul_suov(ret, tcg_env, r1, temp); 2248 } 2249 2250 /* gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); */ 2251 static inline void gen_maddsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) 2252 { 2253 TCGv temp = tcg_constant_i32(con); 2254 gen_helper_madd32_ssov(ret, tcg_env, r1, r2, temp); 2255 } 2256 2257 static inline void gen_maddsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) 2258 { 2259 TCGv temp = tcg_constant_i32(con); 2260 gen_helper_madd32_suov(ret, tcg_env, r1, r2, temp); 2261 } 2262 2263 static void 2264 gen_mul_q(TCGv rl, TCGv rh, TCGv arg1, TCGv arg2, uint32_t n, uint32_t up_shift) 2265 { 2266 TCGv_i64 temp_64 = tcg_temp_new_i64(); 2267 TCGv_i64 temp2_64 = tcg_temp_new_i64(); 2268 2269 if (n == 0) { 2270 if (up_shift == 32) { 2271 tcg_gen_muls2_tl(rh, rl, arg1, arg2); 2272 } else if (up_shift == 16) { 2273 tcg_gen_ext_i32_i64(temp_64, arg1); 2274 tcg_gen_ext_i32_i64(temp2_64, arg2); 2275 2276 tcg_gen_mul_i64(temp_64, temp_64, temp2_64); 2277 tcg_gen_shri_i64(temp_64, temp_64, up_shift); 2278 tcg_gen_extr_i64_i32(rl, rh, temp_64); 2279 } else { 2280 tcg_gen_muls2_tl(rl, rh, arg1, arg2); 2281 } 2282 /* reset v bit */ 2283 tcg_gen_movi_tl(cpu_PSW_V, 0); 2284 } else { /* n is expected to be 1 */ 2285 tcg_gen_ext_i32_i64(temp_64, arg1); 2286 tcg_gen_ext_i32_i64(temp2_64, arg2); 2287 2288 tcg_gen_mul_i64(temp_64, temp_64, temp2_64); 2289 2290 if (up_shift == 0) { 2291 tcg_gen_shli_i64(temp_64, temp_64, 1); 2292 } else { 2293 tcg_gen_shri_i64(temp_64, temp_64, up_shift - 1); 2294 } 2295 tcg_gen_extr_i64_i32(rl, rh, temp_64); 2296 /* overflow only occurs if r1 = r2 = 0x8000 */ 2297 if (up_shift == 0) {/* result is 64 bit */ 2298 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rh, 2299 0x80000000); 2300 } else { /* result is 32 bit */ 2301 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rl, 2302 0x80000000); 2303 } 2304 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 2305 /* calc sv overflow bit */ 2306 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2307 } 2308 /* calc av overflow bit */ 2309 if (up_shift == 0) { 2310 tcg_gen_add_tl(cpu_PSW_AV, rh, rh); 2311 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV); 2312 } else { 2313 tcg_gen_add_tl(cpu_PSW_AV, rl, rl); 2314 tcg_gen_xor_tl(cpu_PSW_AV, rl, cpu_PSW_AV); 2315 } 2316 /* calc sav overflow bit */ 2317 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2318 } 2319 2320 static void 2321 gen_mul_q_16(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n) 2322 { 2323 TCGv temp = tcg_temp_new(); 2324 if (n == 0) { 2325 tcg_gen_mul_tl(ret, arg1, arg2); 2326 } else { /* n is expected to be 1 */ 2327 tcg_gen_mul_tl(ret, arg1, arg2); 2328 tcg_gen_shli_tl(ret, ret, 1); 2329 /* catch special case r1 = r2 = 0x8000 */ 2330 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80000000); 2331 tcg_gen_sub_tl(ret, ret, temp); 2332 } 2333 /* reset v bit */ 2334 tcg_gen_movi_tl(cpu_PSW_V, 0); 2335 /* calc av overflow bit */ 2336 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2337 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2338 /* calc sav overflow bit */ 2339 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2340 } 2341 2342 static void gen_mulr_q(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n) 2343 { 2344 TCGv temp = tcg_temp_new(); 2345 if (n == 0) { 2346 tcg_gen_mul_tl(ret, arg1, arg2); 2347 tcg_gen_addi_tl(ret, ret, 0x8000); 2348 } else { 2349 tcg_gen_mul_tl(ret, arg1, arg2); 2350 tcg_gen_shli_tl(ret, ret, 1); 2351 tcg_gen_addi_tl(ret, ret, 0x8000); 2352 /* catch special case r1 = r2 = 0x8000 */ 2353 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80008000); 2354 tcg_gen_muli_tl(temp, temp, 0x8001); 2355 tcg_gen_sub_tl(ret, ret, temp); 2356 } 2357 /* reset v bit */ 2358 tcg_gen_movi_tl(cpu_PSW_V, 0); 2359 /* calc av overflow bit */ 2360 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2361 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2362 /* calc sav overflow bit */ 2363 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2364 /* cut halfword off */ 2365 tcg_gen_andi_tl(ret, ret, 0xffff0000); 2366 } 2367 2368 static inline void 2369 gen_madds_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2370 TCGv r3) 2371 { 2372 TCGv_i64 temp64 = tcg_temp_new_i64(); 2373 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); 2374 gen_helper_madd64_ssov(temp64, tcg_env, r1, temp64, r3); 2375 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2376 } 2377 2378 static inline void 2379 gen_maddsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2380 int32_t con) 2381 { 2382 TCGv temp = tcg_constant_i32(con); 2383 gen_madds_64(ret_low, ret_high, r1, r2_low, r2_high, temp); 2384 } 2385 2386 static inline void 2387 gen_maddsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2388 TCGv r3) 2389 { 2390 TCGv_i64 temp64 = tcg_temp_new_i64(); 2391 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); 2392 gen_helper_madd64_suov(temp64, tcg_env, r1, temp64, r3); 2393 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2394 } 2395 2396 static inline void 2397 gen_maddsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2398 int32_t con) 2399 { 2400 TCGv temp = tcg_constant_i32(con); 2401 gen_maddsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp); 2402 } 2403 2404 static inline void gen_msubsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) 2405 { 2406 TCGv temp = tcg_constant_i32(con); 2407 gen_helper_msub32_ssov(ret, tcg_env, r1, r2, temp); 2408 } 2409 2410 static inline void gen_msubsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) 2411 { 2412 TCGv temp = tcg_constant_i32(con); 2413 gen_helper_msub32_suov(ret, tcg_env, r1, r2, temp); 2414 } 2415 2416 static inline void 2417 gen_msubs_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2418 TCGv r3) 2419 { 2420 TCGv_i64 temp64 = tcg_temp_new_i64(); 2421 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); 2422 gen_helper_msub64_ssov(temp64, tcg_env, r1, temp64, r3); 2423 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2424 } 2425 2426 static inline void 2427 gen_msubsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2428 int32_t con) 2429 { 2430 TCGv temp = tcg_constant_i32(con); 2431 gen_msubs_64(ret_low, ret_high, r1, r2_low, r2_high, temp); 2432 } 2433 2434 static inline void 2435 gen_msubsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2436 TCGv r3) 2437 { 2438 TCGv_i64 temp64 = tcg_temp_new_i64(); 2439 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); 2440 gen_helper_msub64_suov(temp64, tcg_env, r1, temp64, r3); 2441 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2442 } 2443 2444 static inline void 2445 gen_msubsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2446 int32_t con) 2447 { 2448 TCGv temp = tcg_constant_i32(con); 2449 gen_msubsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp); 2450 } 2451 2452 static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low) 2453 { 2454 tcg_gen_smax_tl(ret, arg, tcg_constant_i32(low)); 2455 tcg_gen_smin_tl(ret, ret, tcg_constant_i32(up)); 2456 } 2457 2458 static void gen_saturate_u(TCGv ret, TCGv arg, int32_t up) 2459 { 2460 tcg_gen_umin_tl(ret, arg, tcg_constant_i32(up)); 2461 } 2462 2463 static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count) 2464 { 2465 if (shift_count == -32) { 2466 tcg_gen_movi_tl(ret, 0); 2467 } else if (shift_count >= 0) { 2468 tcg_gen_shli_tl(ret, r1, shift_count); 2469 } else { 2470 tcg_gen_shri_tl(ret, r1, -shift_count); 2471 } 2472 } 2473 2474 static void gen_sh_hi(TCGv ret, TCGv r1, int32_t shiftcount) 2475 { 2476 TCGv temp_low, temp_high; 2477 2478 if (shiftcount == -16) { 2479 tcg_gen_movi_tl(ret, 0); 2480 } else { 2481 temp_high = tcg_temp_new(); 2482 temp_low = tcg_temp_new(); 2483 2484 tcg_gen_andi_tl(temp_low, r1, 0xffff); 2485 tcg_gen_andi_tl(temp_high, r1, 0xffff0000); 2486 gen_shi(temp_low, temp_low, shiftcount); 2487 gen_shi(ret, temp_high, shiftcount); 2488 tcg_gen_deposit_tl(ret, ret, temp_low, 0, 16); 2489 } 2490 } 2491 2492 static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count) 2493 { 2494 uint32_t msk, msk_start; 2495 TCGv temp = tcg_temp_new(); 2496 TCGv temp2 = tcg_temp_new(); 2497 2498 if (shift_count == 0) { 2499 /* Clear PSW.C and PSW.V */ 2500 tcg_gen_movi_tl(cpu_PSW_C, 0); 2501 tcg_gen_mov_tl(cpu_PSW_V, cpu_PSW_C); 2502 tcg_gen_mov_tl(ret, r1); 2503 } else if (shift_count == -32) { 2504 /* set PSW.C */ 2505 tcg_gen_mov_tl(cpu_PSW_C, r1); 2506 /* fill ret completely with sign bit */ 2507 tcg_gen_sari_tl(ret, r1, 31); 2508 /* clear PSW.V */ 2509 tcg_gen_movi_tl(cpu_PSW_V, 0); 2510 } else if (shift_count > 0) { 2511 TCGv t_max = tcg_constant_i32(0x7FFFFFFF >> shift_count); 2512 TCGv t_min = tcg_constant_i32(((int32_t) -0x80000000) >> shift_count); 2513 2514 /* calc carry */ 2515 msk_start = 32 - shift_count; 2516 msk = ((1 << shift_count) - 1) << msk_start; 2517 tcg_gen_andi_tl(cpu_PSW_C, r1, msk); 2518 /* calc v/sv bits */ 2519 tcg_gen_setcond_tl(TCG_COND_GT, temp, r1, t_max); 2520 tcg_gen_setcond_tl(TCG_COND_LT, temp2, r1, t_min); 2521 tcg_gen_or_tl(cpu_PSW_V, temp, temp2); 2522 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 2523 /* calc sv */ 2524 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_V, cpu_PSW_SV); 2525 /* do shift */ 2526 tcg_gen_shli_tl(ret, r1, shift_count); 2527 } else { 2528 /* clear PSW.V */ 2529 tcg_gen_movi_tl(cpu_PSW_V, 0); 2530 /* calc carry */ 2531 msk = (1 << -shift_count) - 1; 2532 tcg_gen_andi_tl(cpu_PSW_C, r1, msk); 2533 /* do shift */ 2534 tcg_gen_sari_tl(ret, r1, -shift_count); 2535 } 2536 /* calc av overflow bit */ 2537 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2538 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2539 /* calc sav overflow bit */ 2540 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2541 } 2542 2543 static void gen_shas(TCGv ret, TCGv r1, TCGv r2) 2544 { 2545 gen_helper_sha_ssov(ret, tcg_env, r1, r2); 2546 } 2547 2548 static void gen_shasi(TCGv ret, TCGv r1, int32_t con) 2549 { 2550 TCGv temp = tcg_constant_i32(con); 2551 gen_shas(ret, r1, temp); 2552 } 2553 2554 static void gen_sha_hi(TCGv ret, TCGv r1, int32_t shift_count) 2555 { 2556 TCGv low, high; 2557 2558 if (shift_count == 0) { 2559 tcg_gen_mov_tl(ret, r1); 2560 } else if (shift_count > 0) { 2561 low = tcg_temp_new(); 2562 high = tcg_temp_new(); 2563 2564 tcg_gen_andi_tl(high, r1, 0xffff0000); 2565 tcg_gen_shli_tl(low, r1, shift_count); 2566 tcg_gen_shli_tl(ret, high, shift_count); 2567 tcg_gen_deposit_tl(ret, ret, low, 0, 16); 2568 } else { 2569 low = tcg_temp_new(); 2570 high = tcg_temp_new(); 2571 2572 tcg_gen_ext16s_tl(low, r1); 2573 tcg_gen_sari_tl(low, low, -shift_count); 2574 tcg_gen_sari_tl(ret, r1, -shift_count); 2575 tcg_gen_deposit_tl(ret, ret, low, 0, 16); 2576 } 2577 } 2578 2579 /* ret = {ret[30:0], (r1 cond r2)}; */ 2580 static void gen_sh_cond(int cond, TCGv ret, TCGv r1, TCGv r2) 2581 { 2582 TCGv temp = tcg_temp_new(); 2583 TCGv temp2 = tcg_temp_new(); 2584 2585 tcg_gen_shli_tl(temp, ret, 1); 2586 tcg_gen_setcond_tl(cond, temp2, r1, r2); 2587 tcg_gen_or_tl(ret, temp, temp2); 2588 } 2589 2590 static void gen_sh_condi(int cond, TCGv ret, TCGv r1, int32_t con) 2591 { 2592 TCGv temp = tcg_constant_i32(con); 2593 gen_sh_cond(cond, ret, r1, temp); 2594 } 2595 2596 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2) 2597 { 2598 gen_helper_add_ssov(ret, tcg_env, r1, r2); 2599 } 2600 2601 static inline void gen_addsi(TCGv ret, TCGv r1, int32_t con) 2602 { 2603 TCGv temp = tcg_constant_i32(con); 2604 gen_helper_add_ssov(ret, tcg_env, r1, temp); 2605 } 2606 2607 static inline void gen_addsui(TCGv ret, TCGv r1, int32_t con) 2608 { 2609 TCGv temp = tcg_constant_i32(con); 2610 gen_helper_add_suov(ret, tcg_env, r1, temp); 2611 } 2612 2613 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2) 2614 { 2615 gen_helper_sub_ssov(ret, tcg_env, r1, r2); 2616 } 2617 2618 static inline void gen_subsu(TCGv ret, TCGv r1, TCGv r2) 2619 { 2620 gen_helper_sub_suov(ret, tcg_env, r1, r2); 2621 } 2622 2623 static inline void gen_bit_2op(TCGv ret, TCGv r1, TCGv r2, 2624 int pos1, int pos2, 2625 void(*op1)(TCGv, TCGv, TCGv), 2626 void(*op2)(TCGv, TCGv, TCGv)) 2627 { 2628 TCGv temp1, temp2; 2629 2630 temp1 = tcg_temp_new(); 2631 temp2 = tcg_temp_new(); 2632 2633 tcg_gen_shri_tl(temp2, r2, pos2); 2634 tcg_gen_shri_tl(temp1, r1, pos1); 2635 2636 (*op1)(temp1, temp1, temp2); 2637 (*op2)(temp1 , ret, temp1); 2638 2639 tcg_gen_deposit_tl(ret, ret, temp1, 0, 1); 2640 } 2641 2642 /* ret = r1[pos1] op1 r2[pos2]; */ 2643 static inline void gen_bit_1op(TCGv ret, TCGv r1, TCGv r2, 2644 int pos1, int pos2, 2645 void(*op1)(TCGv, TCGv, TCGv)) 2646 { 2647 TCGv temp1, temp2; 2648 2649 temp1 = tcg_temp_new(); 2650 temp2 = tcg_temp_new(); 2651 2652 tcg_gen_shri_tl(temp2, r2, pos2); 2653 tcg_gen_shri_tl(temp1, r1, pos1); 2654 2655 (*op1)(ret, temp1, temp2); 2656 2657 tcg_gen_andi_tl(ret, ret, 0x1); 2658 } 2659 2660 static inline void gen_accumulating_cond(int cond, TCGv ret, TCGv r1, TCGv r2, 2661 void(*op)(TCGv, TCGv, TCGv)) 2662 { 2663 TCGv temp = tcg_temp_new(); 2664 TCGv temp2 = tcg_temp_new(); 2665 /* temp = (arg1 cond arg2 )*/ 2666 tcg_gen_setcond_tl(cond, temp, r1, r2); 2667 /* temp2 = ret[0]*/ 2668 tcg_gen_andi_tl(temp2, ret, 0x1); 2669 /* temp = temp insn temp2 */ 2670 (*op)(temp, temp, temp2); 2671 /* ret = {ret[31:1], temp} */ 2672 tcg_gen_deposit_tl(ret, ret, temp, 0, 1); 2673 } 2674 2675 static inline void 2676 gen_accumulating_condi(int cond, TCGv ret, TCGv r1, int32_t con, 2677 void(*op)(TCGv, TCGv, TCGv)) 2678 { 2679 TCGv temp = tcg_constant_i32(con); 2680 gen_accumulating_cond(cond, ret, r1, temp, op); 2681 } 2682 2683 static inline void gen_eqany_bi(TCGv ret, TCGv r1, int32_t con) 2684 { 2685 TCGv b0 = tcg_temp_new(); 2686 TCGv b1 = tcg_temp_new(); 2687 TCGv b2 = tcg_temp_new(); 2688 TCGv b3 = tcg_temp_new(); 2689 2690 /* byte 0 */ 2691 tcg_gen_andi_tl(b0, r1, 0xff); 2692 tcg_gen_setcondi_tl(TCG_COND_EQ, b0, b0, con & 0xff); 2693 2694 /* byte 1 */ 2695 tcg_gen_andi_tl(b1, r1, 0xff00); 2696 tcg_gen_setcondi_tl(TCG_COND_EQ, b1, b1, con & 0xff00); 2697 2698 /* byte 2 */ 2699 tcg_gen_andi_tl(b2, r1, 0xff0000); 2700 tcg_gen_setcondi_tl(TCG_COND_EQ, b2, b2, con & 0xff0000); 2701 2702 /* byte 3 */ 2703 tcg_gen_andi_tl(b3, r1, 0xff000000); 2704 tcg_gen_setcondi_tl(TCG_COND_EQ, b3, b3, con & 0xff000000); 2705 2706 /* combine them */ 2707 tcg_gen_or_tl(ret, b0, b1); 2708 tcg_gen_or_tl(ret, ret, b2); 2709 tcg_gen_or_tl(ret, ret, b3); 2710 } 2711 2712 static inline void gen_eqany_hi(TCGv ret, TCGv r1, int32_t con) 2713 { 2714 TCGv h0 = tcg_temp_new(); 2715 TCGv h1 = tcg_temp_new(); 2716 2717 /* halfword 0 */ 2718 tcg_gen_andi_tl(h0, r1, 0xffff); 2719 tcg_gen_setcondi_tl(TCG_COND_EQ, h0, h0, con & 0xffff); 2720 2721 /* halfword 1 */ 2722 tcg_gen_andi_tl(h1, r1, 0xffff0000); 2723 tcg_gen_setcondi_tl(TCG_COND_EQ, h1, h1, con & 0xffff0000); 2724 2725 /* combine them */ 2726 tcg_gen_or_tl(ret, h0, h1); 2727 } 2728 2729 /* mask = ((1 << width) -1) << pos; 2730 ret = (r1 & ~mask) | (r2 << pos) & mask); */ 2731 static inline void gen_insert(TCGv ret, TCGv r1, TCGv r2, TCGv width, TCGv pos) 2732 { 2733 TCGv mask = tcg_temp_new(); 2734 TCGv temp = tcg_temp_new(); 2735 TCGv temp2 = tcg_temp_new(); 2736 2737 tcg_gen_shl_tl(mask, tcg_constant_tl(1), width); 2738 tcg_gen_subi_tl(mask, mask, 1); 2739 tcg_gen_shl_tl(mask, mask, pos); 2740 2741 tcg_gen_shl_tl(temp, r2, pos); 2742 tcg_gen_and_tl(temp, temp, mask); 2743 tcg_gen_andc_tl(temp2, r1, mask); 2744 tcg_gen_or_tl(ret, temp, temp2); 2745 } 2746 2747 static inline void gen_bsplit(TCGv rl, TCGv rh, TCGv r1) 2748 { 2749 TCGv_i64 temp = tcg_temp_new_i64(); 2750 2751 gen_helper_bsplit(temp, r1); 2752 tcg_gen_extr_i64_i32(rl, rh, temp); 2753 } 2754 2755 static inline void gen_unpack(TCGv rl, TCGv rh, TCGv r1) 2756 { 2757 TCGv_i64 temp = tcg_temp_new_i64(); 2758 2759 gen_helper_unpack(temp, r1); 2760 tcg_gen_extr_i64_i32(rl, rh, temp); 2761 } 2762 2763 static inline void 2764 gen_dvinit_b(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2) 2765 { 2766 TCGv_i64 ret = tcg_temp_new_i64(); 2767 2768 if (!has_feature(ctx, TRICORE_FEATURE_131)) { 2769 gen_helper_dvinit_b_13(ret, tcg_env, r1, r2); 2770 } else { 2771 gen_helper_dvinit_b_131(ret, tcg_env, r1, r2); 2772 } 2773 tcg_gen_extr_i64_i32(rl, rh, ret); 2774 } 2775 2776 static inline void 2777 gen_dvinit_h(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2) 2778 { 2779 TCGv_i64 ret = tcg_temp_new_i64(); 2780 2781 if (!has_feature(ctx, TRICORE_FEATURE_131)) { 2782 gen_helper_dvinit_h_13(ret, tcg_env, r1, r2); 2783 } else { 2784 gen_helper_dvinit_h_131(ret, tcg_env, r1, r2); 2785 } 2786 tcg_gen_extr_i64_i32(rl, rh, ret); 2787 } 2788 2789 static void gen_calc_usb_mul_h(TCGv arg_low, TCGv arg_high) 2790 { 2791 TCGv temp = tcg_temp_new(); 2792 /* calc AV bit */ 2793 tcg_gen_add_tl(temp, arg_low, arg_low); 2794 tcg_gen_xor_tl(temp, temp, arg_low); 2795 tcg_gen_add_tl(cpu_PSW_AV, arg_high, arg_high); 2796 tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, arg_high); 2797 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp); 2798 /* calc SAV bit */ 2799 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2800 tcg_gen_movi_tl(cpu_PSW_V, 0); 2801 } 2802 2803 static void gen_calc_usb_mulr_h(TCGv arg) 2804 { 2805 TCGv temp = tcg_temp_new(); 2806 /* calc AV bit */ 2807 tcg_gen_add_tl(temp, arg, arg); 2808 tcg_gen_xor_tl(temp, temp, arg); 2809 tcg_gen_shli_tl(cpu_PSW_AV, temp, 16); 2810 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp); 2811 /* calc SAV bit */ 2812 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2813 /* clear V bit */ 2814 tcg_gen_movi_tl(cpu_PSW_V, 0); 2815 } 2816 2817 /* helpers for generating program flow micro-ops */ 2818 2819 static inline void gen_save_pc(target_ulong pc) 2820 { 2821 tcg_gen_movi_tl(cpu_PC, pc); 2822 } 2823 2824 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 2825 { 2826 if (translator_use_goto_tb(&ctx->base, dest)) { 2827 tcg_gen_goto_tb(n); 2828 gen_save_pc(dest); 2829 tcg_gen_exit_tb(ctx->base.tb, n); 2830 } else { 2831 gen_save_pc(dest); 2832 tcg_gen_lookup_and_goto_ptr(); 2833 } 2834 ctx->base.is_jmp = DISAS_NORETURN; 2835 } 2836 2837 static void generate_trap(DisasContext *ctx, int class, int tin) 2838 { 2839 TCGv_i32 classtemp = tcg_constant_i32(class); 2840 TCGv_i32 tintemp = tcg_constant_i32(tin); 2841 2842 gen_save_pc(ctx->base.pc_next); 2843 gen_helper_raise_exception_sync(tcg_env, classtemp, tintemp); 2844 ctx->base.is_jmp = DISAS_NORETURN; 2845 } 2846 2847 static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1, 2848 TCGv r2, int16_t address) 2849 { 2850 TCGLabel *jumpLabel = gen_new_label(); 2851 tcg_gen_brcond_tl(cond, r1, r2, jumpLabel); 2852 2853 gen_goto_tb(ctx, 1, ctx->pc_succ_insn); 2854 2855 gen_set_label(jumpLabel); 2856 gen_goto_tb(ctx, 0, ctx->base.pc_next + address * 2); 2857 } 2858 2859 static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv r1, 2860 int r2, int16_t address) 2861 { 2862 TCGv temp = tcg_constant_i32(r2); 2863 gen_branch_cond(ctx, cond, r1, temp, address); 2864 } 2865 2866 static void gen_loop(DisasContext *ctx, int r1, int32_t offset) 2867 { 2868 TCGLabel *l1 = gen_new_label(); 2869 2870 tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1); 2871 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], -1, l1); 2872 gen_goto_tb(ctx, 1, ctx->base.pc_next + offset); 2873 gen_set_label(l1); 2874 gen_goto_tb(ctx, 0, ctx->pc_succ_insn); 2875 } 2876 2877 static void gen_fcall_save_ctx(DisasContext *ctx) 2878 { 2879 TCGv temp = tcg_temp_new(); 2880 2881 tcg_gen_addi_tl(temp, cpu_gpr_a[10], -4); 2882 tcg_gen_qemu_st_tl(cpu_gpr_a[11], temp, ctx->mem_idx, MO_LESL); 2883 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); 2884 tcg_gen_mov_tl(cpu_gpr_a[10], temp); 2885 } 2886 2887 static void gen_fret(DisasContext *ctx) 2888 { 2889 TCGv temp = tcg_temp_new(); 2890 2891 tcg_gen_andi_tl(temp, cpu_gpr_a[11], ~0x1); 2892 tcg_gen_qemu_ld_tl(cpu_gpr_a[11], cpu_gpr_a[10], ctx->mem_idx, MO_LESL); 2893 tcg_gen_addi_tl(cpu_gpr_a[10], cpu_gpr_a[10], 4); 2894 tcg_gen_mov_tl(cpu_PC, temp); 2895 ctx->base.is_jmp = DISAS_EXIT; 2896 } 2897 2898 static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, 2899 int r2 , int32_t constant , int32_t offset) 2900 { 2901 TCGv temp, temp2; 2902 int n; 2903 2904 switch (opc) { 2905 /* SB-format jumps */ 2906 case OPC1_16_SB_J: 2907 case OPC1_32_B_J: 2908 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); 2909 break; 2910 case OPC1_32_B_CALL: 2911 case OPC1_16_SB_CALL: 2912 gen_helper_1arg(call, ctx->pc_succ_insn); 2913 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); 2914 break; 2915 case OPC1_16_SB_JZ: 2916 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], 0, offset); 2917 break; 2918 case OPC1_16_SB_JNZ: 2919 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 0, offset); 2920 break; 2921 /* SBC-format jumps */ 2922 case OPC1_16_SBC_JEQ: 2923 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset); 2924 break; 2925 case OPC1_16_SBC_JEQ2: 2926 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, 2927 offset + 16); 2928 break; 2929 case OPC1_16_SBC_JNE: 2930 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset); 2931 break; 2932 case OPC1_16_SBC_JNE2: 2933 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 2934 constant, offset + 16); 2935 break; 2936 /* SBRN-format jumps */ 2937 case OPC1_16_SBRN_JZ_T: 2938 temp = tcg_temp_new(); 2939 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant); 2940 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset); 2941 break; 2942 case OPC1_16_SBRN_JNZ_T: 2943 temp = tcg_temp_new(); 2944 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant); 2945 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset); 2946 break; 2947 /* SBR-format jumps */ 2948 case OPC1_16_SBR_JEQ: 2949 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], 2950 offset); 2951 break; 2952 case OPC1_16_SBR_JEQ2: 2953 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], 2954 offset + 16); 2955 break; 2956 case OPC1_16_SBR_JNE: 2957 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], 2958 offset); 2959 break; 2960 case OPC1_16_SBR_JNE2: 2961 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], 2962 offset + 16); 2963 break; 2964 case OPC1_16_SBR_JNZ: 2965 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], 0, offset); 2966 break; 2967 case OPC1_16_SBR_JNZ_A: 2968 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset); 2969 break; 2970 case OPC1_16_SBR_JGEZ: 2971 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], 0, offset); 2972 break; 2973 case OPC1_16_SBR_JGTZ: 2974 gen_branch_condi(ctx, TCG_COND_GT, cpu_gpr_d[r1], 0, offset); 2975 break; 2976 case OPC1_16_SBR_JLEZ: 2977 gen_branch_condi(ctx, TCG_COND_LE, cpu_gpr_d[r1], 0, offset); 2978 break; 2979 case OPC1_16_SBR_JLTZ: 2980 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], 0, offset); 2981 break; 2982 case OPC1_16_SBR_JZ: 2983 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], 0, offset); 2984 break; 2985 case OPC1_16_SBR_JZ_A: 2986 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset); 2987 break; 2988 case OPC1_16_SBR_LOOP: 2989 gen_loop(ctx, r1, offset * 2 - 32); 2990 break; 2991 /* SR-format jumps */ 2992 case OPC1_16_SR_JI: 2993 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], 0xfffffffe); 2994 ctx->base.is_jmp = DISAS_EXIT; 2995 break; 2996 case OPC2_32_SYS_RET: 2997 case OPC2_16_SR_RET: 2998 gen_helper_ret(tcg_env); 2999 ctx->base.is_jmp = DISAS_EXIT; 3000 break; 3001 /* B-format */ 3002 case OPC1_32_B_CALLA: 3003 gen_helper_1arg(call, ctx->pc_succ_insn); 3004 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); 3005 break; 3006 case OPC1_32_B_FCALL: 3007 gen_fcall_save_ctx(ctx); 3008 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); 3009 break; 3010 case OPC1_32_B_FCALLA: 3011 gen_fcall_save_ctx(ctx); 3012 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); 3013 break; 3014 case OPC1_32_B_JLA: 3015 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); 3016 /* fall through */ 3017 case OPC1_32_B_JA: 3018 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); 3019 break; 3020 case OPC1_32_B_JL: 3021 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); 3022 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); 3023 break; 3024 /* BOL format */ 3025 case OPCM_32_BRC_EQ_NEQ: 3026 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JEQ) { 3027 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], constant, offset); 3028 } else { 3029 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], constant, offset); 3030 } 3031 break; 3032 case OPCM_32_BRC_GE: 3033 if (MASK_OP_BRC_OP2(ctx->opcode) == OP2_32_BRC_JGE) { 3034 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], constant, offset); 3035 } else { 3036 constant = MASK_OP_BRC_CONST4(ctx->opcode); 3037 gen_branch_condi(ctx, TCG_COND_GEU, cpu_gpr_d[r1], constant, 3038 offset); 3039 } 3040 break; 3041 case OPCM_32_BRC_JLT: 3042 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JLT) { 3043 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], constant, offset); 3044 } else { 3045 constant = MASK_OP_BRC_CONST4(ctx->opcode); 3046 gen_branch_condi(ctx, TCG_COND_LTU, cpu_gpr_d[r1], constant, 3047 offset); 3048 } 3049 break; 3050 case OPCM_32_BRC_JNE: 3051 temp = tcg_temp_new(); 3052 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JNED) { 3053 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 3054 /* subi is unconditional */ 3055 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); 3056 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset); 3057 } else { 3058 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 3059 /* addi is unconditional */ 3060 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); 3061 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset); 3062 } 3063 break; 3064 /* BRN format */ 3065 case OPCM_32_BRN_JTT: 3066 n = MASK_OP_BRN_N(ctx->opcode); 3067 3068 temp = tcg_temp_new(); 3069 tcg_gen_andi_tl(temp, cpu_gpr_d[r1], (1 << n)); 3070 3071 if (MASK_OP_BRN_OP2(ctx->opcode) == OPC2_32_BRN_JNZ_T) { 3072 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset); 3073 } else { 3074 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset); 3075 } 3076 break; 3077 /* BRR Format */ 3078 case OPCM_32_BRR_EQ_NEQ: 3079 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ) { 3080 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], 3081 offset); 3082 } else { 3083 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], 3084 offset); 3085 } 3086 break; 3087 case OPCM_32_BRR_ADDR_EQ_NEQ: 3088 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ_A) { 3089 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_a[r1], cpu_gpr_a[r2], 3090 offset); 3091 } else { 3092 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_a[r1], cpu_gpr_a[r2], 3093 offset); 3094 } 3095 break; 3096 case OPCM_32_BRR_GE: 3097 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JGE) { 3098 gen_branch_cond(ctx, TCG_COND_GE, cpu_gpr_d[r1], cpu_gpr_d[r2], 3099 offset); 3100 } else { 3101 gen_branch_cond(ctx, TCG_COND_GEU, cpu_gpr_d[r1], cpu_gpr_d[r2], 3102 offset); 3103 } 3104 break; 3105 case OPCM_32_BRR_JLT: 3106 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JLT) { 3107 gen_branch_cond(ctx, TCG_COND_LT, cpu_gpr_d[r1], cpu_gpr_d[r2], 3108 offset); 3109 } else { 3110 gen_branch_cond(ctx, TCG_COND_LTU, cpu_gpr_d[r1], cpu_gpr_d[r2], 3111 offset); 3112 } 3113 break; 3114 case OPCM_32_BRR_LOOP: 3115 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_LOOP) { 3116 gen_loop(ctx, r2, offset * 2); 3117 } else { 3118 /* OPC2_32_BRR_LOOPU */ 3119 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); 3120 } 3121 break; 3122 case OPCM_32_BRR_JNE: 3123 temp = tcg_temp_new(); 3124 temp2 = tcg_temp_new(); 3125 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRR_JNED) { 3126 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 3127 /* also save r2, in case of r1 == r2, so r2 is not decremented */ 3128 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]); 3129 /* subi is unconditional */ 3130 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); 3131 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset); 3132 } else { 3133 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 3134 /* also save r2, in case of r1 == r2, so r2 is not decremented */ 3135 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]); 3136 /* addi is unconditional */ 3137 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); 3138 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset); 3139 } 3140 break; 3141 case OPCM_32_BRR_JNZ: 3142 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JNZ_A) { 3143 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset); 3144 } else { 3145 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset); 3146 } 3147 break; 3148 default: 3149 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3150 } 3151 } 3152 3153 3154 /* 3155 * Functions for decoding instructions 3156 */ 3157 3158 static void decode_src_opc(DisasContext *ctx, int op1) 3159 { 3160 int r1; 3161 int32_t const4; 3162 TCGv temp, temp2; 3163 3164 r1 = MASK_OP_SRC_S1D(ctx->opcode); 3165 const4 = MASK_OP_SRC_CONST4_SEXT(ctx->opcode); 3166 3167 switch (op1) { 3168 case OPC1_16_SRC_ADD: 3169 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); 3170 break; 3171 case OPC1_16_SRC_ADD_A15: 3172 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[15], const4); 3173 break; 3174 case OPC1_16_SRC_ADD_15A: 3175 gen_addi_d(cpu_gpr_d[15], cpu_gpr_d[r1], const4); 3176 break; 3177 case OPC1_16_SRC_ADD_A: 3178 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], const4); 3179 break; 3180 case OPC1_16_SRC_CADD: 3181 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const4, cpu_gpr_d[r1], 3182 cpu_gpr_d[15]); 3183 break; 3184 case OPC1_16_SRC_CADDN: 3185 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const4, cpu_gpr_d[r1], 3186 cpu_gpr_d[15]); 3187 break; 3188 case OPC1_16_SRC_CMOV: 3189 temp = tcg_constant_tl(0); 3190 temp2 = tcg_constant_tl(const4); 3191 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp, 3192 temp2, cpu_gpr_d[r1]); 3193 break; 3194 case OPC1_16_SRC_CMOVN: 3195 temp = tcg_constant_tl(0); 3196 temp2 = tcg_constant_tl(const4); 3197 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp, 3198 temp2, cpu_gpr_d[r1]); 3199 break; 3200 case OPC1_16_SRC_EQ: 3201 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1], 3202 const4); 3203 break; 3204 case OPC1_16_SRC_LT: 3205 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1], 3206 const4); 3207 break; 3208 case OPC1_16_SRC_MOV: 3209 tcg_gen_movi_tl(cpu_gpr_d[r1], const4); 3210 break; 3211 case OPC1_16_SRC_MOV_A: 3212 const4 = MASK_OP_SRC_CONST4(ctx->opcode); 3213 tcg_gen_movi_tl(cpu_gpr_a[r1], const4); 3214 break; 3215 case OPC1_16_SRC_MOV_E: 3216 if (has_feature(ctx, TRICORE_FEATURE_16)) { 3217 CHECK_REG_PAIR(r1); 3218 tcg_gen_movi_tl(cpu_gpr_d[r1], const4); 3219 tcg_gen_sari_tl(cpu_gpr_d[r1+1], cpu_gpr_d[r1], 31); 3220 } else { 3221 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3222 } 3223 break; 3224 case OPC1_16_SRC_SH: 3225 gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); 3226 break; 3227 case OPC1_16_SRC_SHA: 3228 gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); 3229 break; 3230 default: 3231 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3232 } 3233 } 3234 3235 static void decode_srr_opc(DisasContext *ctx, int op1) 3236 { 3237 int r1, r2; 3238 TCGv temp; 3239 3240 r1 = MASK_OP_SRR_S1D(ctx->opcode); 3241 r2 = MASK_OP_SRR_S2(ctx->opcode); 3242 3243 switch (op1) { 3244 case OPC1_16_SRR_ADD: 3245 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3246 break; 3247 case OPC1_16_SRR_ADD_A15: 3248 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]); 3249 break; 3250 case OPC1_16_SRR_ADD_15A: 3251 gen_add_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3252 break; 3253 case OPC1_16_SRR_ADD_A: 3254 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], cpu_gpr_a[r2]); 3255 break; 3256 case OPC1_16_SRR_ADDS: 3257 gen_adds(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3258 break; 3259 case OPC1_16_SRR_AND: 3260 tcg_gen_and_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3261 break; 3262 case OPC1_16_SRR_CMOV: 3263 temp = tcg_constant_tl(0); 3264 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp, 3265 cpu_gpr_d[r2], cpu_gpr_d[r1]); 3266 break; 3267 case OPC1_16_SRR_CMOVN: 3268 temp = tcg_constant_tl(0); 3269 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp, 3270 cpu_gpr_d[r2], cpu_gpr_d[r1]); 3271 break; 3272 case OPC1_16_SRR_EQ: 3273 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1], 3274 cpu_gpr_d[r2]); 3275 break; 3276 case OPC1_16_SRR_LT: 3277 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1], 3278 cpu_gpr_d[r2]); 3279 break; 3280 case OPC1_16_SRR_MOV: 3281 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_d[r2]); 3282 break; 3283 case OPC1_16_SRR_MOV_A: 3284 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_d[r2]); 3285 break; 3286 case OPC1_16_SRR_MOV_AA: 3287 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_a[r2]); 3288 break; 3289 case OPC1_16_SRR_MOV_D: 3290 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_a[r2]); 3291 break; 3292 case OPC1_16_SRR_MUL: 3293 gen_mul_i32s(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3294 break; 3295 case OPC1_16_SRR_OR: 3296 tcg_gen_or_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3297 break; 3298 case OPC1_16_SRR_SUB: 3299 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3300 break; 3301 case OPC1_16_SRR_SUB_A15B: 3302 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]); 3303 break; 3304 case OPC1_16_SRR_SUB_15AB: 3305 gen_sub_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3306 break; 3307 case OPC1_16_SRR_SUBS: 3308 gen_subs(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3309 break; 3310 case OPC1_16_SRR_XOR: 3311 tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3312 break; 3313 default: 3314 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3315 } 3316 } 3317 3318 static void decode_ssr_opc(DisasContext *ctx, int op1) 3319 { 3320 int r1, r2; 3321 3322 r1 = MASK_OP_SSR_S1(ctx->opcode); 3323 r2 = MASK_OP_SSR_S2(ctx->opcode); 3324 3325 switch (op1) { 3326 case OPC1_16_SSR_ST_A: 3327 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); 3328 break; 3329 case OPC1_16_SSR_ST_A_POSTINC: 3330 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); 3331 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); 3332 break; 3333 case OPC1_16_SSR_ST_B: 3334 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); 3335 break; 3336 case OPC1_16_SSR_ST_B_POSTINC: 3337 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); 3338 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1); 3339 break; 3340 case OPC1_16_SSR_ST_H: 3341 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW); 3342 break; 3343 case OPC1_16_SSR_ST_H_POSTINC: 3344 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW); 3345 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2); 3346 break; 3347 case OPC1_16_SSR_ST_W: 3348 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); 3349 break; 3350 case OPC1_16_SSR_ST_W_POSTINC: 3351 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); 3352 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); 3353 break; 3354 default: 3355 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3356 } 3357 } 3358 3359 static void decode_sc_opc(DisasContext *ctx, int op1) 3360 { 3361 int32_t const16; 3362 3363 const16 = MASK_OP_SC_CONST8(ctx->opcode); 3364 3365 switch (op1) { 3366 case OPC1_16_SC_AND: 3367 tcg_gen_andi_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16); 3368 break; 3369 case OPC1_16_SC_BISR: 3370 if (ctx->priv == TRICORE_PRIV_SM) { 3371 gen_helper_1arg(bisr, const16 & 0xff); 3372 } else { 3373 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); 3374 } 3375 break; 3376 case OPC1_16_SC_LD_A: 3377 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL); 3378 break; 3379 case OPC1_16_SC_LD_W: 3380 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL); 3381 break; 3382 case OPC1_16_SC_MOV: 3383 tcg_gen_movi_tl(cpu_gpr_d[15], const16); 3384 break; 3385 case OPC1_16_SC_OR: 3386 tcg_gen_ori_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16); 3387 break; 3388 case OPC1_16_SC_ST_A: 3389 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL); 3390 break; 3391 case OPC1_16_SC_ST_W: 3392 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL); 3393 break; 3394 case OPC1_16_SC_SUB_A: 3395 tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16); 3396 break; 3397 default: 3398 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3399 } 3400 } 3401 3402 static void decode_slr_opc(DisasContext *ctx, int op1) 3403 { 3404 int r1, r2; 3405 3406 r1 = MASK_OP_SLR_D(ctx->opcode); 3407 r2 = MASK_OP_SLR_S2(ctx->opcode); 3408 3409 switch (op1) { 3410 /* SLR-format */ 3411 case OPC1_16_SLR_LD_A: 3412 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); 3413 break; 3414 case OPC1_16_SLR_LD_A_POSTINC: 3415 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); 3416 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); 3417 break; 3418 case OPC1_16_SLR_LD_BU: 3419 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); 3420 break; 3421 case OPC1_16_SLR_LD_BU_POSTINC: 3422 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); 3423 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1); 3424 break; 3425 case OPC1_16_SLR_LD_H: 3426 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW); 3427 break; 3428 case OPC1_16_SLR_LD_H_POSTINC: 3429 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW); 3430 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2); 3431 break; 3432 case OPC1_16_SLR_LD_W: 3433 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); 3434 break; 3435 case OPC1_16_SLR_LD_W_POSTINC: 3436 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); 3437 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); 3438 break; 3439 default: 3440 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3441 } 3442 } 3443 3444 static void decode_sro_opc(DisasContext *ctx, int op1) 3445 { 3446 int r2; 3447 int32_t address; 3448 3449 r2 = MASK_OP_SRO_S2(ctx->opcode); 3450 address = MASK_OP_SRO_OFF4(ctx->opcode); 3451 3452 /* SRO-format */ 3453 switch (op1) { 3454 case OPC1_16_SRO_LD_A: 3455 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL); 3456 break; 3457 case OPC1_16_SRO_LD_BU: 3458 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB); 3459 break; 3460 case OPC1_16_SRO_LD_H: 3461 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW); 3462 break; 3463 case OPC1_16_SRO_LD_W: 3464 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL); 3465 break; 3466 case OPC1_16_SRO_ST_A: 3467 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL); 3468 break; 3469 case OPC1_16_SRO_ST_B: 3470 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB); 3471 break; 3472 case OPC1_16_SRO_ST_H: 3473 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW); 3474 break; 3475 case OPC1_16_SRO_ST_W: 3476 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL); 3477 break; 3478 default: 3479 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3480 } 3481 } 3482 3483 static void decode_sr_system(DisasContext *ctx) 3484 { 3485 uint32_t op2; 3486 op2 = MASK_OP_SR_OP2(ctx->opcode); 3487 3488 switch (op2) { 3489 case OPC2_16_SR_NOP: 3490 break; 3491 case OPC2_16_SR_RET: 3492 gen_compute_branch(ctx, op2, 0, 0, 0, 0); 3493 break; 3494 case OPC2_16_SR_RFE: 3495 gen_helper_rfe(tcg_env); 3496 ctx->base.is_jmp = DISAS_EXIT; 3497 break; 3498 case OPC2_16_SR_DEBUG: 3499 /* raise EXCP_DEBUG */ 3500 break; 3501 case OPC2_16_SR_FRET: 3502 gen_fret(ctx); 3503 break; 3504 default: 3505 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3506 } 3507 } 3508 3509 static void decode_sr_accu(DisasContext *ctx) 3510 { 3511 uint32_t op2; 3512 uint32_t r1; 3513 3514 r1 = MASK_OP_SR_S1D(ctx->opcode); 3515 op2 = MASK_OP_SR_OP2(ctx->opcode); 3516 3517 switch (op2) { 3518 case OPC2_16_SR_RSUB: 3519 /* calc V bit -- overflow only if r1 = -0x80000000 */ 3520 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], -0x80000000); 3521 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 3522 /* calc SV bit */ 3523 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 3524 /* sub */ 3525 tcg_gen_neg_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]); 3526 /* calc av */ 3527 tcg_gen_add_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_gpr_d[r1]); 3528 tcg_gen_xor_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_PSW_AV); 3529 /* calc sav */ 3530 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 3531 break; 3532 case OPC2_16_SR_SAT_B: 3533 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7f, -0x80); 3534 break; 3535 case OPC2_16_SR_SAT_BU: 3536 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xff); 3537 break; 3538 case OPC2_16_SR_SAT_H: 3539 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7fff, -0x8000); 3540 break; 3541 case OPC2_16_SR_SAT_HU: 3542 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xffff); 3543 break; 3544 default: 3545 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3546 } 3547 } 3548 3549 static void decode_16Bit_opc(DisasContext *ctx) 3550 { 3551 int op1; 3552 int r1, r2; 3553 int32_t const16; 3554 int32_t address; 3555 TCGv temp; 3556 3557 op1 = MASK_OP_MAJOR(ctx->opcode); 3558 3559 /* handle ADDSC.A opcode only being 6 bit long */ 3560 if (unlikely((op1 & 0x3f) == OPC1_16_SRRS_ADDSC_A)) { 3561 op1 = OPC1_16_SRRS_ADDSC_A; 3562 } 3563 3564 switch (op1) { 3565 case OPC1_16_SRC_ADD: 3566 case OPC1_16_SRC_ADD_A15: 3567 case OPC1_16_SRC_ADD_15A: 3568 case OPC1_16_SRC_ADD_A: 3569 case OPC1_16_SRC_CADD: 3570 case OPC1_16_SRC_CADDN: 3571 case OPC1_16_SRC_CMOV: 3572 case OPC1_16_SRC_CMOVN: 3573 case OPC1_16_SRC_EQ: 3574 case OPC1_16_SRC_LT: 3575 case OPC1_16_SRC_MOV: 3576 case OPC1_16_SRC_MOV_A: 3577 case OPC1_16_SRC_MOV_E: 3578 case OPC1_16_SRC_SH: 3579 case OPC1_16_SRC_SHA: 3580 decode_src_opc(ctx, op1); 3581 break; 3582 /* SRR-format */ 3583 case OPC1_16_SRR_ADD: 3584 case OPC1_16_SRR_ADD_A15: 3585 case OPC1_16_SRR_ADD_15A: 3586 case OPC1_16_SRR_ADD_A: 3587 case OPC1_16_SRR_ADDS: 3588 case OPC1_16_SRR_AND: 3589 case OPC1_16_SRR_CMOV: 3590 case OPC1_16_SRR_CMOVN: 3591 case OPC1_16_SRR_EQ: 3592 case OPC1_16_SRR_LT: 3593 case OPC1_16_SRR_MOV: 3594 case OPC1_16_SRR_MOV_A: 3595 case OPC1_16_SRR_MOV_AA: 3596 case OPC1_16_SRR_MOV_D: 3597 case OPC1_16_SRR_MUL: 3598 case OPC1_16_SRR_OR: 3599 case OPC1_16_SRR_SUB: 3600 case OPC1_16_SRR_SUB_A15B: 3601 case OPC1_16_SRR_SUB_15AB: 3602 case OPC1_16_SRR_SUBS: 3603 case OPC1_16_SRR_XOR: 3604 decode_srr_opc(ctx, op1); 3605 break; 3606 /* SSR-format */ 3607 case OPC1_16_SSR_ST_A: 3608 case OPC1_16_SSR_ST_A_POSTINC: 3609 case OPC1_16_SSR_ST_B: 3610 case OPC1_16_SSR_ST_B_POSTINC: 3611 case OPC1_16_SSR_ST_H: 3612 case OPC1_16_SSR_ST_H_POSTINC: 3613 case OPC1_16_SSR_ST_W: 3614 case OPC1_16_SSR_ST_W_POSTINC: 3615 decode_ssr_opc(ctx, op1); 3616 break; 3617 /* SRRS-format */ 3618 case OPC1_16_SRRS_ADDSC_A: 3619 r2 = MASK_OP_SRRS_S2(ctx->opcode); 3620 r1 = MASK_OP_SRRS_S1D(ctx->opcode); 3621 const16 = MASK_OP_SRRS_N(ctx->opcode); 3622 temp = tcg_temp_new(); 3623 tcg_gen_shli_tl(temp, cpu_gpr_d[15], const16); 3624 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], temp); 3625 break; 3626 /* SLRO-format */ 3627 case OPC1_16_SLRO_LD_A: 3628 r1 = MASK_OP_SLRO_D(ctx->opcode); 3629 const16 = MASK_OP_SLRO_OFF4(ctx->opcode); 3630 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); 3631 break; 3632 case OPC1_16_SLRO_LD_BU: 3633 r1 = MASK_OP_SLRO_D(ctx->opcode); 3634 const16 = MASK_OP_SLRO_OFF4(ctx->opcode); 3635 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB); 3636 break; 3637 case OPC1_16_SLRO_LD_H: 3638 r1 = MASK_OP_SLRO_D(ctx->opcode); 3639 const16 = MASK_OP_SLRO_OFF4(ctx->opcode); 3640 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW); 3641 break; 3642 case OPC1_16_SLRO_LD_W: 3643 r1 = MASK_OP_SLRO_D(ctx->opcode); 3644 const16 = MASK_OP_SLRO_OFF4(ctx->opcode); 3645 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); 3646 break; 3647 /* SB-format */ 3648 case OPC1_16_SB_CALL: 3649 case OPC1_16_SB_J: 3650 case OPC1_16_SB_JNZ: 3651 case OPC1_16_SB_JZ: 3652 address = MASK_OP_SB_DISP8_SEXT(ctx->opcode); 3653 gen_compute_branch(ctx, op1, 0, 0, 0, address); 3654 break; 3655 /* SBC-format */ 3656 case OPC1_16_SBC_JEQ: 3657 case OPC1_16_SBC_JNE: 3658 address = MASK_OP_SBC_DISP4(ctx->opcode); 3659 const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode); 3660 gen_compute_branch(ctx, op1, 0, 0, const16, address); 3661 break; 3662 case OPC1_16_SBC_JEQ2: 3663 case OPC1_16_SBC_JNE2: 3664 if (has_feature(ctx, TRICORE_FEATURE_16)) { 3665 address = MASK_OP_SBC_DISP4(ctx->opcode); 3666 const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode); 3667 gen_compute_branch(ctx, op1, 0, 0, const16, address); 3668 } else { 3669 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3670 } 3671 break; 3672 /* SBRN-format */ 3673 case OPC1_16_SBRN_JNZ_T: 3674 case OPC1_16_SBRN_JZ_T: 3675 address = MASK_OP_SBRN_DISP4(ctx->opcode); 3676 const16 = MASK_OP_SBRN_N(ctx->opcode); 3677 gen_compute_branch(ctx, op1, 0, 0, const16, address); 3678 break; 3679 /* SBR-format */ 3680 case OPC1_16_SBR_JEQ2: 3681 case OPC1_16_SBR_JNE2: 3682 if (has_feature(ctx, TRICORE_FEATURE_16)) { 3683 r1 = MASK_OP_SBR_S2(ctx->opcode); 3684 address = MASK_OP_SBR_DISP4(ctx->opcode); 3685 gen_compute_branch(ctx, op1, r1, 0, 0, address); 3686 } else { 3687 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3688 } 3689 break; 3690 case OPC1_16_SBR_JEQ: 3691 case OPC1_16_SBR_JGEZ: 3692 case OPC1_16_SBR_JGTZ: 3693 case OPC1_16_SBR_JLEZ: 3694 case OPC1_16_SBR_JLTZ: 3695 case OPC1_16_SBR_JNE: 3696 case OPC1_16_SBR_JNZ: 3697 case OPC1_16_SBR_JNZ_A: 3698 case OPC1_16_SBR_JZ: 3699 case OPC1_16_SBR_JZ_A: 3700 case OPC1_16_SBR_LOOP: 3701 r1 = MASK_OP_SBR_S2(ctx->opcode); 3702 address = MASK_OP_SBR_DISP4(ctx->opcode); 3703 gen_compute_branch(ctx, op1, r1, 0, 0, address); 3704 break; 3705 /* SC-format */ 3706 case OPC1_16_SC_AND: 3707 case OPC1_16_SC_BISR: 3708 case OPC1_16_SC_LD_A: 3709 case OPC1_16_SC_LD_W: 3710 case OPC1_16_SC_MOV: 3711 case OPC1_16_SC_OR: 3712 case OPC1_16_SC_ST_A: 3713 case OPC1_16_SC_ST_W: 3714 case OPC1_16_SC_SUB_A: 3715 decode_sc_opc(ctx, op1); 3716 break; 3717 /* SLR-format */ 3718 case OPC1_16_SLR_LD_A: 3719 case OPC1_16_SLR_LD_A_POSTINC: 3720 case OPC1_16_SLR_LD_BU: 3721 case OPC1_16_SLR_LD_BU_POSTINC: 3722 case OPC1_16_SLR_LD_H: 3723 case OPC1_16_SLR_LD_H_POSTINC: 3724 case OPC1_16_SLR_LD_W: 3725 case OPC1_16_SLR_LD_W_POSTINC: 3726 decode_slr_opc(ctx, op1); 3727 break; 3728 /* SRO-format */ 3729 case OPC1_16_SRO_LD_A: 3730 case OPC1_16_SRO_LD_BU: 3731 case OPC1_16_SRO_LD_H: 3732 case OPC1_16_SRO_LD_W: 3733 case OPC1_16_SRO_ST_A: 3734 case OPC1_16_SRO_ST_B: 3735 case OPC1_16_SRO_ST_H: 3736 case OPC1_16_SRO_ST_W: 3737 decode_sro_opc(ctx, op1); 3738 break; 3739 /* SSRO-format */ 3740 case OPC1_16_SSRO_ST_A: 3741 r1 = MASK_OP_SSRO_S1(ctx->opcode); 3742 const16 = MASK_OP_SSRO_OFF4(ctx->opcode); 3743 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); 3744 break; 3745 case OPC1_16_SSRO_ST_B: 3746 r1 = MASK_OP_SSRO_S1(ctx->opcode); 3747 const16 = MASK_OP_SSRO_OFF4(ctx->opcode); 3748 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB); 3749 break; 3750 case OPC1_16_SSRO_ST_H: 3751 r1 = MASK_OP_SSRO_S1(ctx->opcode); 3752 const16 = MASK_OP_SSRO_OFF4(ctx->opcode); 3753 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW); 3754 break; 3755 case OPC1_16_SSRO_ST_W: 3756 r1 = MASK_OP_SSRO_S1(ctx->opcode); 3757 const16 = MASK_OP_SSRO_OFF4(ctx->opcode); 3758 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); 3759 break; 3760 /* SR-format */ 3761 case OPCM_16_SR_SYSTEM: 3762 decode_sr_system(ctx); 3763 break; 3764 case OPCM_16_SR_ACCU: 3765 decode_sr_accu(ctx); 3766 break; 3767 case OPC1_16_SR_JI: 3768 r1 = MASK_OP_SR_S1D(ctx->opcode); 3769 gen_compute_branch(ctx, op1, r1, 0, 0, 0); 3770 break; 3771 case OPC1_16_SR_NOT: 3772 r1 = MASK_OP_SR_S1D(ctx->opcode); 3773 tcg_gen_not_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]); 3774 break; 3775 default: 3776 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3777 } 3778 } 3779 3780 /* 3781 * 32 bit instructions 3782 */ 3783 3784 /* ABS-format */ 3785 static void decode_abs_ldw(DisasContext *ctx) 3786 { 3787 int32_t op2; 3788 int32_t r1; 3789 uint32_t address; 3790 TCGv temp; 3791 3792 r1 = MASK_OP_ABS_S1D(ctx->opcode); 3793 address = MASK_OP_ABS_OFF18(ctx->opcode); 3794 op2 = MASK_OP_ABS_OP2(ctx->opcode); 3795 3796 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 3797 3798 switch (op2) { 3799 case OPC2_32_ABS_LD_A: 3800 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL); 3801 break; 3802 case OPC2_32_ABS_LD_D: 3803 CHECK_REG_PAIR(r1); 3804 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); 3805 break; 3806 case OPC2_32_ABS_LD_DA: 3807 CHECK_REG_PAIR(r1); 3808 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); 3809 break; 3810 case OPC2_32_ABS_LD_W: 3811 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL); 3812 break; 3813 default: 3814 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3815 } 3816 } 3817 3818 static void decode_abs_ldb(DisasContext *ctx) 3819 { 3820 int32_t op2; 3821 int32_t r1; 3822 uint32_t address; 3823 TCGv temp; 3824 3825 r1 = MASK_OP_ABS_S1D(ctx->opcode); 3826 address = MASK_OP_ABS_OFF18(ctx->opcode); 3827 op2 = MASK_OP_ABS_OP2(ctx->opcode); 3828 3829 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 3830 3831 switch (op2) { 3832 case OPC2_32_ABS_LD_B: 3833 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_SB); 3834 break; 3835 case OPC2_32_ABS_LD_BU: 3836 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB); 3837 break; 3838 case OPC2_32_ABS_LD_H: 3839 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESW); 3840 break; 3841 case OPC2_32_ABS_LD_HU: 3842 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); 3843 break; 3844 default: 3845 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3846 } 3847 } 3848 3849 static void decode_abs_ldst_swap(DisasContext *ctx) 3850 { 3851 int32_t op2; 3852 int32_t r1; 3853 uint32_t address; 3854 TCGv temp; 3855 3856 r1 = MASK_OP_ABS_S1D(ctx->opcode); 3857 address = MASK_OP_ABS_OFF18(ctx->opcode); 3858 op2 = MASK_OP_ABS_OP2(ctx->opcode); 3859 3860 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 3861 3862 switch (op2) { 3863 case OPC2_32_ABS_LDMST: 3864 gen_ldmst(ctx, r1, temp); 3865 break; 3866 case OPC2_32_ABS_SWAP_W: 3867 gen_swap(ctx, r1, temp); 3868 break; 3869 default: 3870 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3871 } 3872 } 3873 3874 static void decode_abs_ldst_context(DisasContext *ctx) 3875 { 3876 uint32_t op2; 3877 int32_t off18; 3878 3879 off18 = MASK_OP_ABS_OFF18(ctx->opcode); 3880 op2 = MASK_OP_ABS_OP2(ctx->opcode); 3881 3882 switch (op2) { 3883 case OPC2_32_ABS_LDLCX: 3884 gen_helper_1arg(ldlcx, EA_ABS_FORMAT(off18)); 3885 break; 3886 case OPC2_32_ABS_LDUCX: 3887 gen_helper_1arg(lducx, EA_ABS_FORMAT(off18)); 3888 break; 3889 case OPC2_32_ABS_STLCX: 3890 gen_helper_1arg(stlcx, EA_ABS_FORMAT(off18)); 3891 break; 3892 case OPC2_32_ABS_STUCX: 3893 gen_helper_1arg(stucx, EA_ABS_FORMAT(off18)); 3894 break; 3895 default: 3896 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3897 } 3898 } 3899 3900 static void decode_abs_store(DisasContext *ctx) 3901 { 3902 int32_t op2; 3903 int32_t r1; 3904 uint32_t address; 3905 TCGv temp; 3906 3907 r1 = MASK_OP_ABS_S1D(ctx->opcode); 3908 address = MASK_OP_ABS_OFF18(ctx->opcode); 3909 op2 = MASK_OP_ABS_OP2(ctx->opcode); 3910 3911 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 3912 3913 switch (op2) { 3914 case OPC2_32_ABS_ST_A: 3915 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL); 3916 break; 3917 case OPC2_32_ABS_ST_D: 3918 CHECK_REG_PAIR(r1); 3919 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); 3920 break; 3921 case OPC2_32_ABS_ST_DA: 3922 CHECK_REG_PAIR(r1); 3923 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); 3924 break; 3925 case OPC2_32_ABS_ST_W: 3926 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL); 3927 break; 3928 default: 3929 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3930 } 3931 } 3932 3933 static void decode_abs_storeb_h(DisasContext *ctx) 3934 { 3935 int32_t op2; 3936 int32_t r1; 3937 uint32_t address; 3938 TCGv temp; 3939 3940 r1 = MASK_OP_ABS_S1D(ctx->opcode); 3941 address = MASK_OP_ABS_OFF18(ctx->opcode); 3942 op2 = MASK_OP_ABS_OP2(ctx->opcode); 3943 3944 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 3945 3946 switch (op2) { 3947 case OPC2_32_ABS_ST_B: 3948 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB); 3949 break; 3950 case OPC2_32_ABS_ST_H: 3951 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); 3952 break; 3953 default: 3954 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3955 } 3956 } 3957 3958 /* Bit-format */ 3959 3960 static void decode_bit_andacc(DisasContext *ctx) 3961 { 3962 uint32_t op2; 3963 int r1, r2, r3; 3964 int pos1, pos2; 3965 3966 r1 = MASK_OP_BIT_S1(ctx->opcode); 3967 r2 = MASK_OP_BIT_S2(ctx->opcode); 3968 r3 = MASK_OP_BIT_D(ctx->opcode); 3969 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 3970 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 3971 op2 = MASK_OP_BIT_OP2(ctx->opcode); 3972 3973 3974 switch (op2) { 3975 case OPC2_32_BIT_AND_AND_T: 3976 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 3977 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_and_tl); 3978 break; 3979 case OPC2_32_BIT_AND_ANDN_T: 3980 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 3981 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_and_tl); 3982 break; 3983 case OPC2_32_BIT_AND_NOR_T: 3984 if (tcg_op_supported(INDEX_op_andc_i32, TCG_TYPE_I32, 0)) { 3985 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 3986 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_andc_tl); 3987 } else { 3988 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 3989 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_and_tl); 3990 } 3991 break; 3992 case OPC2_32_BIT_AND_OR_T: 3993 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 3994 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_and_tl); 3995 break; 3996 default: 3997 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3998 } 3999 } 4000 4001 static void decode_bit_logical_t(DisasContext *ctx) 4002 { 4003 uint32_t op2; 4004 int r1, r2, r3; 4005 int pos1, pos2; 4006 r1 = MASK_OP_BIT_S1(ctx->opcode); 4007 r2 = MASK_OP_BIT_S2(ctx->opcode); 4008 r3 = MASK_OP_BIT_D(ctx->opcode); 4009 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4010 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4011 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4012 4013 switch (op2) { 4014 case OPC2_32_BIT_AND_T: 4015 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4016 pos1, pos2, &tcg_gen_and_tl); 4017 break; 4018 case OPC2_32_BIT_ANDN_T: 4019 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4020 pos1, pos2, &tcg_gen_andc_tl); 4021 break; 4022 case OPC2_32_BIT_NOR_T: 4023 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4024 pos1, pos2, &tcg_gen_nor_tl); 4025 break; 4026 case OPC2_32_BIT_OR_T: 4027 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4028 pos1, pos2, &tcg_gen_or_tl); 4029 break; 4030 default: 4031 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4032 } 4033 } 4034 4035 static void decode_bit_insert(DisasContext *ctx) 4036 { 4037 uint32_t op2; 4038 int r1, r2, r3; 4039 int pos1, pos2; 4040 TCGv temp; 4041 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4042 r1 = MASK_OP_BIT_S1(ctx->opcode); 4043 r2 = MASK_OP_BIT_S2(ctx->opcode); 4044 r3 = MASK_OP_BIT_D(ctx->opcode); 4045 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4046 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4047 4048 temp = tcg_temp_new(); 4049 4050 tcg_gen_shri_tl(temp, cpu_gpr_d[r2], pos2); 4051 if (op2 == OPC2_32_BIT_INSN_T) { 4052 tcg_gen_not_tl(temp, temp); 4053 } 4054 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, pos1, 1); 4055 } 4056 4057 static void decode_bit_logical_t2(DisasContext *ctx) 4058 { 4059 uint32_t op2; 4060 4061 int r1, r2, r3; 4062 int pos1, pos2; 4063 4064 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4065 r1 = MASK_OP_BIT_S1(ctx->opcode); 4066 r2 = MASK_OP_BIT_S2(ctx->opcode); 4067 r3 = MASK_OP_BIT_D(ctx->opcode); 4068 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4069 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4070 4071 switch (op2) { 4072 case OPC2_32_BIT_NAND_T: 4073 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4074 pos1, pos2, &tcg_gen_nand_tl); 4075 break; 4076 case OPC2_32_BIT_ORN_T: 4077 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4078 pos1, pos2, &tcg_gen_orc_tl); 4079 break; 4080 case OPC2_32_BIT_XNOR_T: 4081 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4082 pos1, pos2, &tcg_gen_eqv_tl); 4083 break; 4084 case OPC2_32_BIT_XOR_T: 4085 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4086 pos1, pos2, &tcg_gen_xor_tl); 4087 break; 4088 default: 4089 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4090 } 4091 } 4092 4093 static void decode_bit_orand(DisasContext *ctx) 4094 { 4095 uint32_t op2; 4096 4097 int r1, r2, r3; 4098 int pos1, pos2; 4099 4100 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4101 r1 = MASK_OP_BIT_S1(ctx->opcode); 4102 r2 = MASK_OP_BIT_S2(ctx->opcode); 4103 r3 = MASK_OP_BIT_D(ctx->opcode); 4104 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4105 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4106 4107 switch (op2) { 4108 case OPC2_32_BIT_OR_AND_T: 4109 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4110 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_or_tl); 4111 break; 4112 case OPC2_32_BIT_OR_ANDN_T: 4113 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4114 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_or_tl); 4115 break; 4116 case OPC2_32_BIT_OR_NOR_T: 4117 if (tcg_op_supported(INDEX_op_orc_i32, TCG_TYPE_I32, 0)) { 4118 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4119 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_orc_tl); 4120 } else { 4121 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4122 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_or_tl); 4123 } 4124 break; 4125 case OPC2_32_BIT_OR_OR_T: 4126 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4127 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_or_tl); 4128 break; 4129 default: 4130 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4131 } 4132 } 4133 4134 static void decode_bit_sh_logic1(DisasContext *ctx) 4135 { 4136 uint32_t op2; 4137 int r1, r2, r3; 4138 int pos1, pos2; 4139 TCGv temp; 4140 4141 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4142 r1 = MASK_OP_BIT_S1(ctx->opcode); 4143 r2 = MASK_OP_BIT_S2(ctx->opcode); 4144 r3 = MASK_OP_BIT_D(ctx->opcode); 4145 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4146 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4147 4148 temp = tcg_temp_new(); 4149 4150 switch (op2) { 4151 case OPC2_32_BIT_SH_AND_T: 4152 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4153 pos1, pos2, &tcg_gen_and_tl); 4154 break; 4155 case OPC2_32_BIT_SH_ANDN_T: 4156 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4157 pos1, pos2, &tcg_gen_andc_tl); 4158 break; 4159 case OPC2_32_BIT_SH_NOR_T: 4160 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4161 pos1, pos2, &tcg_gen_nor_tl); 4162 break; 4163 case OPC2_32_BIT_SH_OR_T: 4164 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4165 pos1, pos2, &tcg_gen_or_tl); 4166 break; 4167 default: 4168 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4169 } 4170 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1); 4171 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp); 4172 } 4173 4174 static void decode_bit_sh_logic2(DisasContext *ctx) 4175 { 4176 uint32_t op2; 4177 int r1, r2, r3; 4178 int pos1, pos2; 4179 TCGv temp; 4180 4181 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4182 r1 = MASK_OP_BIT_S1(ctx->opcode); 4183 r2 = MASK_OP_BIT_S2(ctx->opcode); 4184 r3 = MASK_OP_BIT_D(ctx->opcode); 4185 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4186 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4187 4188 temp = tcg_temp_new(); 4189 4190 switch (op2) { 4191 case OPC2_32_BIT_SH_NAND_T: 4192 gen_bit_1op(temp, cpu_gpr_d[r1] , cpu_gpr_d[r2] , 4193 pos1, pos2, &tcg_gen_nand_tl); 4194 break; 4195 case OPC2_32_BIT_SH_ORN_T: 4196 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4197 pos1, pos2, &tcg_gen_orc_tl); 4198 break; 4199 case OPC2_32_BIT_SH_XNOR_T: 4200 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4201 pos1, pos2, &tcg_gen_eqv_tl); 4202 break; 4203 case OPC2_32_BIT_SH_XOR_T: 4204 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4205 pos1, pos2, &tcg_gen_xor_tl); 4206 break; 4207 default: 4208 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4209 } 4210 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1); 4211 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp); 4212 } 4213 4214 /* BO-format */ 4215 4216 4217 static void decode_bo_addrmode_post_pre_base(DisasContext *ctx) 4218 { 4219 uint32_t op2; 4220 uint32_t off10; 4221 int32_t r1, r2; 4222 TCGv temp; 4223 4224 r1 = MASK_OP_BO_S1D(ctx->opcode); 4225 r2 = MASK_OP_BO_S2(ctx->opcode); 4226 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4227 op2 = MASK_OP_BO_OP2(ctx->opcode); 4228 4229 switch (op2) { 4230 case OPC2_32_BO_CACHEA_WI_SHORTOFF: 4231 case OPC2_32_BO_CACHEA_W_SHORTOFF: 4232 case OPC2_32_BO_CACHEA_I_SHORTOFF: 4233 /* instruction to access the cache */ 4234 break; 4235 case OPC2_32_BO_CACHEA_WI_POSTINC: 4236 case OPC2_32_BO_CACHEA_W_POSTINC: 4237 case OPC2_32_BO_CACHEA_I_POSTINC: 4238 /* instruction to access the cache, but we still need to handle 4239 the addressing mode */ 4240 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4241 break; 4242 case OPC2_32_BO_CACHEA_WI_PREINC: 4243 case OPC2_32_BO_CACHEA_W_PREINC: 4244 case OPC2_32_BO_CACHEA_I_PREINC: 4245 /* instruction to access the cache, but we still need to handle 4246 the addressing mode */ 4247 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4248 break; 4249 case OPC2_32_BO_CACHEI_WI_SHORTOFF: 4250 case OPC2_32_BO_CACHEI_W_SHORTOFF: 4251 if (!has_feature(ctx, TRICORE_FEATURE_131)) { 4252 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4253 } 4254 break; 4255 case OPC2_32_BO_CACHEI_W_POSTINC: 4256 case OPC2_32_BO_CACHEI_WI_POSTINC: 4257 if (has_feature(ctx, TRICORE_FEATURE_131)) { 4258 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4259 } else { 4260 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4261 } 4262 break; 4263 case OPC2_32_BO_CACHEI_W_PREINC: 4264 case OPC2_32_BO_CACHEI_WI_PREINC: 4265 if (has_feature(ctx, TRICORE_FEATURE_131)) { 4266 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4267 } else { 4268 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4269 } 4270 break; 4271 case OPC2_32_BO_ST_A_SHORTOFF: 4272 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL); 4273 break; 4274 case OPC2_32_BO_ST_A_POSTINC: 4275 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, 4276 MO_LESL); 4277 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4278 break; 4279 case OPC2_32_BO_ST_A_PREINC: 4280 gen_st_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL); 4281 break; 4282 case OPC2_32_BO_ST_B_SHORTOFF: 4283 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); 4284 break; 4285 case OPC2_32_BO_ST_B_POSTINC: 4286 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4287 MO_UB); 4288 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4289 break; 4290 case OPC2_32_BO_ST_B_PREINC: 4291 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); 4292 break; 4293 case OPC2_32_BO_ST_D_SHORTOFF: 4294 CHECK_REG_PAIR(r1); 4295 gen_offset_st_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], 4296 off10, ctx); 4297 break; 4298 case OPC2_32_BO_ST_D_POSTINC: 4299 CHECK_REG_PAIR(r1); 4300 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx); 4301 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4302 break; 4303 case OPC2_32_BO_ST_D_PREINC: 4304 CHECK_REG_PAIR(r1); 4305 temp = tcg_temp_new(); 4306 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4307 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); 4308 tcg_gen_mov_tl(cpu_gpr_a[r2], temp); 4309 break; 4310 case OPC2_32_BO_ST_DA_SHORTOFF: 4311 CHECK_REG_PAIR(r1); 4312 gen_offset_st_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], 4313 off10, ctx); 4314 break; 4315 case OPC2_32_BO_ST_DA_POSTINC: 4316 CHECK_REG_PAIR(r1); 4317 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx); 4318 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4319 break; 4320 case OPC2_32_BO_ST_DA_PREINC: 4321 CHECK_REG_PAIR(r1); 4322 temp = tcg_temp_new(); 4323 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4324 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); 4325 tcg_gen_mov_tl(cpu_gpr_a[r2], temp); 4326 break; 4327 case OPC2_32_BO_ST_H_SHORTOFF: 4328 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4329 break; 4330 case OPC2_32_BO_ST_H_POSTINC: 4331 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4332 MO_LEUW); 4333 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4334 break; 4335 case OPC2_32_BO_ST_H_PREINC: 4336 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4337 break; 4338 case OPC2_32_BO_ST_Q_SHORTOFF: 4339 temp = tcg_temp_new(); 4340 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4341 gen_offset_st(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW); 4342 break; 4343 case OPC2_32_BO_ST_Q_POSTINC: 4344 temp = tcg_temp_new(); 4345 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4346 tcg_gen_qemu_st_tl(temp, cpu_gpr_a[r2], ctx->mem_idx, 4347 MO_LEUW); 4348 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4349 break; 4350 case OPC2_32_BO_ST_Q_PREINC: 4351 temp = tcg_temp_new(); 4352 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4353 gen_st_preincr(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW); 4354 break; 4355 case OPC2_32_BO_ST_W_SHORTOFF: 4356 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4357 break; 4358 case OPC2_32_BO_ST_W_POSTINC: 4359 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4360 MO_LEUL); 4361 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4362 break; 4363 case OPC2_32_BO_ST_W_PREINC: 4364 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4365 break; 4366 default: 4367 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4368 } 4369 } 4370 4371 static void decode_bo_addrmode_bitreverse_circular(DisasContext *ctx) 4372 { 4373 uint32_t op2; 4374 uint32_t off10; 4375 int32_t r1, r2; 4376 TCGv temp, temp2, t_off10; 4377 4378 r1 = MASK_OP_BO_S1D(ctx->opcode); 4379 r2 = MASK_OP_BO_S2(ctx->opcode); 4380 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4381 op2 = MASK_OP_BO_OP2(ctx->opcode); 4382 4383 temp = tcg_temp_new(); 4384 temp2 = tcg_temp_new(); 4385 t_off10 = tcg_constant_i32(off10); 4386 CHECK_REG_PAIR(r2); 4387 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]); 4388 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4389 4390 switch (op2) { 4391 case OPC2_32_BO_CACHEA_WI_BR: 4392 case OPC2_32_BO_CACHEA_W_BR: 4393 case OPC2_32_BO_CACHEA_I_BR: 4394 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4395 break; 4396 case OPC2_32_BO_CACHEA_WI_CIRC: 4397 case OPC2_32_BO_CACHEA_W_CIRC: 4398 case OPC2_32_BO_CACHEA_I_CIRC: 4399 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4400 break; 4401 case OPC2_32_BO_ST_A_BR: 4402 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4403 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4404 break; 4405 case OPC2_32_BO_ST_A_CIRC: 4406 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4407 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4408 break; 4409 case OPC2_32_BO_ST_B_BR: 4410 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); 4411 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4412 break; 4413 case OPC2_32_BO_ST_B_CIRC: 4414 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); 4415 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4416 break; 4417 case OPC2_32_BO_ST_D_BR: 4418 CHECK_REG_PAIR(r1); 4419 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx); 4420 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4421 break; 4422 case OPC2_32_BO_ST_D_CIRC: 4423 CHECK_REG_PAIR(r1); 4424 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4425 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); 4426 tcg_gen_addi_tl(temp, temp, 4); 4427 tcg_gen_rem_tl(temp, temp, temp2); 4428 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4429 tcg_gen_qemu_st_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL); 4430 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4431 break; 4432 case OPC2_32_BO_ST_DA_BR: 4433 CHECK_REG_PAIR(r1); 4434 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx); 4435 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4436 break; 4437 case OPC2_32_BO_ST_DA_CIRC: 4438 CHECK_REG_PAIR(r1); 4439 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4440 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); 4441 tcg_gen_addi_tl(temp, temp, 4); 4442 tcg_gen_rem_tl(temp, temp, temp2); 4443 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4444 tcg_gen_qemu_st_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL); 4445 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4446 break; 4447 case OPC2_32_BO_ST_H_BR: 4448 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4449 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4450 break; 4451 case OPC2_32_BO_ST_H_CIRC: 4452 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4453 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4454 break; 4455 case OPC2_32_BO_ST_Q_BR: 4456 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4457 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW); 4458 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4459 break; 4460 case OPC2_32_BO_ST_Q_CIRC: 4461 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4462 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW); 4463 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4464 break; 4465 case OPC2_32_BO_ST_W_BR: 4466 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4467 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4468 break; 4469 case OPC2_32_BO_ST_W_CIRC: 4470 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4471 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4472 break; 4473 default: 4474 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4475 } 4476 } 4477 4478 static void decode_bo_addrmode_ld_post_pre_base(DisasContext *ctx) 4479 { 4480 uint32_t op2; 4481 uint32_t off10; 4482 int32_t r1, r2; 4483 TCGv temp; 4484 4485 r1 = MASK_OP_BO_S1D(ctx->opcode); 4486 r2 = MASK_OP_BO_S2(ctx->opcode); 4487 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4488 op2 = MASK_OP_BO_OP2(ctx->opcode); 4489 4490 switch (op2) { 4491 case OPC2_32_BO_LD_A_SHORTOFF: 4492 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4493 break; 4494 case OPC2_32_BO_LD_A_POSTINC: 4495 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, 4496 MO_LEUL); 4497 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4498 break; 4499 case OPC2_32_BO_LD_A_PREINC: 4500 gen_ld_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4501 break; 4502 case OPC2_32_BO_LD_B_SHORTOFF: 4503 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB); 4504 break; 4505 case OPC2_32_BO_LD_B_POSTINC: 4506 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4507 MO_SB); 4508 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4509 break; 4510 case OPC2_32_BO_LD_B_PREINC: 4511 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB); 4512 break; 4513 case OPC2_32_BO_LD_BU_SHORTOFF: 4514 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); 4515 break; 4516 case OPC2_32_BO_LD_BU_POSTINC: 4517 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4518 MO_UB); 4519 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4520 break; 4521 case OPC2_32_BO_LD_BU_PREINC: 4522 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); 4523 break; 4524 case OPC2_32_BO_LD_D_SHORTOFF: 4525 CHECK_REG_PAIR(r1); 4526 gen_offset_ld_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], 4527 off10, ctx); 4528 break; 4529 case OPC2_32_BO_LD_D_POSTINC: 4530 CHECK_REG_PAIR(r1); 4531 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx); 4532 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4533 break; 4534 case OPC2_32_BO_LD_D_PREINC: 4535 CHECK_REG_PAIR(r1); 4536 temp = tcg_temp_new(); 4537 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4538 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); 4539 tcg_gen_mov_tl(cpu_gpr_a[r2], temp); 4540 break; 4541 case OPC2_32_BO_LD_DA_SHORTOFF: 4542 CHECK_REG_PAIR(r1); 4543 gen_offset_ld_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], 4544 off10, ctx); 4545 break; 4546 case OPC2_32_BO_LD_DA_POSTINC: 4547 CHECK_REG_PAIR(r1); 4548 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx); 4549 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4550 break; 4551 case OPC2_32_BO_LD_DA_PREINC: 4552 CHECK_REG_PAIR(r1); 4553 temp = tcg_temp_new(); 4554 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4555 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); 4556 tcg_gen_mov_tl(cpu_gpr_a[r2], temp); 4557 break; 4558 case OPC2_32_BO_LD_H_SHORTOFF: 4559 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW); 4560 break; 4561 case OPC2_32_BO_LD_H_POSTINC: 4562 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4563 MO_LESW); 4564 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4565 break; 4566 case OPC2_32_BO_LD_H_PREINC: 4567 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW); 4568 break; 4569 case OPC2_32_BO_LD_HU_SHORTOFF: 4570 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4571 break; 4572 case OPC2_32_BO_LD_HU_POSTINC: 4573 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4574 MO_LEUW); 4575 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4576 break; 4577 case OPC2_32_BO_LD_HU_PREINC: 4578 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4579 break; 4580 case OPC2_32_BO_LD_Q_SHORTOFF: 4581 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4582 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 4583 break; 4584 case OPC2_32_BO_LD_Q_POSTINC: 4585 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4586 MO_LEUW); 4587 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 4588 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4589 break; 4590 case OPC2_32_BO_LD_Q_PREINC: 4591 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4592 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 4593 break; 4594 case OPC2_32_BO_LD_W_SHORTOFF: 4595 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4596 break; 4597 case OPC2_32_BO_LD_W_POSTINC: 4598 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4599 MO_LEUL); 4600 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4601 break; 4602 case OPC2_32_BO_LD_W_PREINC: 4603 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4604 break; 4605 default: 4606 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4607 } 4608 } 4609 4610 static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx) 4611 { 4612 uint32_t op2; 4613 uint32_t off10; 4614 int r1, r2; 4615 TCGv temp, temp2, t_off10; 4616 4617 r1 = MASK_OP_BO_S1D(ctx->opcode); 4618 r2 = MASK_OP_BO_S2(ctx->opcode); 4619 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4620 op2 = MASK_OP_BO_OP2(ctx->opcode); 4621 4622 temp = tcg_temp_new(); 4623 temp2 = tcg_temp_new(); 4624 t_off10 = tcg_constant_i32(off10); 4625 CHECK_REG_PAIR(r2); 4626 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]); 4627 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4628 4629 4630 switch (op2) { 4631 case OPC2_32_BO_LD_A_BR: 4632 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4633 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4634 break; 4635 case OPC2_32_BO_LD_A_CIRC: 4636 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4637 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4638 break; 4639 case OPC2_32_BO_LD_B_BR: 4640 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB); 4641 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4642 break; 4643 case OPC2_32_BO_LD_B_CIRC: 4644 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB); 4645 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4646 break; 4647 case OPC2_32_BO_LD_BU_BR: 4648 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); 4649 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4650 break; 4651 case OPC2_32_BO_LD_BU_CIRC: 4652 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); 4653 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4654 break; 4655 case OPC2_32_BO_LD_D_BR: 4656 CHECK_REG_PAIR(r1); 4657 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx); 4658 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4659 break; 4660 case OPC2_32_BO_LD_D_CIRC: 4661 CHECK_REG_PAIR(r1); 4662 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4663 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); 4664 tcg_gen_addi_tl(temp, temp, 4); 4665 tcg_gen_rem_tl(temp, temp, temp2); 4666 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4667 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL); 4668 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4669 break; 4670 case OPC2_32_BO_LD_DA_BR: 4671 CHECK_REG_PAIR(r1); 4672 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx); 4673 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4674 break; 4675 case OPC2_32_BO_LD_DA_CIRC: 4676 CHECK_REG_PAIR(r1); 4677 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4678 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); 4679 tcg_gen_addi_tl(temp, temp, 4); 4680 tcg_gen_rem_tl(temp, temp, temp2); 4681 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4682 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL); 4683 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4684 break; 4685 case OPC2_32_BO_LD_H_BR: 4686 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW); 4687 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4688 break; 4689 case OPC2_32_BO_LD_H_CIRC: 4690 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW); 4691 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4692 break; 4693 case OPC2_32_BO_LD_HU_BR: 4694 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4695 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4696 break; 4697 case OPC2_32_BO_LD_HU_CIRC: 4698 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4699 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4700 break; 4701 case OPC2_32_BO_LD_Q_BR: 4702 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4703 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 4704 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4705 break; 4706 case OPC2_32_BO_LD_Q_CIRC: 4707 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4708 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 4709 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4710 break; 4711 case OPC2_32_BO_LD_W_BR: 4712 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4713 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4714 break; 4715 case OPC2_32_BO_LD_W_CIRC: 4716 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4717 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4718 break; 4719 default: 4720 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4721 } 4722 } 4723 4724 static void decode_bo_addrmode_stctx_post_pre_base(DisasContext *ctx) 4725 { 4726 uint32_t op2; 4727 uint32_t off10; 4728 int r1, r2; 4729 4730 TCGv temp; 4731 4732 r1 = MASK_OP_BO_S1D(ctx->opcode); 4733 r2 = MASK_OP_BO_S2(ctx->opcode); 4734 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4735 op2 = MASK_OP_BO_OP2(ctx->opcode); 4736 4737 4738 temp = tcg_temp_new(); 4739 4740 switch (op2) { 4741 case OPC2_32_BO_LDLCX_SHORTOFF: 4742 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4743 gen_helper_ldlcx(tcg_env, temp); 4744 break; 4745 case OPC2_32_BO_LDMST_SHORTOFF: 4746 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4747 gen_ldmst(ctx, r1, temp); 4748 break; 4749 case OPC2_32_BO_LDMST_POSTINC: 4750 gen_ldmst(ctx, r1, cpu_gpr_a[r2]); 4751 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4752 break; 4753 case OPC2_32_BO_LDMST_PREINC: 4754 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4755 gen_ldmst(ctx, r1, cpu_gpr_a[r2]); 4756 break; 4757 case OPC2_32_BO_LDUCX_SHORTOFF: 4758 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4759 gen_helper_lducx(tcg_env, temp); 4760 break; 4761 case OPC2_32_BO_LEA_SHORTOFF: 4762 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], off10); 4763 break; 4764 case OPC2_32_BO_STLCX_SHORTOFF: 4765 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4766 gen_helper_stlcx(tcg_env, temp); 4767 break; 4768 case OPC2_32_BO_STUCX_SHORTOFF: 4769 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4770 gen_helper_stucx(tcg_env, temp); 4771 break; 4772 case OPC2_32_BO_SWAP_W_SHORTOFF: 4773 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4774 gen_swap(ctx, r1, temp); 4775 break; 4776 case OPC2_32_BO_SWAP_W_POSTINC: 4777 gen_swap(ctx, r1, cpu_gpr_a[r2]); 4778 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4779 break; 4780 case OPC2_32_BO_SWAP_W_PREINC: 4781 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4782 gen_swap(ctx, r1, cpu_gpr_a[r2]); 4783 break; 4784 case OPC2_32_BO_CMPSWAP_W_SHORTOFF: 4785 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4786 gen_cmpswap(ctx, r1, temp); 4787 break; 4788 case OPC2_32_BO_CMPSWAP_W_POSTINC: 4789 gen_cmpswap(ctx, r1, cpu_gpr_a[r2]); 4790 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4791 break; 4792 case OPC2_32_BO_CMPSWAP_W_PREINC: 4793 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4794 gen_cmpswap(ctx, r1, cpu_gpr_a[r2]); 4795 break; 4796 case OPC2_32_BO_SWAPMSK_W_SHORTOFF: 4797 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4798 gen_swapmsk(ctx, r1, temp); 4799 break; 4800 case OPC2_32_BO_SWAPMSK_W_POSTINC: 4801 gen_swapmsk(ctx, r1, cpu_gpr_a[r2]); 4802 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4803 break; 4804 case OPC2_32_BO_SWAPMSK_W_PREINC: 4805 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4806 gen_swapmsk(ctx, r1, cpu_gpr_a[r2]); 4807 break; 4808 default: 4809 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4810 } 4811 } 4812 4813 static void decode_bo_addrmode_ldmst_bitreverse_circular(DisasContext *ctx) 4814 { 4815 uint32_t op2; 4816 uint32_t off10; 4817 int r1, r2; 4818 TCGv temp, temp2, t_off10; 4819 4820 r1 = MASK_OP_BO_S1D(ctx->opcode); 4821 r2 = MASK_OP_BO_S2(ctx->opcode); 4822 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4823 op2 = MASK_OP_BO_OP2(ctx->opcode); 4824 4825 temp = tcg_temp_new(); 4826 temp2 = tcg_temp_new(); 4827 t_off10 = tcg_constant_i32(off10); 4828 CHECK_REG_PAIR(r2); 4829 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]); 4830 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4831 4832 switch (op2) { 4833 case OPC2_32_BO_LDMST_BR: 4834 gen_ldmst(ctx, r1, temp2); 4835 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4836 break; 4837 case OPC2_32_BO_LDMST_CIRC: 4838 gen_ldmst(ctx, r1, temp2); 4839 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4840 break; 4841 case OPC2_32_BO_SWAP_W_BR: 4842 gen_swap(ctx, r1, temp2); 4843 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4844 break; 4845 case OPC2_32_BO_SWAP_W_CIRC: 4846 gen_swap(ctx, r1, temp2); 4847 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4848 break; 4849 case OPC2_32_BO_CMPSWAP_W_BR: 4850 gen_cmpswap(ctx, r1, temp2); 4851 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4852 break; 4853 case OPC2_32_BO_CMPSWAP_W_CIRC: 4854 gen_cmpswap(ctx, r1, temp2); 4855 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4856 break; 4857 case OPC2_32_BO_SWAPMSK_W_BR: 4858 gen_swapmsk(ctx, r1, temp2); 4859 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4860 break; 4861 case OPC2_32_BO_SWAPMSK_W_CIRC: 4862 gen_swapmsk(ctx, r1, temp2); 4863 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4864 break; 4865 default: 4866 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4867 } 4868 } 4869 4870 static void decode_bol_opc(DisasContext *ctx, int32_t op1) 4871 { 4872 int r1, r2; 4873 int32_t address; 4874 TCGv temp; 4875 4876 r1 = MASK_OP_BOL_S1D(ctx->opcode); 4877 r2 = MASK_OP_BOL_S2(ctx->opcode); 4878 address = MASK_OP_BOL_OFF16_SEXT(ctx->opcode); 4879 4880 switch (op1) { 4881 case OPC1_32_BOL_LD_A_LONGOFF: 4882 temp = tcg_temp_new(); 4883 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address); 4884 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LEUL); 4885 break; 4886 case OPC1_32_BOL_LD_W_LONGOFF: 4887 temp = tcg_temp_new(); 4888 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address); 4889 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUL); 4890 break; 4891 case OPC1_32_BOL_LEA_LONGOFF: 4892 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], address); 4893 break; 4894 case OPC1_32_BOL_ST_A_LONGOFF: 4895 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4896 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], address, MO_LEUL); 4897 } else { 4898 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4899 } 4900 break; 4901 case OPC1_32_BOL_ST_W_LONGOFF: 4902 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUL); 4903 break; 4904 case OPC1_32_BOL_LD_B_LONGOFF: 4905 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4906 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB); 4907 } else { 4908 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4909 } 4910 break; 4911 case OPC1_32_BOL_LD_BU_LONGOFF: 4912 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4913 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_UB); 4914 } else { 4915 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4916 } 4917 break; 4918 case OPC1_32_BOL_LD_H_LONGOFF: 4919 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4920 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW); 4921 } else { 4922 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4923 } 4924 break; 4925 case OPC1_32_BOL_LD_HU_LONGOFF: 4926 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4927 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUW); 4928 } else { 4929 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4930 } 4931 break; 4932 case OPC1_32_BOL_ST_B_LONGOFF: 4933 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4934 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB); 4935 } else { 4936 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4937 } 4938 break; 4939 case OPC1_32_BOL_ST_H_LONGOFF: 4940 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4941 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW); 4942 } else { 4943 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4944 } 4945 break; 4946 default: 4947 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4948 } 4949 } 4950 4951 /* RC format */ 4952 static void decode_rc_logical_shift(DisasContext *ctx) 4953 { 4954 uint32_t op2; 4955 int r1, r2; 4956 int32_t const9; 4957 TCGv temp; 4958 4959 r2 = MASK_OP_RC_D(ctx->opcode); 4960 r1 = MASK_OP_RC_S1(ctx->opcode); 4961 const9 = MASK_OP_RC_CONST9(ctx->opcode); 4962 op2 = MASK_OP_RC_OP2(ctx->opcode); 4963 4964 switch (op2) { 4965 case OPC2_32_RC_AND: 4966 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 4967 break; 4968 case OPC2_32_RC_ANDN: 4969 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9); 4970 break; 4971 case OPC2_32_RC_NAND: 4972 temp = tcg_temp_new(); 4973 tcg_gen_movi_tl(temp, const9); 4974 tcg_gen_nand_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp); 4975 break; 4976 case OPC2_32_RC_NOR: 4977 temp = tcg_temp_new(); 4978 tcg_gen_movi_tl(temp, const9); 4979 tcg_gen_nor_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp); 4980 break; 4981 case OPC2_32_RC_OR: 4982 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 4983 break; 4984 case OPC2_32_RC_ORN: 4985 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9); 4986 break; 4987 case OPC2_32_RC_SH: 4988 const9 = sextract32(const9, 0, 6); 4989 gen_shi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 4990 break; 4991 case OPC2_32_RC_SH_H: 4992 const9 = sextract32(const9, 0, 5); 4993 gen_sh_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 4994 break; 4995 case OPC2_32_RC_SHA: 4996 const9 = sextract32(const9, 0, 6); 4997 gen_shaci(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 4998 break; 4999 case OPC2_32_RC_SHA_H: 5000 const9 = sextract32(const9, 0, 5); 5001 gen_sha_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5002 break; 5003 case OPC2_32_RC_SHAS: 5004 gen_shasi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5005 break; 5006 case OPC2_32_RC_XNOR: 5007 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5008 tcg_gen_not_tl(cpu_gpr_d[r2], cpu_gpr_d[r2]); 5009 break; 5010 case OPC2_32_RC_XOR: 5011 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5012 break; 5013 case OPC2_32_RC_SHUFFLE: 5014 if (has_feature(ctx, TRICORE_FEATURE_162)) { 5015 temp = tcg_constant_i32(const9); 5016 gen_helper_shuffle(cpu_gpr_d[r2], cpu_gpr_d[r1], temp); 5017 } else { 5018 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5019 } 5020 break; 5021 default: 5022 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5023 } 5024 } 5025 5026 static void decode_rc_accumulator(DisasContext *ctx) 5027 { 5028 uint32_t op2; 5029 int r1, r2; 5030 int16_t const9; 5031 5032 TCGv temp; 5033 5034 r2 = MASK_OP_RC_D(ctx->opcode); 5035 r1 = MASK_OP_RC_S1(ctx->opcode); 5036 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode); 5037 5038 op2 = MASK_OP_RC_OP2(ctx->opcode); 5039 5040 temp = tcg_temp_new(); 5041 5042 switch (op2) { 5043 case OPC2_32_RC_ABSDIF: 5044 gen_absdifi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5045 break; 5046 case OPC2_32_RC_ABSDIFS: 5047 gen_absdifsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5048 break; 5049 case OPC2_32_RC_ADD: 5050 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5051 break; 5052 case OPC2_32_RC_ADDC: 5053 gen_addci_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5054 break; 5055 case OPC2_32_RC_ADDS: 5056 gen_addsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5057 break; 5058 case OPC2_32_RC_ADDS_U: 5059 gen_addsui(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5060 break; 5061 case OPC2_32_RC_ADDX: 5062 gen_addi_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5063 break; 5064 case OPC2_32_RC_AND_EQ: 5065 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], 5066 const9, &tcg_gen_and_tl); 5067 break; 5068 case OPC2_32_RC_AND_GE: 5069 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5070 const9, &tcg_gen_and_tl); 5071 break; 5072 case OPC2_32_RC_AND_GE_U: 5073 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5074 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5075 const9, &tcg_gen_and_tl); 5076 break; 5077 case OPC2_32_RC_AND_LT: 5078 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], 5079 const9, &tcg_gen_and_tl); 5080 break; 5081 case OPC2_32_RC_AND_LT_U: 5082 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5083 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5084 const9, &tcg_gen_and_tl); 5085 break; 5086 case OPC2_32_RC_AND_NE: 5087 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5088 const9, &tcg_gen_and_tl); 5089 break; 5090 case OPC2_32_RC_EQ: 5091 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5092 break; 5093 case OPC2_32_RC_EQANY_B: 5094 gen_eqany_bi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5095 break; 5096 case OPC2_32_RC_EQANY_H: 5097 gen_eqany_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5098 break; 5099 case OPC2_32_RC_GE: 5100 tcg_gen_setcondi_tl(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5101 break; 5102 case OPC2_32_RC_GE_U: 5103 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5104 tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5105 break; 5106 case OPC2_32_RC_LT: 5107 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5108 break; 5109 case OPC2_32_RC_LT_U: 5110 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5111 tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5112 break; 5113 case OPC2_32_RC_MAX: 5114 tcg_gen_movi_tl(temp, const9); 5115 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, 5116 cpu_gpr_d[r1], temp); 5117 break; 5118 case OPC2_32_RC_MAX_U: 5119 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode)); 5120 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, 5121 cpu_gpr_d[r1], temp); 5122 break; 5123 case OPC2_32_RC_MIN: 5124 tcg_gen_movi_tl(temp, const9); 5125 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, 5126 cpu_gpr_d[r1], temp); 5127 break; 5128 case OPC2_32_RC_MIN_U: 5129 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode)); 5130 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, 5131 cpu_gpr_d[r1], temp); 5132 break; 5133 case OPC2_32_RC_NE: 5134 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5135 break; 5136 case OPC2_32_RC_OR_EQ: 5137 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], 5138 const9, &tcg_gen_or_tl); 5139 break; 5140 case OPC2_32_RC_OR_GE: 5141 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5142 const9, &tcg_gen_or_tl); 5143 break; 5144 case OPC2_32_RC_OR_GE_U: 5145 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5146 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5147 const9, &tcg_gen_or_tl); 5148 break; 5149 case OPC2_32_RC_OR_LT: 5150 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], 5151 const9, &tcg_gen_or_tl); 5152 break; 5153 case OPC2_32_RC_OR_LT_U: 5154 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5155 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5156 const9, &tcg_gen_or_tl); 5157 break; 5158 case OPC2_32_RC_OR_NE: 5159 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5160 const9, &tcg_gen_or_tl); 5161 break; 5162 case OPC2_32_RC_RSUB: 5163 tcg_gen_movi_tl(temp, const9); 5164 gen_sub_d(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]); 5165 break; 5166 case OPC2_32_RC_RSUBS: 5167 tcg_gen_movi_tl(temp, const9); 5168 gen_subs(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]); 5169 break; 5170 case OPC2_32_RC_RSUBS_U: 5171 tcg_gen_movi_tl(temp, const9); 5172 gen_subsu(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]); 5173 break; 5174 case OPC2_32_RC_SH_EQ: 5175 gen_sh_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5176 break; 5177 case OPC2_32_RC_SH_GE: 5178 gen_sh_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5179 break; 5180 case OPC2_32_RC_SH_GE_U: 5181 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5182 gen_sh_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5183 break; 5184 case OPC2_32_RC_SH_LT: 5185 gen_sh_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5186 break; 5187 case OPC2_32_RC_SH_LT_U: 5188 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5189 gen_sh_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5190 break; 5191 case OPC2_32_RC_SH_NE: 5192 gen_sh_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5193 break; 5194 case OPC2_32_RC_XOR_EQ: 5195 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], 5196 const9, &tcg_gen_xor_tl); 5197 break; 5198 case OPC2_32_RC_XOR_GE: 5199 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5200 const9, &tcg_gen_xor_tl); 5201 break; 5202 case OPC2_32_RC_XOR_GE_U: 5203 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5204 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5205 const9, &tcg_gen_xor_tl); 5206 break; 5207 case OPC2_32_RC_XOR_LT: 5208 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], 5209 const9, &tcg_gen_xor_tl); 5210 break; 5211 case OPC2_32_RC_XOR_LT_U: 5212 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5213 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5214 const9, &tcg_gen_xor_tl); 5215 break; 5216 case OPC2_32_RC_XOR_NE: 5217 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5218 const9, &tcg_gen_xor_tl); 5219 break; 5220 default: 5221 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5222 } 5223 } 5224 5225 static void decode_rc_serviceroutine(DisasContext *ctx) 5226 { 5227 uint32_t op2; 5228 uint32_t const9; 5229 5230 op2 = MASK_OP_RC_OP2(ctx->opcode); 5231 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5232 5233 switch (op2) { 5234 case OPC2_32_RC_BISR: 5235 if (ctx->priv == TRICORE_PRIV_SM) { 5236 gen_helper_1arg(bisr, const9); 5237 } else { 5238 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); 5239 } 5240 break; 5241 case OPC2_32_RC_SYSCALL: 5242 generate_trap(ctx, TRAPC_SYSCALL, const9 & 0xff); 5243 break; 5244 default: 5245 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5246 } 5247 } 5248 5249 static void decode_rc_mul(DisasContext *ctx) 5250 { 5251 uint32_t op2; 5252 int r1, r2; 5253 int16_t const9; 5254 5255 r2 = MASK_OP_RC_D(ctx->opcode); 5256 r1 = MASK_OP_RC_S1(ctx->opcode); 5257 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode); 5258 5259 op2 = MASK_OP_RC_OP2(ctx->opcode); 5260 5261 switch (op2) { 5262 case OPC2_32_RC_MUL_32: 5263 gen_muli_i32s(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5264 break; 5265 case OPC2_32_RC_MUL_64: 5266 CHECK_REG_PAIR(r2); 5267 gen_muli_i64s(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9); 5268 break; 5269 case OPC2_32_RC_MULS_32: 5270 gen_mulsi_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5271 break; 5272 case OPC2_32_RC_MUL_U_64: 5273 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5274 CHECK_REG_PAIR(r2); 5275 gen_muli_i64u(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9); 5276 break; 5277 case OPC2_32_RC_MULS_U_32: 5278 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5279 gen_mulsui_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5280 break; 5281 default: 5282 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5283 } 5284 } 5285 5286 /* RCPW format */ 5287 static void decode_rcpw_insert(DisasContext *ctx) 5288 { 5289 uint32_t op2; 5290 int r1, r2; 5291 int32_t pos, width, const4; 5292 5293 TCGv temp; 5294 5295 op2 = MASK_OP_RCPW_OP2(ctx->opcode); 5296 r1 = MASK_OP_RCPW_S1(ctx->opcode); 5297 r2 = MASK_OP_RCPW_D(ctx->opcode); 5298 const4 = MASK_OP_RCPW_CONST4(ctx->opcode); 5299 width = MASK_OP_RCPW_WIDTH(ctx->opcode); 5300 pos = MASK_OP_RCPW_POS(ctx->opcode); 5301 5302 switch (op2) { 5303 case OPC2_32_RCPW_IMASK: 5304 CHECK_REG_PAIR(r2); 5305 /* if pos + width > 32 undefined result */ 5306 if (pos + width <= 32) { 5307 tcg_gen_movi_tl(cpu_gpr_d[r2+1], ((1u << width) - 1) << pos); 5308 tcg_gen_movi_tl(cpu_gpr_d[r2], (const4 << pos)); 5309 } 5310 break; 5311 case OPC2_32_RCPW_INSERT: 5312 /* tcg_gen_deposit_tl() does not handle the case of width = 0 */ 5313 if (width == 0) { 5314 tcg_gen_mov_tl(cpu_gpr_d[r2], cpu_gpr_d[r1]); 5315 /* if pos + width > 32 undefined result */ 5316 } else if (pos + width <= 32) { 5317 temp = tcg_constant_i32(const4); 5318 tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, width); 5319 } 5320 break; 5321 default: 5322 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5323 } 5324 } 5325 5326 /* RCRW format */ 5327 5328 static void decode_rcrw_insert(DisasContext *ctx) 5329 { 5330 uint32_t op2; 5331 int r1, r3, r4; 5332 int32_t width, const4; 5333 5334 TCGv temp, temp2, temp3; 5335 5336 op2 = MASK_OP_RCRW_OP2(ctx->opcode); 5337 r1 = MASK_OP_RCRW_S1(ctx->opcode); 5338 r3 = MASK_OP_RCRW_S3(ctx->opcode); 5339 r4 = MASK_OP_RCRW_D(ctx->opcode); 5340 width = MASK_OP_RCRW_WIDTH(ctx->opcode); 5341 const4 = MASK_OP_RCRW_CONST4(ctx->opcode); 5342 5343 temp = tcg_temp_new(); 5344 temp2 = tcg_temp_new(); 5345 5346 switch (op2) { 5347 case OPC2_32_RCRW_IMASK: 5348 CHECK_REG_PAIR(r4); 5349 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); 5350 tcg_gen_movi_tl(temp2, (1 << width) - 1); 5351 tcg_gen_shl_tl(cpu_gpr_d[r4 + 1], temp2, temp); 5352 tcg_gen_movi_tl(temp2, const4); 5353 tcg_gen_shl_tl(cpu_gpr_d[r4], temp2, temp); 5354 break; 5355 case OPC2_32_RCRW_INSERT: 5356 temp3 = tcg_temp_new(); 5357 5358 tcg_gen_movi_tl(temp, width); 5359 tcg_gen_movi_tl(temp2, const4); 5360 tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f); 5361 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], temp2, temp, temp3); 5362 break; 5363 default: 5364 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5365 } 5366 } 5367 5368 /* RCR format */ 5369 5370 static void decode_rcr_cond_select(DisasContext *ctx) 5371 { 5372 uint32_t op2; 5373 int r1, r3, r4; 5374 int32_t const9; 5375 5376 TCGv temp, temp2; 5377 5378 op2 = MASK_OP_RCR_OP2(ctx->opcode); 5379 r1 = MASK_OP_RCR_S1(ctx->opcode); 5380 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode); 5381 r3 = MASK_OP_RCR_S3(ctx->opcode); 5382 r4 = MASK_OP_RCR_D(ctx->opcode); 5383 5384 switch (op2) { 5385 case OPC2_32_RCR_CADD: 5386 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const9, cpu_gpr_d[r4], 5387 cpu_gpr_d[r3]); 5388 break; 5389 case OPC2_32_RCR_CADDN: 5390 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const9, cpu_gpr_d[r4], 5391 cpu_gpr_d[r3]); 5392 break; 5393 case OPC2_32_RCR_SEL: 5394 temp = tcg_constant_i32(0); 5395 temp2 = tcg_constant_i32(const9); 5396 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, 5397 cpu_gpr_d[r1], temp2); 5398 break; 5399 case OPC2_32_RCR_SELN: 5400 temp = tcg_constant_i32(0); 5401 temp2 = tcg_constant_i32(const9); 5402 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, 5403 cpu_gpr_d[r1], temp2); 5404 break; 5405 default: 5406 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5407 } 5408 } 5409 5410 static void decode_rcr_madd(DisasContext *ctx) 5411 { 5412 uint32_t op2; 5413 int r1, r3, r4; 5414 int32_t const9; 5415 5416 5417 op2 = MASK_OP_RCR_OP2(ctx->opcode); 5418 r1 = MASK_OP_RCR_S1(ctx->opcode); 5419 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode); 5420 r3 = MASK_OP_RCR_S3(ctx->opcode); 5421 r4 = MASK_OP_RCR_D(ctx->opcode); 5422 5423 switch (op2) { 5424 case OPC2_32_RCR_MADD_32: 5425 gen_maddi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5426 break; 5427 case OPC2_32_RCR_MADD_64: 5428 CHECK_REG_PAIR(r4); 5429 CHECK_REG_PAIR(r3); 5430 gen_maddi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5431 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5432 break; 5433 case OPC2_32_RCR_MADDS_32: 5434 gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5435 break; 5436 case OPC2_32_RCR_MADDS_64: 5437 CHECK_REG_PAIR(r4); 5438 CHECK_REG_PAIR(r3); 5439 gen_maddsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5440 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5441 break; 5442 case OPC2_32_RCR_MADD_U_64: 5443 CHECK_REG_PAIR(r4); 5444 CHECK_REG_PAIR(r3); 5445 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5446 gen_maddui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5447 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5448 break; 5449 case OPC2_32_RCR_MADDS_U_32: 5450 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5451 gen_maddsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5452 break; 5453 case OPC2_32_RCR_MADDS_U_64: 5454 CHECK_REG_PAIR(r4); 5455 CHECK_REG_PAIR(r3); 5456 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5457 gen_maddsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5458 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5459 break; 5460 default: 5461 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5462 } 5463 } 5464 5465 static void decode_rcr_msub(DisasContext *ctx) 5466 { 5467 uint32_t op2; 5468 int r1, r3, r4; 5469 int32_t const9; 5470 5471 5472 op2 = MASK_OP_RCR_OP2(ctx->opcode); 5473 r1 = MASK_OP_RCR_S1(ctx->opcode); 5474 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode); 5475 r3 = MASK_OP_RCR_S3(ctx->opcode); 5476 r4 = MASK_OP_RCR_D(ctx->opcode); 5477 5478 switch (op2) { 5479 case OPC2_32_RCR_MSUB_32: 5480 gen_msubi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5481 break; 5482 case OPC2_32_RCR_MSUB_64: 5483 CHECK_REG_PAIR(r4); 5484 CHECK_REG_PAIR(r3); 5485 gen_msubi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5486 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5487 break; 5488 case OPC2_32_RCR_MSUBS_32: 5489 gen_msubsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5490 break; 5491 case OPC2_32_RCR_MSUBS_64: 5492 CHECK_REG_PAIR(r4); 5493 CHECK_REG_PAIR(r3); 5494 gen_msubsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5495 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5496 break; 5497 case OPC2_32_RCR_MSUB_U_64: 5498 CHECK_REG_PAIR(r4); 5499 CHECK_REG_PAIR(r3); 5500 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5501 gen_msubui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5502 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5503 break; 5504 case OPC2_32_RCR_MSUBS_U_32: 5505 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5506 gen_msubsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5507 break; 5508 case OPC2_32_RCR_MSUBS_U_64: 5509 CHECK_REG_PAIR(r4); 5510 CHECK_REG_PAIR(r3); 5511 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5512 gen_msubsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5513 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5514 break; 5515 default: 5516 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5517 } 5518 } 5519 5520 /* RLC format */ 5521 5522 static void decode_rlc_opc(DisasContext *ctx, 5523 uint32_t op1) 5524 { 5525 int32_t const16; 5526 int r1, r2; 5527 5528 const16 = MASK_OP_RLC_CONST16_SEXT(ctx->opcode); 5529 r1 = MASK_OP_RLC_S1(ctx->opcode); 5530 r2 = MASK_OP_RLC_D(ctx->opcode); 5531 5532 switch (op1) { 5533 case OPC1_32_RLC_ADDI: 5534 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16); 5535 break; 5536 case OPC1_32_RLC_ADDIH: 5537 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16 << 16); 5538 break; 5539 case OPC1_32_RLC_ADDIH_A: 5540 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r1], const16 << 16); 5541 break; 5542 case OPC1_32_RLC_MFCR: 5543 const16 = MASK_OP_RLC_CONST16(ctx->opcode); 5544 gen_mfcr(ctx, cpu_gpr_d[r2], const16); 5545 break; 5546 case OPC1_32_RLC_MOV: 5547 tcg_gen_movi_tl(cpu_gpr_d[r2], const16); 5548 break; 5549 case OPC1_32_RLC_MOV_64: 5550 if (has_feature(ctx, TRICORE_FEATURE_16)) { 5551 CHECK_REG_PAIR(r2); 5552 tcg_gen_movi_tl(cpu_gpr_d[r2], const16); 5553 tcg_gen_movi_tl(cpu_gpr_d[r2+1], const16 >> 15); 5554 } else { 5555 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5556 } 5557 break; 5558 case OPC1_32_RLC_MOV_U: 5559 const16 = MASK_OP_RLC_CONST16(ctx->opcode); 5560 tcg_gen_movi_tl(cpu_gpr_d[r2], const16); 5561 break; 5562 case OPC1_32_RLC_MOV_H: 5563 tcg_gen_movi_tl(cpu_gpr_d[r2], const16 << 16); 5564 break; 5565 case OPC1_32_RLC_MOVH_A: 5566 tcg_gen_movi_tl(cpu_gpr_a[r2], const16 << 16); 5567 break; 5568 case OPC1_32_RLC_MTCR: 5569 const16 = MASK_OP_RLC_CONST16(ctx->opcode); 5570 gen_mtcr(ctx, cpu_gpr_d[r1], const16); 5571 break; 5572 default: 5573 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5574 } 5575 } 5576 5577 /* RR format */ 5578 static void decode_rr_accumulator(DisasContext *ctx) 5579 { 5580 uint32_t op2; 5581 int r3, r2, r1; 5582 5583 TCGv temp; 5584 5585 r3 = MASK_OP_RR_D(ctx->opcode); 5586 r2 = MASK_OP_RR_S2(ctx->opcode); 5587 r1 = MASK_OP_RR_S1(ctx->opcode); 5588 op2 = MASK_OP_RR_OP2(ctx->opcode); 5589 5590 switch (op2) { 5591 case OPC2_32_RR_ABS: 5592 gen_abs(cpu_gpr_d[r3], cpu_gpr_d[r2]); 5593 break; 5594 case OPC2_32_RR_ABS_B: 5595 gen_helper_abs_b(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r2]); 5596 break; 5597 case OPC2_32_RR_ABS_H: 5598 gen_helper_abs_h(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r2]); 5599 break; 5600 case OPC2_32_RR_ABSDIF: 5601 gen_absdif(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5602 break; 5603 case OPC2_32_RR_ABSDIF_B: 5604 gen_helper_absdif_b(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], 5605 cpu_gpr_d[r2]); 5606 break; 5607 case OPC2_32_RR_ABSDIF_H: 5608 gen_helper_absdif_h(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], 5609 cpu_gpr_d[r2]); 5610 break; 5611 case OPC2_32_RR_ABSDIFS: 5612 gen_helper_absdif_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], 5613 cpu_gpr_d[r2]); 5614 break; 5615 case OPC2_32_RR_ABSDIFS_H: 5616 gen_helper_absdif_h_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], 5617 cpu_gpr_d[r2]); 5618 break; 5619 case OPC2_32_RR_ABSS: 5620 gen_helper_abs_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r2]); 5621 break; 5622 case OPC2_32_RR_ABSS_H: 5623 gen_helper_abs_h_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r2]); 5624 break; 5625 case OPC2_32_RR_ADD: 5626 gen_add_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5627 break; 5628 case OPC2_32_RR_ADD_B: 5629 gen_helper_add_b(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 5630 break; 5631 case OPC2_32_RR_ADD_H: 5632 gen_helper_add_h(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 5633 break; 5634 case OPC2_32_RR_ADDC: 5635 gen_addc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5636 break; 5637 case OPC2_32_RR_ADDS: 5638 gen_adds(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5639 break; 5640 case OPC2_32_RR_ADDS_H: 5641 gen_helper_add_h_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], 5642 cpu_gpr_d[r2]); 5643 break; 5644 case OPC2_32_RR_ADDS_HU: 5645 gen_helper_add_h_suov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], 5646 cpu_gpr_d[r2]); 5647 break; 5648 case OPC2_32_RR_ADDS_U: 5649 gen_helper_add_suov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], 5650 cpu_gpr_d[r2]); 5651 break; 5652 case OPC2_32_RR_ADDX: 5653 gen_add_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5654 break; 5655 case OPC2_32_RR_AND_EQ: 5656 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 5657 cpu_gpr_d[r2], &tcg_gen_and_tl); 5658 break; 5659 case OPC2_32_RR_AND_GE: 5660 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5661 cpu_gpr_d[r2], &tcg_gen_and_tl); 5662 break; 5663 case OPC2_32_RR_AND_GE_U: 5664 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5665 cpu_gpr_d[r2], &tcg_gen_and_tl); 5666 break; 5667 case OPC2_32_RR_AND_LT: 5668 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5669 cpu_gpr_d[r2], &tcg_gen_and_tl); 5670 break; 5671 case OPC2_32_RR_AND_LT_U: 5672 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5673 cpu_gpr_d[r2], &tcg_gen_and_tl); 5674 break; 5675 case OPC2_32_RR_AND_NE: 5676 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5677 cpu_gpr_d[r2], &tcg_gen_and_tl); 5678 break; 5679 case OPC2_32_RR_EQ: 5680 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 5681 cpu_gpr_d[r2]); 5682 break; 5683 case OPC2_32_RR_EQ_B: 5684 gen_helper_eq_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5685 break; 5686 case OPC2_32_RR_EQ_H: 5687 gen_helper_eq_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5688 break; 5689 case OPC2_32_RR_EQ_W: 5690 tcg_gen_negsetcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], 5691 cpu_gpr_d[r1], cpu_gpr_d[r2]); 5692 break; 5693 case OPC2_32_RR_EQANY_B: 5694 gen_helper_eqany_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5695 break; 5696 case OPC2_32_RR_EQANY_H: 5697 gen_helper_eqany_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5698 break; 5699 case OPC2_32_RR_GE: 5700 tcg_gen_setcond_tl(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5701 cpu_gpr_d[r2]); 5702 break; 5703 case OPC2_32_RR_GE_U: 5704 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5705 cpu_gpr_d[r2]); 5706 break; 5707 case OPC2_32_RR_LT: 5708 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5709 cpu_gpr_d[r2]); 5710 break; 5711 case OPC2_32_RR_LT_U: 5712 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5713 cpu_gpr_d[r2]); 5714 break; 5715 case OPC2_32_RR_LT_B: 5716 gen_helper_lt_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5717 break; 5718 case OPC2_32_RR_LT_BU: 5719 gen_helper_lt_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5720 break; 5721 case OPC2_32_RR_LT_H: 5722 gen_helper_lt_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5723 break; 5724 case OPC2_32_RR_LT_HU: 5725 gen_helper_lt_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5726 break; 5727 case OPC2_32_RR_LT_W: 5728 tcg_gen_negsetcond_tl(TCG_COND_LT, cpu_gpr_d[r3], 5729 cpu_gpr_d[r1], cpu_gpr_d[r2]); 5730 break; 5731 case OPC2_32_RR_LT_WU: 5732 tcg_gen_negsetcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], 5733 cpu_gpr_d[r1], cpu_gpr_d[r2]); 5734 break; 5735 case OPC2_32_RR_MAX: 5736 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5737 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5738 break; 5739 case OPC2_32_RR_MAX_U: 5740 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5741 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5742 break; 5743 case OPC2_32_RR_MAX_B: 5744 gen_helper_max_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5745 break; 5746 case OPC2_32_RR_MAX_BU: 5747 gen_helper_max_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5748 break; 5749 case OPC2_32_RR_MAX_H: 5750 gen_helper_max_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5751 break; 5752 case OPC2_32_RR_MAX_HU: 5753 gen_helper_max_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5754 break; 5755 case OPC2_32_RR_MIN: 5756 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5757 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5758 break; 5759 case OPC2_32_RR_MIN_U: 5760 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5761 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5762 break; 5763 case OPC2_32_RR_MIN_B: 5764 gen_helper_min_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5765 break; 5766 case OPC2_32_RR_MIN_BU: 5767 gen_helper_min_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5768 break; 5769 case OPC2_32_RR_MIN_H: 5770 gen_helper_min_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5771 break; 5772 case OPC2_32_RR_MIN_HU: 5773 gen_helper_min_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5774 break; 5775 case OPC2_32_RR_MOV: 5776 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); 5777 break; 5778 case OPC2_32_RR_MOV_64: 5779 if (has_feature(ctx, TRICORE_FEATURE_16)) { 5780 temp = tcg_temp_new(); 5781 5782 CHECK_REG_PAIR(r3); 5783 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 5784 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); 5785 tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp); 5786 } else { 5787 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5788 } 5789 break; 5790 case OPC2_32_RR_MOVS_64: 5791 if (has_feature(ctx, TRICORE_FEATURE_16)) { 5792 CHECK_REG_PAIR(r3); 5793 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); 5794 tcg_gen_sari_tl(cpu_gpr_d[r3 + 1], cpu_gpr_d[r2], 31); 5795 } else { 5796 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5797 } 5798 break; 5799 case OPC2_32_RR_NE: 5800 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5801 cpu_gpr_d[r2]); 5802 break; 5803 case OPC2_32_RR_OR_EQ: 5804 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 5805 cpu_gpr_d[r2], &tcg_gen_or_tl); 5806 break; 5807 case OPC2_32_RR_OR_GE: 5808 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5809 cpu_gpr_d[r2], &tcg_gen_or_tl); 5810 break; 5811 case OPC2_32_RR_OR_GE_U: 5812 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5813 cpu_gpr_d[r2], &tcg_gen_or_tl); 5814 break; 5815 case OPC2_32_RR_OR_LT: 5816 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5817 cpu_gpr_d[r2], &tcg_gen_or_tl); 5818 break; 5819 case OPC2_32_RR_OR_LT_U: 5820 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5821 cpu_gpr_d[r2], &tcg_gen_or_tl); 5822 break; 5823 case OPC2_32_RR_OR_NE: 5824 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5825 cpu_gpr_d[r2], &tcg_gen_or_tl); 5826 break; 5827 case OPC2_32_RR_SAT_B: 5828 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7f, -0x80); 5829 break; 5830 case OPC2_32_RR_SAT_BU: 5831 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xff); 5832 break; 5833 case OPC2_32_RR_SAT_H: 5834 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7fff, -0x8000); 5835 break; 5836 case OPC2_32_RR_SAT_HU: 5837 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xffff); 5838 break; 5839 case OPC2_32_RR_SH_EQ: 5840 gen_sh_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 5841 cpu_gpr_d[r2]); 5842 break; 5843 case OPC2_32_RR_SH_GE: 5844 gen_sh_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5845 cpu_gpr_d[r2]); 5846 break; 5847 case OPC2_32_RR_SH_GE_U: 5848 gen_sh_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5849 cpu_gpr_d[r2]); 5850 break; 5851 case OPC2_32_RR_SH_LT: 5852 gen_sh_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5853 cpu_gpr_d[r2]); 5854 break; 5855 case OPC2_32_RR_SH_LT_U: 5856 gen_sh_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5857 cpu_gpr_d[r2]); 5858 break; 5859 case OPC2_32_RR_SH_NE: 5860 gen_sh_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5861 cpu_gpr_d[r2]); 5862 break; 5863 case OPC2_32_RR_SUB: 5864 gen_sub_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5865 break; 5866 case OPC2_32_RR_SUB_B: 5867 gen_helper_sub_b(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 5868 break; 5869 case OPC2_32_RR_SUB_H: 5870 gen_helper_sub_h(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 5871 break; 5872 case OPC2_32_RR_SUBC: 5873 gen_subc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5874 break; 5875 case OPC2_32_RR_SUBS: 5876 gen_subs(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5877 break; 5878 case OPC2_32_RR_SUBS_U: 5879 gen_subsu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5880 break; 5881 case OPC2_32_RR_SUBS_H: 5882 gen_helper_sub_h_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], 5883 cpu_gpr_d[r2]); 5884 break; 5885 case OPC2_32_RR_SUBS_HU: 5886 gen_helper_sub_h_suov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], 5887 cpu_gpr_d[r2]); 5888 break; 5889 case OPC2_32_RR_SUBX: 5890 gen_sub_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5891 break; 5892 case OPC2_32_RR_XOR_EQ: 5893 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 5894 cpu_gpr_d[r2], &tcg_gen_xor_tl); 5895 break; 5896 case OPC2_32_RR_XOR_GE: 5897 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5898 cpu_gpr_d[r2], &tcg_gen_xor_tl); 5899 break; 5900 case OPC2_32_RR_XOR_GE_U: 5901 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5902 cpu_gpr_d[r2], &tcg_gen_xor_tl); 5903 break; 5904 case OPC2_32_RR_XOR_LT: 5905 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5906 cpu_gpr_d[r2], &tcg_gen_xor_tl); 5907 break; 5908 case OPC2_32_RR_XOR_LT_U: 5909 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5910 cpu_gpr_d[r2], &tcg_gen_xor_tl); 5911 break; 5912 case OPC2_32_RR_XOR_NE: 5913 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5914 cpu_gpr_d[r2], &tcg_gen_xor_tl); 5915 break; 5916 default: 5917 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5918 } 5919 } 5920 5921 static void decode_rr_logical_shift(DisasContext *ctx) 5922 { 5923 uint32_t op2; 5924 int r3, r2, r1; 5925 5926 r3 = MASK_OP_RR_D(ctx->opcode); 5927 r2 = MASK_OP_RR_S2(ctx->opcode); 5928 r1 = MASK_OP_RR_S1(ctx->opcode); 5929 op2 = MASK_OP_RR_OP2(ctx->opcode); 5930 5931 switch (op2) { 5932 case OPC2_32_RR_AND: 5933 tcg_gen_and_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5934 break; 5935 case OPC2_32_RR_ANDN: 5936 tcg_gen_andc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5937 break; 5938 case OPC2_32_RR_CLO: 5939 tcg_gen_not_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 5940 tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], TARGET_LONG_BITS); 5941 break; 5942 case OPC2_32_RR_CLO_H: 5943 gen_helper_clo_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); 5944 break; 5945 case OPC2_32_RR_CLS: 5946 tcg_gen_clrsb_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 5947 break; 5948 case OPC2_32_RR_CLS_H: 5949 gen_helper_cls_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); 5950 break; 5951 case OPC2_32_RR_CLZ: 5952 tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], TARGET_LONG_BITS); 5953 break; 5954 case OPC2_32_RR_CLZ_H: 5955 gen_helper_clz_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); 5956 break; 5957 case OPC2_32_RR_NAND: 5958 tcg_gen_nand_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5959 break; 5960 case OPC2_32_RR_NOR: 5961 tcg_gen_nor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5962 break; 5963 case OPC2_32_RR_OR: 5964 tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5965 break; 5966 case OPC2_32_RR_ORN: 5967 tcg_gen_orc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5968 break; 5969 case OPC2_32_RR_SH: 5970 gen_helper_sh(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5971 break; 5972 case OPC2_32_RR_SH_H: 5973 gen_helper_sh_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5974 break; 5975 case OPC2_32_RR_SHA: 5976 gen_helper_sha(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 5977 break; 5978 case OPC2_32_RR_SHA_H: 5979 gen_helper_sha_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5980 break; 5981 case OPC2_32_RR_SHAS: 5982 gen_shas(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5983 break; 5984 case OPC2_32_RR_XNOR: 5985 tcg_gen_eqv_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5986 break; 5987 case OPC2_32_RR_XOR: 5988 tcg_gen_xor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5989 break; 5990 default: 5991 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5992 } 5993 } 5994 5995 static void decode_rr_address(DisasContext *ctx) 5996 { 5997 uint32_t op2, n; 5998 int r1, r2, r3; 5999 TCGv temp; 6000 6001 op2 = MASK_OP_RR_OP2(ctx->opcode); 6002 r3 = MASK_OP_RR_D(ctx->opcode); 6003 r2 = MASK_OP_RR_S2(ctx->opcode); 6004 r1 = MASK_OP_RR_S1(ctx->opcode); 6005 n = MASK_OP_RR_N(ctx->opcode); 6006 6007 switch (op2) { 6008 case OPC2_32_RR_ADD_A: 6009 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]); 6010 break; 6011 case OPC2_32_RR_ADDSC_A: 6012 temp = tcg_temp_new(); 6013 tcg_gen_shli_tl(temp, cpu_gpr_d[r1], n); 6014 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r2], temp); 6015 break; 6016 case OPC2_32_RR_ADDSC_AT: 6017 temp = tcg_temp_new(); 6018 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 3); 6019 tcg_gen_add_tl(temp, cpu_gpr_a[r2], temp); 6020 tcg_gen_andi_tl(cpu_gpr_a[r3], temp, 0xFFFFFFFC); 6021 break; 6022 case OPC2_32_RR_EQ_A: 6023 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], 6024 cpu_gpr_a[r2]); 6025 break; 6026 case OPC2_32_RR_EQZ: 6027 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], 0); 6028 break; 6029 case OPC2_32_RR_GE_A: 6030 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_a[r1], 6031 cpu_gpr_a[r2]); 6032 break; 6033 case OPC2_32_RR_LT_A: 6034 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_a[r1], 6035 cpu_gpr_a[r2]); 6036 break; 6037 case OPC2_32_RR_MOV_A: 6038 tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_d[r2]); 6039 break; 6040 case OPC2_32_RR_MOV_AA: 6041 tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_a[r2]); 6042 break; 6043 case OPC2_32_RR_MOV_D: 6044 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_a[r2]); 6045 break; 6046 case OPC2_32_RR_NE_A: 6047 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1], 6048 cpu_gpr_a[r2]); 6049 break; 6050 case OPC2_32_RR_NEZ_A: 6051 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1], 0); 6052 break; 6053 case OPC2_32_RR_SUB_A: 6054 tcg_gen_sub_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]); 6055 break; 6056 default: 6057 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6058 } 6059 } 6060 6061 static void decode_rr_idirect(DisasContext *ctx) 6062 { 6063 uint32_t op2; 6064 int r1; 6065 6066 op2 = MASK_OP_RR_OP2(ctx->opcode); 6067 r1 = MASK_OP_RR_S1(ctx->opcode); 6068 6069 switch (op2) { 6070 case OPC2_32_RR_JI: 6071 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); 6072 break; 6073 case OPC2_32_RR_JLI: 6074 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); 6075 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); 6076 break; 6077 case OPC2_32_RR_CALLI: 6078 gen_helper_1arg(call, ctx->pc_succ_insn); 6079 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); 6080 break; 6081 case OPC2_32_RR_FCALLI: 6082 gen_fcall_save_ctx(ctx); 6083 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); 6084 break; 6085 default: 6086 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6087 return; 6088 } 6089 ctx->base.is_jmp = DISAS_JUMP; 6090 } 6091 6092 static void decode_rr_divide(DisasContext *ctx) 6093 { 6094 uint32_t op2; 6095 int r1, r2, r3; 6096 6097 TCGv temp, temp2, temp3; 6098 6099 op2 = MASK_OP_RR_OP2(ctx->opcode); 6100 r3 = MASK_OP_RR_D(ctx->opcode); 6101 r2 = MASK_OP_RR_S2(ctx->opcode); 6102 r1 = MASK_OP_RR_S1(ctx->opcode); 6103 6104 switch (op2) { 6105 case OPC2_32_RR_BMERGE: 6106 gen_helper_bmerge(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6107 break; 6108 case OPC2_32_RR_BSPLIT: 6109 CHECK_REG_PAIR(r3); 6110 gen_bsplit(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]); 6111 break; 6112 case OPC2_32_RR_DVINIT_B: 6113 CHECK_REG_PAIR(r3); 6114 gen_dvinit_b(ctx, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6115 cpu_gpr_d[r2]); 6116 break; 6117 case OPC2_32_RR_DVINIT_BU: 6118 temp = tcg_temp_new(); 6119 temp2 = tcg_temp_new(); 6120 temp3 = tcg_temp_new(); 6121 CHECK_REG_PAIR(r3); 6122 tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 8); 6123 /* reset av */ 6124 tcg_gen_movi_tl(cpu_PSW_AV, 0); 6125 if (!has_feature(ctx, TRICORE_FEATURE_131)) { 6126 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */ 6127 tcg_gen_abs_tl(temp, temp3); 6128 tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]); 6129 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2); 6130 } else { 6131 /* overflow = (D[b] == 0) */ 6132 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0); 6133 } 6134 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 6135 /* sv */ 6136 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 6137 /* write result */ 6138 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 24); 6139 tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3); 6140 break; 6141 case OPC2_32_RR_DVINIT_H: 6142 CHECK_REG_PAIR(r3); 6143 gen_dvinit_h(ctx, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6144 cpu_gpr_d[r2]); 6145 break; 6146 case OPC2_32_RR_DVINIT_HU: 6147 temp = tcg_temp_new(); 6148 temp2 = tcg_temp_new(); 6149 temp3 = tcg_temp_new(); 6150 CHECK_REG_PAIR(r3); 6151 tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 16); 6152 /* reset av */ 6153 tcg_gen_movi_tl(cpu_PSW_AV, 0); 6154 if (!has_feature(ctx, TRICORE_FEATURE_131)) { 6155 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */ 6156 tcg_gen_abs_tl(temp, temp3); 6157 tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]); 6158 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2); 6159 } else { 6160 /* overflow = (D[b] == 0) */ 6161 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0); 6162 } 6163 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 6164 /* sv */ 6165 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 6166 /* write result */ 6167 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 16); 6168 tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3); 6169 break; 6170 case OPC2_32_RR_DVINIT: 6171 temp = tcg_temp_new(); 6172 temp2 = tcg_temp_new(); 6173 CHECK_REG_PAIR(r3); 6174 /* overflow = ((D[b] == 0) || 6175 ((D[b] == 0xFFFFFFFF) && (D[a] == 0x80000000))) */ 6176 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, cpu_gpr_d[r2], 0xffffffff); 6177 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r1], 0x80000000); 6178 tcg_gen_and_tl(temp, temp, temp2); 6179 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r2], 0); 6180 tcg_gen_or_tl(cpu_PSW_V, temp, temp2); 6181 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 6182 /* sv */ 6183 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 6184 /* reset av */ 6185 tcg_gen_movi_tl(cpu_PSW_AV, 0); 6186 /* write result */ 6187 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6188 /* sign extend to high reg */ 6189 tcg_gen_sari_tl(cpu_gpr_d[r3+1], cpu_gpr_d[r1], 31); 6190 break; 6191 case OPC2_32_RR_DVINIT_U: 6192 CHECK_REG_PAIR(r3); 6193 /* overflow = (D[b] == 0) */ 6194 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0); 6195 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 6196 /* sv */ 6197 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 6198 /* reset av */ 6199 tcg_gen_movi_tl(cpu_PSW_AV, 0); 6200 /* write result */ 6201 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6202 /* zero extend to high reg*/ 6203 tcg_gen_movi_tl(cpu_gpr_d[r3+1], 0); 6204 break; 6205 case OPC2_32_RR_PARITY: 6206 gen_helper_parity(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6207 break; 6208 case OPC2_32_RR_UNPACK: 6209 CHECK_REG_PAIR(r3); 6210 gen_unpack(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]); 6211 break; 6212 case OPC2_32_RR_CRC32_B: 6213 if (has_feature(ctx, TRICORE_FEATURE_162)) { 6214 gen_helper_crc32b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6215 } else { 6216 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6217 } 6218 break; 6219 case OPC2_32_RR_CRC32: /* CRC32B.W in 1.6.2 */ 6220 if (has_feature(ctx, TRICORE_FEATURE_161)) { 6221 gen_helper_crc32_be(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6222 } else { 6223 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6224 } 6225 break; 6226 case OPC2_32_RR_CRC32L_W: 6227 if (has_feature(ctx, TRICORE_FEATURE_162)) { 6228 gen_helper_crc32_le(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6229 } else { 6230 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6231 } 6232 break; 6233 6234 case OPC2_32_RR_POPCNT_W: 6235 if (has_feature(ctx, TRICORE_FEATURE_162)) { 6236 tcg_gen_ctpop_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6237 } else { 6238 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6239 } 6240 break; 6241 case OPC2_32_RR_DIV: 6242 if (has_feature(ctx, TRICORE_FEATURE_16)) { 6243 CHECK_REG_PAIR(r3); 6244 GEN_HELPER_RR(divide, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6245 cpu_gpr_d[r2]); 6246 } else { 6247 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6248 } 6249 break; 6250 case OPC2_32_RR_DIV_U: 6251 if (has_feature(ctx, TRICORE_FEATURE_16)) { 6252 CHECK_REG_PAIR(r3); 6253 GEN_HELPER_RR(divide_u, cpu_gpr_d[r3], cpu_gpr_d[r3+1], 6254 cpu_gpr_d[r1], cpu_gpr_d[r2]); 6255 } else { 6256 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6257 } 6258 break; 6259 case OPC2_32_RR_MUL_F: 6260 gen_helper_fmul(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6261 break; 6262 case OPC2_32_RR_DIV_F: 6263 gen_helper_fdiv(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6264 break; 6265 case OPC2_32_RR_FTOHP: 6266 if (has_feature(ctx, TRICORE_FEATURE_162)) { 6267 gen_helper_ftohp(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); 6268 } else { 6269 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6270 } 6271 break; 6272 case OPC2_32_RR_HPTOF: 6273 if (has_feature(ctx, TRICORE_FEATURE_162)) { 6274 gen_helper_hptof(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); 6275 } else { 6276 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6277 } 6278 break; 6279 case OPC2_32_RR_CMP_F: 6280 gen_helper_fcmp(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6281 break; 6282 case OPC2_32_RR_FTOI: 6283 gen_helper_ftoi(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); 6284 break; 6285 case OPC2_32_RR_ITOF: 6286 gen_helper_itof(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); 6287 break; 6288 case OPC2_32_RR_FTOU: 6289 gen_helper_ftou(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); 6290 break; 6291 case OPC2_32_RR_FTOUZ: 6292 if (has_feature(ctx, TRICORE_FEATURE_131)) { 6293 gen_helper_ftouz(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); 6294 } else { 6295 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6296 } 6297 break; 6298 case OPC2_32_RR_UPDFL: 6299 gen_helper_updfl(tcg_env, cpu_gpr_d[r1]); 6300 break; 6301 case OPC2_32_RR_UTOF: 6302 gen_helper_utof(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); 6303 break; 6304 case OPC2_32_RR_FTOIZ: 6305 gen_helper_ftoiz(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); 6306 break; 6307 case OPC2_32_RR_QSEED_F: 6308 gen_helper_qseed(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); 6309 break; 6310 default: 6311 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6312 } 6313 } 6314 6315 /* RR1 Format */ 6316 static void decode_rr1_mul(DisasContext *ctx) 6317 { 6318 uint32_t op2; 6319 6320 int r1, r2, r3; 6321 TCGv n; 6322 TCGv_i64 temp64; 6323 6324 r1 = MASK_OP_RR1_S1(ctx->opcode); 6325 r2 = MASK_OP_RR1_S2(ctx->opcode); 6326 r3 = MASK_OP_RR1_D(ctx->opcode); 6327 n = tcg_constant_i32(MASK_OP_RR1_N(ctx->opcode)); 6328 op2 = MASK_OP_RR1_OP2(ctx->opcode); 6329 6330 switch (op2) { 6331 case OPC2_32_RR1_MUL_H_32_LL: 6332 temp64 = tcg_temp_new_i64(); 6333 CHECK_REG_PAIR(r3); 6334 GEN_HELPER_LL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6335 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6336 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); 6337 break; 6338 case OPC2_32_RR1_MUL_H_32_LU: 6339 temp64 = tcg_temp_new_i64(); 6340 CHECK_REG_PAIR(r3); 6341 GEN_HELPER_LU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6342 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6343 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); 6344 break; 6345 case OPC2_32_RR1_MUL_H_32_UL: 6346 temp64 = tcg_temp_new_i64(); 6347 CHECK_REG_PAIR(r3); 6348 GEN_HELPER_UL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6349 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6350 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); 6351 break; 6352 case OPC2_32_RR1_MUL_H_32_UU: 6353 temp64 = tcg_temp_new_i64(); 6354 CHECK_REG_PAIR(r3); 6355 GEN_HELPER_UU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6356 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6357 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); 6358 break; 6359 case OPC2_32_RR1_MULM_H_64_LL: 6360 temp64 = tcg_temp_new_i64(); 6361 CHECK_REG_PAIR(r3); 6362 GEN_HELPER_LL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6363 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6364 /* reset V bit */ 6365 tcg_gen_movi_tl(cpu_PSW_V, 0); 6366 /* reset AV bit */ 6367 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 6368 break; 6369 case OPC2_32_RR1_MULM_H_64_LU: 6370 temp64 = tcg_temp_new_i64(); 6371 CHECK_REG_PAIR(r3); 6372 GEN_HELPER_LU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6373 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6374 /* reset V bit */ 6375 tcg_gen_movi_tl(cpu_PSW_V, 0); 6376 /* reset AV bit */ 6377 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 6378 break; 6379 case OPC2_32_RR1_MULM_H_64_UL: 6380 temp64 = tcg_temp_new_i64(); 6381 CHECK_REG_PAIR(r3); 6382 GEN_HELPER_UL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6383 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6384 /* reset V bit */ 6385 tcg_gen_movi_tl(cpu_PSW_V, 0); 6386 /* reset AV bit */ 6387 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 6388 break; 6389 case OPC2_32_RR1_MULM_H_64_UU: 6390 temp64 = tcg_temp_new_i64(); 6391 CHECK_REG_PAIR(r3); 6392 GEN_HELPER_UU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6393 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6394 /* reset V bit */ 6395 tcg_gen_movi_tl(cpu_PSW_V, 0); 6396 /* reset AV bit */ 6397 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 6398 break; 6399 case OPC2_32_RR1_MULR_H_16_LL: 6400 GEN_HELPER_LL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6401 gen_calc_usb_mulr_h(cpu_gpr_d[r3]); 6402 break; 6403 case OPC2_32_RR1_MULR_H_16_LU: 6404 GEN_HELPER_LU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6405 gen_calc_usb_mulr_h(cpu_gpr_d[r3]); 6406 break; 6407 case OPC2_32_RR1_MULR_H_16_UL: 6408 GEN_HELPER_UL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6409 gen_calc_usb_mulr_h(cpu_gpr_d[r3]); 6410 break; 6411 case OPC2_32_RR1_MULR_H_16_UU: 6412 GEN_HELPER_UU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6413 gen_calc_usb_mulr_h(cpu_gpr_d[r3]); 6414 break; 6415 default: 6416 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6417 } 6418 } 6419 6420 static void decode_rr1_mulq(DisasContext *ctx) 6421 { 6422 uint32_t op2; 6423 int r1, r2, r3; 6424 uint32_t n; 6425 6426 TCGv temp, temp2; 6427 6428 r1 = MASK_OP_RR1_S1(ctx->opcode); 6429 r2 = MASK_OP_RR1_S2(ctx->opcode); 6430 r3 = MASK_OP_RR1_D(ctx->opcode); 6431 n = MASK_OP_RR1_N(ctx->opcode); 6432 op2 = MASK_OP_RR1_OP2(ctx->opcode); 6433 6434 temp = tcg_temp_new(); 6435 temp2 = tcg_temp_new(); 6436 6437 switch (op2) { 6438 case OPC2_32_RR1_MUL_Q_32: 6439 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], cpu_gpr_d[r2], n, 32); 6440 break; 6441 case OPC2_32_RR1_MUL_Q_64: 6442 CHECK_REG_PAIR(r3); 6443 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 6444 n, 0); 6445 break; 6446 case OPC2_32_RR1_MUL_Q_32_L: 6447 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 6448 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16); 6449 break; 6450 case OPC2_32_RR1_MUL_Q_64_L: 6451 CHECK_REG_PAIR(r3); 6452 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 6453 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0); 6454 break; 6455 case OPC2_32_RR1_MUL_Q_32_U: 6456 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 6457 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16); 6458 break; 6459 case OPC2_32_RR1_MUL_Q_64_U: 6460 CHECK_REG_PAIR(r3); 6461 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 6462 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0); 6463 break; 6464 case OPC2_32_RR1_MUL_Q_32_LL: 6465 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 6466 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 6467 gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n); 6468 break; 6469 case OPC2_32_RR1_MUL_Q_32_UU: 6470 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 6471 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 6472 gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n); 6473 break; 6474 case OPC2_32_RR1_MULR_Q_32_L: 6475 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 6476 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 6477 gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n); 6478 break; 6479 case OPC2_32_RR1_MULR_Q_32_U: 6480 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 6481 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 6482 gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n); 6483 break; 6484 default: 6485 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6486 } 6487 } 6488 6489 /* RR2 format */ 6490 static void decode_rr2_mul(DisasContext *ctx) 6491 { 6492 uint32_t op2; 6493 int r1, r2, r3; 6494 6495 op2 = MASK_OP_RR2_OP2(ctx->opcode); 6496 r1 = MASK_OP_RR2_S1(ctx->opcode); 6497 r2 = MASK_OP_RR2_S2(ctx->opcode); 6498 r3 = MASK_OP_RR2_D(ctx->opcode); 6499 switch (op2) { 6500 case OPC2_32_RR2_MUL_32: 6501 gen_mul_i32s(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6502 break; 6503 case OPC2_32_RR2_MUL_64: 6504 CHECK_REG_PAIR(r3); 6505 gen_mul_i64s(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6506 cpu_gpr_d[r2]); 6507 break; 6508 case OPC2_32_RR2_MULS_32: 6509 gen_helper_mul_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], 6510 cpu_gpr_d[r2]); 6511 break; 6512 case OPC2_32_RR2_MUL_U_64: 6513 CHECK_REG_PAIR(r3); 6514 gen_mul_i64u(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6515 cpu_gpr_d[r2]); 6516 break; 6517 case OPC2_32_RR2_MULS_U_32: 6518 gen_helper_mul_suov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], 6519 cpu_gpr_d[r2]); 6520 break; 6521 default: 6522 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6523 } 6524 } 6525 6526 /* RRPW format */ 6527 static void decode_rrpw_extract_insert(DisasContext *ctx) 6528 { 6529 uint32_t op2; 6530 int r1, r2, r3; 6531 int32_t pos, width; 6532 TCGv temp; 6533 6534 op2 = MASK_OP_RRPW_OP2(ctx->opcode); 6535 r1 = MASK_OP_RRPW_S1(ctx->opcode); 6536 r2 = MASK_OP_RRPW_S2(ctx->opcode); 6537 r3 = MASK_OP_RRPW_D(ctx->opcode); 6538 pos = MASK_OP_RRPW_POS(ctx->opcode); 6539 width = MASK_OP_RRPW_WIDTH(ctx->opcode); 6540 6541 switch (op2) { 6542 case OPC2_32_RRPW_EXTR: 6543 if (width == 0) { 6544 tcg_gen_movi_tl(cpu_gpr_d[r3], 0); 6545 } else if (pos + width <= 32) { 6546 tcg_gen_sextract_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], pos, width); 6547 } 6548 break; 6549 case OPC2_32_RRPW_EXTR_U: 6550 if (width == 0) { 6551 tcg_gen_movi_tl(cpu_gpr_d[r3], 0); 6552 } else { 6553 tcg_gen_extract_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], pos, width); 6554 } 6555 break; 6556 case OPC2_32_RRPW_IMASK: 6557 CHECK_REG_PAIR(r3); 6558 6559 if (pos + width <= 32) { 6560 temp = tcg_temp_new(); 6561 tcg_gen_movi_tl(temp, ((1u << width) - 1) << pos); 6562 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], pos); 6563 tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp); 6564 } 6565 6566 break; 6567 case OPC2_32_RRPW_INSERT: 6568 /* tcg_gen_deposit_tl() does not handle the case of width = 0 */ 6569 if (width == 0) { 6570 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6571 } else if (pos + width <= 32) { 6572 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 6573 pos, width); 6574 } 6575 break; 6576 default: 6577 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6578 } 6579 } 6580 6581 /* RRR format */ 6582 static void decode_rrr_cond_select(DisasContext *ctx) 6583 { 6584 uint32_t op2; 6585 int r1, r2, r3, r4; 6586 TCGv temp; 6587 6588 op2 = MASK_OP_RRR_OP2(ctx->opcode); 6589 r1 = MASK_OP_RRR_S1(ctx->opcode); 6590 r2 = MASK_OP_RRR_S2(ctx->opcode); 6591 r3 = MASK_OP_RRR_S3(ctx->opcode); 6592 r4 = MASK_OP_RRR_D(ctx->opcode); 6593 6594 switch (op2) { 6595 case OPC2_32_RRR_CADD: 6596 gen_cond_add(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], 6597 cpu_gpr_d[r4], cpu_gpr_d[r3]); 6598 break; 6599 case OPC2_32_RRR_CADDN: 6600 gen_cond_add(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4], 6601 cpu_gpr_d[r3]); 6602 break; 6603 case OPC2_32_RRR_CSUB: 6604 gen_cond_sub(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4], 6605 cpu_gpr_d[r3]); 6606 break; 6607 case OPC2_32_RRR_CSUBN: 6608 gen_cond_sub(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4], 6609 cpu_gpr_d[r3]); 6610 break; 6611 case OPC2_32_RRR_SEL: 6612 temp = tcg_constant_i32(0); 6613 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, 6614 cpu_gpr_d[r1], cpu_gpr_d[r2]); 6615 break; 6616 case OPC2_32_RRR_SELN: 6617 temp = tcg_constant_i32(0); 6618 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, 6619 cpu_gpr_d[r1], cpu_gpr_d[r2]); 6620 break; 6621 default: 6622 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6623 } 6624 } 6625 6626 static void decode_rrr_divide(DisasContext *ctx) 6627 { 6628 uint32_t op2; 6629 6630 int r1, r2, r3, r4; 6631 6632 op2 = MASK_OP_RRR_OP2(ctx->opcode); 6633 r1 = MASK_OP_RRR_S1(ctx->opcode); 6634 r2 = MASK_OP_RRR_S2(ctx->opcode); 6635 r3 = MASK_OP_RRR_S3(ctx->opcode); 6636 r4 = MASK_OP_RRR_D(ctx->opcode); 6637 6638 switch (op2) { 6639 case OPC2_32_RRR_DVADJ: 6640 CHECK_REG_PAIR(r3); 6641 CHECK_REG_PAIR(r4); 6642 GEN_HELPER_RRR(dvadj, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6643 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6644 break; 6645 case OPC2_32_RRR_DVSTEP: 6646 CHECK_REG_PAIR(r3); 6647 CHECK_REG_PAIR(r4); 6648 GEN_HELPER_RRR(dvstep, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6649 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6650 break; 6651 case OPC2_32_RRR_DVSTEP_U: 6652 CHECK_REG_PAIR(r3); 6653 CHECK_REG_PAIR(r4); 6654 GEN_HELPER_RRR(dvstep_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6655 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6656 break; 6657 case OPC2_32_RRR_IXMAX: 6658 CHECK_REG_PAIR(r3); 6659 CHECK_REG_PAIR(r4); 6660 GEN_HELPER_RRR(ixmax, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6661 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6662 break; 6663 case OPC2_32_RRR_IXMAX_U: 6664 CHECK_REG_PAIR(r3); 6665 CHECK_REG_PAIR(r4); 6666 GEN_HELPER_RRR(ixmax_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6667 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6668 break; 6669 case OPC2_32_RRR_IXMIN: 6670 CHECK_REG_PAIR(r3); 6671 CHECK_REG_PAIR(r4); 6672 GEN_HELPER_RRR(ixmin, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6673 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6674 break; 6675 case OPC2_32_RRR_IXMIN_U: 6676 CHECK_REG_PAIR(r3); 6677 CHECK_REG_PAIR(r4); 6678 GEN_HELPER_RRR(ixmin_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6679 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6680 break; 6681 case OPC2_32_RRR_PACK: 6682 CHECK_REG_PAIR(r3); 6683 gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3], 6684 cpu_gpr_d[r3+1], cpu_gpr_d[r1]); 6685 break; 6686 case OPC2_32_RRR_CRCN: 6687 if (has_feature(ctx, TRICORE_FEATURE_162)) { 6688 gen_helper_crcn(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], 6689 cpu_gpr_d[r3]); 6690 } else { 6691 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6692 } 6693 break; 6694 case OPC2_32_RRR_ADD_F: 6695 gen_helper_fadd(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r3]); 6696 break; 6697 case OPC2_32_RRR_SUB_F: 6698 gen_helper_fsub(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r3]); 6699 break; 6700 case OPC2_32_RRR_MADD_F: 6701 gen_helper_fmadd(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], 6702 cpu_gpr_d[r2], cpu_gpr_d[r3]); 6703 break; 6704 case OPC2_32_RRR_MSUB_F: 6705 gen_helper_fmsub(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], 6706 cpu_gpr_d[r2], cpu_gpr_d[r3]); 6707 break; 6708 default: 6709 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6710 } 6711 } 6712 6713 /* RRR2 format */ 6714 static void decode_rrr2_madd(DisasContext *ctx) 6715 { 6716 uint32_t op2; 6717 uint32_t r1, r2, r3, r4; 6718 6719 op2 = MASK_OP_RRR2_OP2(ctx->opcode); 6720 r1 = MASK_OP_RRR2_S1(ctx->opcode); 6721 r2 = MASK_OP_RRR2_S2(ctx->opcode); 6722 r3 = MASK_OP_RRR2_S3(ctx->opcode); 6723 r4 = MASK_OP_RRR2_D(ctx->opcode); 6724 switch (op2) { 6725 case OPC2_32_RRR2_MADD_32: 6726 gen_madd32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], 6727 cpu_gpr_d[r2]); 6728 break; 6729 case OPC2_32_RRR2_MADD_64: 6730 CHECK_REG_PAIR(r4); 6731 CHECK_REG_PAIR(r3); 6732 gen_madd64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6733 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6734 break; 6735 case OPC2_32_RRR2_MADDS_32: 6736 gen_helper_madd32_ssov(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], 6737 cpu_gpr_d[r3], cpu_gpr_d[r2]); 6738 break; 6739 case OPC2_32_RRR2_MADDS_64: 6740 CHECK_REG_PAIR(r4); 6741 CHECK_REG_PAIR(r3); 6742 gen_madds_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6743 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6744 break; 6745 case OPC2_32_RRR2_MADD_U_64: 6746 CHECK_REG_PAIR(r4); 6747 CHECK_REG_PAIR(r3); 6748 gen_maddu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6749 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6750 break; 6751 case OPC2_32_RRR2_MADDS_U_32: 6752 gen_helper_madd32_suov(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], 6753 cpu_gpr_d[r3], cpu_gpr_d[r2]); 6754 break; 6755 case OPC2_32_RRR2_MADDS_U_64: 6756 CHECK_REG_PAIR(r4); 6757 CHECK_REG_PAIR(r3); 6758 gen_maddsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6759 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6760 break; 6761 default: 6762 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6763 } 6764 } 6765 6766 static void decode_rrr2_msub(DisasContext *ctx) 6767 { 6768 uint32_t op2; 6769 uint32_t r1, r2, r3, r4; 6770 6771 op2 = MASK_OP_RRR2_OP2(ctx->opcode); 6772 r1 = MASK_OP_RRR2_S1(ctx->opcode); 6773 r2 = MASK_OP_RRR2_S2(ctx->opcode); 6774 r3 = MASK_OP_RRR2_S3(ctx->opcode); 6775 r4 = MASK_OP_RRR2_D(ctx->opcode); 6776 6777 switch (op2) { 6778 case OPC2_32_RRR2_MSUB_32: 6779 gen_msub32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], 6780 cpu_gpr_d[r2]); 6781 break; 6782 case OPC2_32_RRR2_MSUB_64: 6783 CHECK_REG_PAIR(r4); 6784 CHECK_REG_PAIR(r3); 6785 gen_msub64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6786 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6787 break; 6788 case OPC2_32_RRR2_MSUBS_32: 6789 gen_helper_msub32_ssov(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], 6790 cpu_gpr_d[r3], cpu_gpr_d[r2]); 6791 break; 6792 case OPC2_32_RRR2_MSUBS_64: 6793 CHECK_REG_PAIR(r4); 6794 CHECK_REG_PAIR(r3); 6795 gen_msubs_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6796 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6797 break; 6798 case OPC2_32_RRR2_MSUB_U_64: 6799 CHECK_REG_PAIR(r4); 6800 CHECK_REG_PAIR(r3); 6801 gen_msubu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6802 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6803 break; 6804 case OPC2_32_RRR2_MSUBS_U_32: 6805 gen_helper_msub32_suov(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], 6806 cpu_gpr_d[r3], cpu_gpr_d[r2]); 6807 break; 6808 case OPC2_32_RRR2_MSUBS_U_64: 6809 CHECK_REG_PAIR(r4); 6810 CHECK_REG_PAIR(r3); 6811 gen_msubsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6812 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6813 break; 6814 default: 6815 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6816 } 6817 } 6818 6819 /* RRR1 format */ 6820 static void decode_rrr1_madd(DisasContext *ctx) 6821 { 6822 uint32_t op2; 6823 uint32_t r1, r2, r3, r4, n; 6824 6825 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 6826 r1 = MASK_OP_RRR1_S1(ctx->opcode); 6827 r2 = MASK_OP_RRR1_S2(ctx->opcode); 6828 r3 = MASK_OP_RRR1_S3(ctx->opcode); 6829 r4 = MASK_OP_RRR1_D(ctx->opcode); 6830 n = MASK_OP_RRR1_N(ctx->opcode); 6831 6832 switch (op2) { 6833 case OPC2_32_RRR1_MADD_H_LL: 6834 CHECK_REG_PAIR(r4); 6835 CHECK_REG_PAIR(r3); 6836 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6837 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 6838 break; 6839 case OPC2_32_RRR1_MADD_H_LU: 6840 CHECK_REG_PAIR(r4); 6841 CHECK_REG_PAIR(r3); 6842 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6843 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 6844 break; 6845 case OPC2_32_RRR1_MADD_H_UL: 6846 CHECK_REG_PAIR(r4); 6847 CHECK_REG_PAIR(r3); 6848 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6849 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 6850 break; 6851 case OPC2_32_RRR1_MADD_H_UU: 6852 CHECK_REG_PAIR(r4); 6853 CHECK_REG_PAIR(r3); 6854 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6855 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 6856 break; 6857 case OPC2_32_RRR1_MADDS_H_LL: 6858 CHECK_REG_PAIR(r4); 6859 CHECK_REG_PAIR(r3); 6860 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6861 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 6862 break; 6863 case OPC2_32_RRR1_MADDS_H_LU: 6864 CHECK_REG_PAIR(r4); 6865 CHECK_REG_PAIR(r3); 6866 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6867 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 6868 break; 6869 case OPC2_32_RRR1_MADDS_H_UL: 6870 CHECK_REG_PAIR(r4); 6871 CHECK_REG_PAIR(r3); 6872 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6873 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 6874 break; 6875 case OPC2_32_RRR1_MADDS_H_UU: 6876 CHECK_REG_PAIR(r4); 6877 CHECK_REG_PAIR(r3); 6878 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6879 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 6880 break; 6881 case OPC2_32_RRR1_MADDM_H_LL: 6882 CHECK_REG_PAIR(r4); 6883 CHECK_REG_PAIR(r3); 6884 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6885 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 6886 break; 6887 case OPC2_32_RRR1_MADDM_H_LU: 6888 CHECK_REG_PAIR(r4); 6889 CHECK_REG_PAIR(r3); 6890 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6891 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 6892 break; 6893 case OPC2_32_RRR1_MADDM_H_UL: 6894 CHECK_REG_PAIR(r4); 6895 CHECK_REG_PAIR(r3); 6896 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6897 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 6898 break; 6899 case OPC2_32_RRR1_MADDM_H_UU: 6900 CHECK_REG_PAIR(r4); 6901 CHECK_REG_PAIR(r3); 6902 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6903 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 6904 break; 6905 case OPC2_32_RRR1_MADDMS_H_LL: 6906 CHECK_REG_PAIR(r4); 6907 CHECK_REG_PAIR(r3); 6908 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6909 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 6910 break; 6911 case OPC2_32_RRR1_MADDMS_H_LU: 6912 CHECK_REG_PAIR(r4); 6913 CHECK_REG_PAIR(r3); 6914 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6915 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 6916 break; 6917 case OPC2_32_RRR1_MADDMS_H_UL: 6918 CHECK_REG_PAIR(r4); 6919 CHECK_REG_PAIR(r3); 6920 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6921 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 6922 break; 6923 case OPC2_32_RRR1_MADDMS_H_UU: 6924 CHECK_REG_PAIR(r4); 6925 CHECK_REG_PAIR(r3); 6926 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6927 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 6928 break; 6929 case OPC2_32_RRR1_MADDR_H_LL: 6930 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6931 cpu_gpr_d[r2], n, MODE_LL); 6932 break; 6933 case OPC2_32_RRR1_MADDR_H_LU: 6934 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6935 cpu_gpr_d[r2], n, MODE_LU); 6936 break; 6937 case OPC2_32_RRR1_MADDR_H_UL: 6938 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6939 cpu_gpr_d[r2], n, MODE_UL); 6940 break; 6941 case OPC2_32_RRR1_MADDR_H_UU: 6942 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6943 cpu_gpr_d[r2], n, MODE_UU); 6944 break; 6945 case OPC2_32_RRR1_MADDRS_H_LL: 6946 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6947 cpu_gpr_d[r2], n, MODE_LL); 6948 break; 6949 case OPC2_32_RRR1_MADDRS_H_LU: 6950 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6951 cpu_gpr_d[r2], n, MODE_LU); 6952 break; 6953 case OPC2_32_RRR1_MADDRS_H_UL: 6954 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6955 cpu_gpr_d[r2], n, MODE_UL); 6956 break; 6957 case OPC2_32_RRR1_MADDRS_H_UU: 6958 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6959 cpu_gpr_d[r2], n, MODE_UU); 6960 break; 6961 default: 6962 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6963 } 6964 } 6965 6966 static void decode_rrr1_maddq_h(DisasContext *ctx) 6967 { 6968 uint32_t op2; 6969 uint32_t r1, r2, r3, r4, n; 6970 TCGv temp, temp2; 6971 6972 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 6973 r1 = MASK_OP_RRR1_S1(ctx->opcode); 6974 r2 = MASK_OP_RRR1_S2(ctx->opcode); 6975 r3 = MASK_OP_RRR1_S3(ctx->opcode); 6976 r4 = MASK_OP_RRR1_D(ctx->opcode); 6977 n = MASK_OP_RRR1_N(ctx->opcode); 6978 6979 temp = tcg_temp_new(); 6980 temp2 = tcg_temp_new(); 6981 6982 switch (op2) { 6983 case OPC2_32_RRR1_MADD_Q_32: 6984 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6985 cpu_gpr_d[r2], n, 32); 6986 break; 6987 case OPC2_32_RRR1_MADD_Q_64: 6988 CHECK_REG_PAIR(r4); 6989 CHECK_REG_PAIR(r3); 6990 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6991 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 6992 n); 6993 break; 6994 case OPC2_32_RRR1_MADD_Q_32_L: 6995 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 6996 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6997 temp, n, 16); 6998 break; 6999 case OPC2_32_RRR1_MADD_Q_64_L: 7000 CHECK_REG_PAIR(r4); 7001 CHECK_REG_PAIR(r3); 7002 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7003 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7004 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7005 n); 7006 break; 7007 case OPC2_32_RRR1_MADD_Q_32_U: 7008 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7009 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7010 temp, n, 16); 7011 break; 7012 case OPC2_32_RRR1_MADD_Q_64_U: 7013 CHECK_REG_PAIR(r4); 7014 CHECK_REG_PAIR(r3); 7015 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7016 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7017 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7018 n); 7019 break; 7020 case OPC2_32_RRR1_MADD_Q_32_LL: 7021 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7022 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7023 gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7024 break; 7025 case OPC2_32_RRR1_MADD_Q_64_LL: 7026 CHECK_REG_PAIR(r4); 7027 CHECK_REG_PAIR(r3); 7028 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7029 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7030 gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7031 cpu_gpr_d[r3+1], temp, temp2, n); 7032 break; 7033 case OPC2_32_RRR1_MADD_Q_32_UU: 7034 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7035 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7036 gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7037 break; 7038 case OPC2_32_RRR1_MADD_Q_64_UU: 7039 CHECK_REG_PAIR(r4); 7040 CHECK_REG_PAIR(r3); 7041 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7042 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7043 gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7044 cpu_gpr_d[r3+1], temp, temp2, n); 7045 break; 7046 case OPC2_32_RRR1_MADDS_Q_32: 7047 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7048 cpu_gpr_d[r2], n, 32); 7049 break; 7050 case OPC2_32_RRR1_MADDS_Q_64: 7051 CHECK_REG_PAIR(r4); 7052 CHECK_REG_PAIR(r3); 7053 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7054 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7055 n); 7056 break; 7057 case OPC2_32_RRR1_MADDS_Q_32_L: 7058 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7059 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7060 temp, n, 16); 7061 break; 7062 case OPC2_32_RRR1_MADDS_Q_64_L: 7063 CHECK_REG_PAIR(r4); 7064 CHECK_REG_PAIR(r3); 7065 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7066 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7067 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7068 n); 7069 break; 7070 case OPC2_32_RRR1_MADDS_Q_32_U: 7071 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7072 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7073 temp, n, 16); 7074 break; 7075 case OPC2_32_RRR1_MADDS_Q_64_U: 7076 CHECK_REG_PAIR(r4); 7077 CHECK_REG_PAIR(r3); 7078 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7079 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7080 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7081 n); 7082 break; 7083 case OPC2_32_RRR1_MADDS_Q_32_LL: 7084 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7085 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7086 gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7087 break; 7088 case OPC2_32_RRR1_MADDS_Q_64_LL: 7089 CHECK_REG_PAIR(r4); 7090 CHECK_REG_PAIR(r3); 7091 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7092 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7093 gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7094 cpu_gpr_d[r3+1], temp, temp2, n); 7095 break; 7096 case OPC2_32_RRR1_MADDS_Q_32_UU: 7097 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7098 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7099 gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7100 break; 7101 case OPC2_32_RRR1_MADDS_Q_64_UU: 7102 CHECK_REG_PAIR(r4); 7103 CHECK_REG_PAIR(r3); 7104 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7105 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7106 gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7107 cpu_gpr_d[r3+1], temp, temp2, n); 7108 break; 7109 case OPC2_32_RRR1_MADDR_H_64_UL: 7110 CHECK_REG_PAIR(r3); 7111 gen_maddr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], 7112 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); 7113 break; 7114 case OPC2_32_RRR1_MADDRS_H_64_UL: 7115 CHECK_REG_PAIR(r3); 7116 gen_maddr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], 7117 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); 7118 break; 7119 case OPC2_32_RRR1_MADDR_Q_32_LL: 7120 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7121 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7122 gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7123 break; 7124 case OPC2_32_RRR1_MADDR_Q_32_UU: 7125 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7126 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7127 gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7128 break; 7129 case OPC2_32_RRR1_MADDRS_Q_32_LL: 7130 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7131 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7132 gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7133 break; 7134 case OPC2_32_RRR1_MADDRS_Q_32_UU: 7135 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7136 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7137 gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7138 break; 7139 default: 7140 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7141 } 7142 } 7143 7144 static void decode_rrr1_maddsu_h(DisasContext *ctx) 7145 { 7146 uint32_t op2; 7147 uint32_t r1, r2, r3, r4, n; 7148 7149 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 7150 r1 = MASK_OP_RRR1_S1(ctx->opcode); 7151 r2 = MASK_OP_RRR1_S2(ctx->opcode); 7152 r3 = MASK_OP_RRR1_S3(ctx->opcode); 7153 r4 = MASK_OP_RRR1_D(ctx->opcode); 7154 n = MASK_OP_RRR1_N(ctx->opcode); 7155 7156 switch (op2) { 7157 case OPC2_32_RRR1_MADDSU_H_32_LL: 7158 CHECK_REG_PAIR(r4); 7159 CHECK_REG_PAIR(r3); 7160 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7161 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7162 break; 7163 case OPC2_32_RRR1_MADDSU_H_32_LU: 7164 CHECK_REG_PAIR(r4); 7165 CHECK_REG_PAIR(r3); 7166 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7167 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7168 break; 7169 case OPC2_32_RRR1_MADDSU_H_32_UL: 7170 CHECK_REG_PAIR(r4); 7171 CHECK_REG_PAIR(r3); 7172 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7173 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7174 break; 7175 case OPC2_32_RRR1_MADDSU_H_32_UU: 7176 CHECK_REG_PAIR(r4); 7177 CHECK_REG_PAIR(r3); 7178 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7179 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7180 break; 7181 case OPC2_32_RRR1_MADDSUS_H_32_LL: 7182 CHECK_REG_PAIR(r4); 7183 CHECK_REG_PAIR(r3); 7184 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7185 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7186 n, MODE_LL); 7187 break; 7188 case OPC2_32_RRR1_MADDSUS_H_32_LU: 7189 CHECK_REG_PAIR(r4); 7190 CHECK_REG_PAIR(r3); 7191 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7192 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7193 n, MODE_LU); 7194 break; 7195 case OPC2_32_RRR1_MADDSUS_H_32_UL: 7196 CHECK_REG_PAIR(r4); 7197 CHECK_REG_PAIR(r3); 7198 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7199 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7200 n, MODE_UL); 7201 break; 7202 case OPC2_32_RRR1_MADDSUS_H_32_UU: 7203 CHECK_REG_PAIR(r4); 7204 CHECK_REG_PAIR(r3); 7205 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7206 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7207 n, MODE_UU); 7208 break; 7209 case OPC2_32_RRR1_MADDSUM_H_64_LL: 7210 CHECK_REG_PAIR(r4); 7211 CHECK_REG_PAIR(r3); 7212 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7213 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7214 n, MODE_LL); 7215 break; 7216 case OPC2_32_RRR1_MADDSUM_H_64_LU: 7217 CHECK_REG_PAIR(r4); 7218 CHECK_REG_PAIR(r3); 7219 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7220 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7221 n, MODE_LU); 7222 break; 7223 case OPC2_32_RRR1_MADDSUM_H_64_UL: 7224 CHECK_REG_PAIR(r4); 7225 CHECK_REG_PAIR(r3); 7226 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7227 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7228 n, MODE_UL); 7229 break; 7230 case OPC2_32_RRR1_MADDSUM_H_64_UU: 7231 CHECK_REG_PAIR(r4); 7232 CHECK_REG_PAIR(r3); 7233 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7234 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7235 n, MODE_UU); 7236 break; 7237 case OPC2_32_RRR1_MADDSUMS_H_64_LL: 7238 CHECK_REG_PAIR(r4); 7239 CHECK_REG_PAIR(r3); 7240 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7241 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7242 n, MODE_LL); 7243 break; 7244 case OPC2_32_RRR1_MADDSUMS_H_64_LU: 7245 CHECK_REG_PAIR(r4); 7246 CHECK_REG_PAIR(r3); 7247 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7248 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7249 n, MODE_LU); 7250 break; 7251 case OPC2_32_RRR1_MADDSUMS_H_64_UL: 7252 CHECK_REG_PAIR(r4); 7253 CHECK_REG_PAIR(r3); 7254 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7255 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7256 n, MODE_UL); 7257 break; 7258 case OPC2_32_RRR1_MADDSUMS_H_64_UU: 7259 CHECK_REG_PAIR(r4); 7260 CHECK_REG_PAIR(r3); 7261 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7262 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7263 n, MODE_UU); 7264 break; 7265 case OPC2_32_RRR1_MADDSUR_H_16_LL: 7266 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7267 cpu_gpr_d[r2], n, MODE_LL); 7268 break; 7269 case OPC2_32_RRR1_MADDSUR_H_16_LU: 7270 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7271 cpu_gpr_d[r2], n, MODE_LU); 7272 break; 7273 case OPC2_32_RRR1_MADDSUR_H_16_UL: 7274 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7275 cpu_gpr_d[r2], n, MODE_UL); 7276 break; 7277 case OPC2_32_RRR1_MADDSUR_H_16_UU: 7278 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7279 cpu_gpr_d[r2], n, MODE_UU); 7280 break; 7281 case OPC2_32_RRR1_MADDSURS_H_16_LL: 7282 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7283 cpu_gpr_d[r2], n, MODE_LL); 7284 break; 7285 case OPC2_32_RRR1_MADDSURS_H_16_LU: 7286 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7287 cpu_gpr_d[r2], n, MODE_LU); 7288 break; 7289 case OPC2_32_RRR1_MADDSURS_H_16_UL: 7290 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7291 cpu_gpr_d[r2], n, MODE_UL); 7292 break; 7293 case OPC2_32_RRR1_MADDSURS_H_16_UU: 7294 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7295 cpu_gpr_d[r2], n, MODE_UU); 7296 break; 7297 default: 7298 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7299 } 7300 } 7301 7302 static void decode_rrr1_msub(DisasContext *ctx) 7303 { 7304 uint32_t op2; 7305 uint32_t r1, r2, r3, r4, n; 7306 7307 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 7308 r1 = MASK_OP_RRR1_S1(ctx->opcode); 7309 r2 = MASK_OP_RRR1_S2(ctx->opcode); 7310 r3 = MASK_OP_RRR1_S3(ctx->opcode); 7311 r4 = MASK_OP_RRR1_D(ctx->opcode); 7312 n = MASK_OP_RRR1_N(ctx->opcode); 7313 7314 switch (op2) { 7315 case OPC2_32_RRR1_MSUB_H_LL: 7316 CHECK_REG_PAIR(r4); 7317 CHECK_REG_PAIR(r3); 7318 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7319 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7320 break; 7321 case OPC2_32_RRR1_MSUB_H_LU: 7322 CHECK_REG_PAIR(r4); 7323 CHECK_REG_PAIR(r3); 7324 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7325 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7326 break; 7327 case OPC2_32_RRR1_MSUB_H_UL: 7328 CHECK_REG_PAIR(r4); 7329 CHECK_REG_PAIR(r3); 7330 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7331 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7332 break; 7333 case OPC2_32_RRR1_MSUB_H_UU: 7334 CHECK_REG_PAIR(r4); 7335 CHECK_REG_PAIR(r3); 7336 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7337 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7338 break; 7339 case OPC2_32_RRR1_MSUBS_H_LL: 7340 CHECK_REG_PAIR(r4); 7341 CHECK_REG_PAIR(r3); 7342 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7343 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7344 break; 7345 case OPC2_32_RRR1_MSUBS_H_LU: 7346 CHECK_REG_PAIR(r4); 7347 CHECK_REG_PAIR(r3); 7348 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7349 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7350 break; 7351 case OPC2_32_RRR1_MSUBS_H_UL: 7352 CHECK_REG_PAIR(r4); 7353 CHECK_REG_PAIR(r3); 7354 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7355 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7356 break; 7357 case OPC2_32_RRR1_MSUBS_H_UU: 7358 CHECK_REG_PAIR(r4); 7359 CHECK_REG_PAIR(r3); 7360 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7361 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7362 break; 7363 case OPC2_32_RRR1_MSUBM_H_LL: 7364 CHECK_REG_PAIR(r4); 7365 CHECK_REG_PAIR(r3); 7366 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7367 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7368 break; 7369 case OPC2_32_RRR1_MSUBM_H_LU: 7370 CHECK_REG_PAIR(r4); 7371 CHECK_REG_PAIR(r3); 7372 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7373 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7374 break; 7375 case OPC2_32_RRR1_MSUBM_H_UL: 7376 CHECK_REG_PAIR(r4); 7377 CHECK_REG_PAIR(r3); 7378 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7379 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7380 break; 7381 case OPC2_32_RRR1_MSUBM_H_UU: 7382 CHECK_REG_PAIR(r4); 7383 CHECK_REG_PAIR(r3); 7384 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7385 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7386 break; 7387 case OPC2_32_RRR1_MSUBMS_H_LL: 7388 CHECK_REG_PAIR(r4); 7389 CHECK_REG_PAIR(r3); 7390 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7391 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7392 break; 7393 case OPC2_32_RRR1_MSUBMS_H_LU: 7394 CHECK_REG_PAIR(r4); 7395 CHECK_REG_PAIR(r3); 7396 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7397 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7398 break; 7399 case OPC2_32_RRR1_MSUBMS_H_UL: 7400 CHECK_REG_PAIR(r4); 7401 CHECK_REG_PAIR(r3); 7402 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7403 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7404 break; 7405 case OPC2_32_RRR1_MSUBMS_H_UU: 7406 CHECK_REG_PAIR(r4); 7407 CHECK_REG_PAIR(r3); 7408 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7409 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7410 break; 7411 case OPC2_32_RRR1_MSUBR_H_LL: 7412 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7413 cpu_gpr_d[r2], n, MODE_LL); 7414 break; 7415 case OPC2_32_RRR1_MSUBR_H_LU: 7416 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7417 cpu_gpr_d[r2], n, MODE_LU); 7418 break; 7419 case OPC2_32_RRR1_MSUBR_H_UL: 7420 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7421 cpu_gpr_d[r2], n, MODE_UL); 7422 break; 7423 case OPC2_32_RRR1_MSUBR_H_UU: 7424 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7425 cpu_gpr_d[r2], n, MODE_UU); 7426 break; 7427 case OPC2_32_RRR1_MSUBRS_H_LL: 7428 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7429 cpu_gpr_d[r2], n, MODE_LL); 7430 break; 7431 case OPC2_32_RRR1_MSUBRS_H_LU: 7432 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7433 cpu_gpr_d[r2], n, MODE_LU); 7434 break; 7435 case OPC2_32_RRR1_MSUBRS_H_UL: 7436 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7437 cpu_gpr_d[r2], n, MODE_UL); 7438 break; 7439 case OPC2_32_RRR1_MSUBRS_H_UU: 7440 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7441 cpu_gpr_d[r2], n, MODE_UU); 7442 break; 7443 default: 7444 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7445 } 7446 } 7447 7448 static void decode_rrr1_msubq_h(DisasContext *ctx) 7449 { 7450 uint32_t op2; 7451 uint32_t r1, r2, r3, r4, n; 7452 TCGv temp, temp2; 7453 7454 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 7455 r1 = MASK_OP_RRR1_S1(ctx->opcode); 7456 r2 = MASK_OP_RRR1_S2(ctx->opcode); 7457 r3 = MASK_OP_RRR1_S3(ctx->opcode); 7458 r4 = MASK_OP_RRR1_D(ctx->opcode); 7459 n = MASK_OP_RRR1_N(ctx->opcode); 7460 7461 temp = tcg_temp_new(); 7462 temp2 = tcg_temp_new(); 7463 7464 switch (op2) { 7465 case OPC2_32_RRR1_MSUB_Q_32: 7466 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7467 cpu_gpr_d[r2], n, 32); 7468 break; 7469 case OPC2_32_RRR1_MSUB_Q_64: 7470 CHECK_REG_PAIR(r4); 7471 CHECK_REG_PAIR(r3); 7472 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7473 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7474 n); 7475 break; 7476 case OPC2_32_RRR1_MSUB_Q_32_L: 7477 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7478 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7479 temp, n, 16); 7480 break; 7481 case OPC2_32_RRR1_MSUB_Q_64_L: 7482 CHECK_REG_PAIR(r4); 7483 CHECK_REG_PAIR(r3); 7484 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7485 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7486 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7487 n); 7488 break; 7489 case OPC2_32_RRR1_MSUB_Q_32_U: 7490 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7491 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7492 temp, n, 16); 7493 break; 7494 case OPC2_32_RRR1_MSUB_Q_64_U: 7495 CHECK_REG_PAIR(r4); 7496 CHECK_REG_PAIR(r3); 7497 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7498 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7499 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7500 n); 7501 break; 7502 case OPC2_32_RRR1_MSUB_Q_32_LL: 7503 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7504 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7505 gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7506 break; 7507 case OPC2_32_RRR1_MSUB_Q_64_LL: 7508 CHECK_REG_PAIR(r4); 7509 CHECK_REG_PAIR(r3); 7510 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7511 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7512 gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7513 cpu_gpr_d[r3+1], temp, temp2, n); 7514 break; 7515 case OPC2_32_RRR1_MSUB_Q_32_UU: 7516 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7517 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7518 gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7519 break; 7520 case OPC2_32_RRR1_MSUB_Q_64_UU: 7521 CHECK_REG_PAIR(r4); 7522 CHECK_REG_PAIR(r3); 7523 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7524 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7525 gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7526 cpu_gpr_d[r3+1], temp, temp2, n); 7527 break; 7528 case OPC2_32_RRR1_MSUBS_Q_32: 7529 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7530 cpu_gpr_d[r2], n, 32); 7531 break; 7532 case OPC2_32_RRR1_MSUBS_Q_64: 7533 CHECK_REG_PAIR(r4); 7534 CHECK_REG_PAIR(r3); 7535 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7536 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7537 n); 7538 break; 7539 case OPC2_32_RRR1_MSUBS_Q_32_L: 7540 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7541 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7542 temp, n, 16); 7543 break; 7544 case OPC2_32_RRR1_MSUBS_Q_64_L: 7545 CHECK_REG_PAIR(r4); 7546 CHECK_REG_PAIR(r3); 7547 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7548 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7549 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7550 n); 7551 break; 7552 case OPC2_32_RRR1_MSUBS_Q_32_U: 7553 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7554 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7555 temp, n, 16); 7556 break; 7557 case OPC2_32_RRR1_MSUBS_Q_64_U: 7558 CHECK_REG_PAIR(r4); 7559 CHECK_REG_PAIR(r3); 7560 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7561 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7562 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7563 n); 7564 break; 7565 case OPC2_32_RRR1_MSUBS_Q_32_LL: 7566 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7567 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7568 gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7569 break; 7570 case OPC2_32_RRR1_MSUBS_Q_64_LL: 7571 CHECK_REG_PAIR(r4); 7572 CHECK_REG_PAIR(r3); 7573 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7574 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7575 gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7576 cpu_gpr_d[r3+1], temp, temp2, n); 7577 break; 7578 case OPC2_32_RRR1_MSUBS_Q_32_UU: 7579 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7580 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7581 gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7582 break; 7583 case OPC2_32_RRR1_MSUBS_Q_64_UU: 7584 CHECK_REG_PAIR(r4); 7585 CHECK_REG_PAIR(r3); 7586 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7587 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7588 gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7589 cpu_gpr_d[r3+1], temp, temp2, n); 7590 break; 7591 case OPC2_32_RRR1_MSUBR_H_64_UL: 7592 CHECK_REG_PAIR(r3); 7593 gen_msubr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], 7594 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); 7595 break; 7596 case OPC2_32_RRR1_MSUBRS_H_64_UL: 7597 CHECK_REG_PAIR(r3); 7598 gen_msubr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], 7599 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); 7600 break; 7601 case OPC2_32_RRR1_MSUBR_Q_32_LL: 7602 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7603 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7604 gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7605 break; 7606 case OPC2_32_RRR1_MSUBR_Q_32_UU: 7607 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7608 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7609 gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7610 break; 7611 case OPC2_32_RRR1_MSUBRS_Q_32_LL: 7612 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7613 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7614 gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7615 break; 7616 case OPC2_32_RRR1_MSUBRS_Q_32_UU: 7617 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7618 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7619 gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7620 break; 7621 default: 7622 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7623 } 7624 } 7625 7626 static void decode_rrr1_msubad_h(DisasContext *ctx) 7627 { 7628 uint32_t op2; 7629 uint32_t r1, r2, r3, r4, n; 7630 7631 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 7632 r1 = MASK_OP_RRR1_S1(ctx->opcode); 7633 r2 = MASK_OP_RRR1_S2(ctx->opcode); 7634 r3 = MASK_OP_RRR1_S3(ctx->opcode); 7635 r4 = MASK_OP_RRR1_D(ctx->opcode); 7636 n = MASK_OP_RRR1_N(ctx->opcode); 7637 7638 switch (op2) { 7639 case OPC2_32_RRR1_MSUBAD_H_32_LL: 7640 CHECK_REG_PAIR(r4); 7641 CHECK_REG_PAIR(r3); 7642 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7643 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7644 break; 7645 case OPC2_32_RRR1_MSUBAD_H_32_LU: 7646 CHECK_REG_PAIR(r4); 7647 CHECK_REG_PAIR(r3); 7648 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7649 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7650 break; 7651 case OPC2_32_RRR1_MSUBAD_H_32_UL: 7652 CHECK_REG_PAIR(r4); 7653 CHECK_REG_PAIR(r3); 7654 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7655 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7656 break; 7657 case OPC2_32_RRR1_MSUBAD_H_32_UU: 7658 CHECK_REG_PAIR(r4); 7659 CHECK_REG_PAIR(r3); 7660 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7661 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7662 break; 7663 case OPC2_32_RRR1_MSUBADS_H_32_LL: 7664 CHECK_REG_PAIR(r4); 7665 CHECK_REG_PAIR(r3); 7666 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7667 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7668 n, MODE_LL); 7669 break; 7670 case OPC2_32_RRR1_MSUBADS_H_32_LU: 7671 CHECK_REG_PAIR(r4); 7672 CHECK_REG_PAIR(r3); 7673 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7674 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7675 n, MODE_LU); 7676 break; 7677 case OPC2_32_RRR1_MSUBADS_H_32_UL: 7678 CHECK_REG_PAIR(r4); 7679 CHECK_REG_PAIR(r3); 7680 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7681 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7682 n, MODE_UL); 7683 break; 7684 case OPC2_32_RRR1_MSUBADS_H_32_UU: 7685 CHECK_REG_PAIR(r4); 7686 CHECK_REG_PAIR(r3); 7687 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7688 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7689 n, MODE_UU); 7690 break; 7691 case OPC2_32_RRR1_MSUBADM_H_64_LL: 7692 CHECK_REG_PAIR(r4); 7693 CHECK_REG_PAIR(r3); 7694 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7695 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7696 n, MODE_LL); 7697 break; 7698 case OPC2_32_RRR1_MSUBADM_H_64_LU: 7699 CHECK_REG_PAIR(r4); 7700 CHECK_REG_PAIR(r3); 7701 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7702 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7703 n, MODE_LU); 7704 break; 7705 case OPC2_32_RRR1_MSUBADM_H_64_UL: 7706 CHECK_REG_PAIR(r4); 7707 CHECK_REG_PAIR(r3); 7708 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7709 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7710 n, MODE_UL); 7711 break; 7712 case OPC2_32_RRR1_MSUBADM_H_64_UU: 7713 CHECK_REG_PAIR(r4); 7714 CHECK_REG_PAIR(r3); 7715 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7716 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7717 n, MODE_UU); 7718 break; 7719 case OPC2_32_RRR1_MSUBADMS_H_64_LL: 7720 CHECK_REG_PAIR(r4); 7721 CHECK_REG_PAIR(r3); 7722 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7723 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7724 n, MODE_LL); 7725 break; 7726 case OPC2_32_RRR1_MSUBADMS_H_64_LU: 7727 CHECK_REG_PAIR(r4); 7728 CHECK_REG_PAIR(r3); 7729 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7730 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7731 n, MODE_LU); 7732 break; 7733 case OPC2_32_RRR1_MSUBADMS_H_64_UL: 7734 CHECK_REG_PAIR(r4); 7735 CHECK_REG_PAIR(r3); 7736 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7737 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7738 n, MODE_UL); 7739 break; 7740 case OPC2_32_RRR1_MSUBADMS_H_64_UU: 7741 CHECK_REG_PAIR(r4); 7742 CHECK_REG_PAIR(r3); 7743 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7744 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7745 n, MODE_UU); 7746 break; 7747 case OPC2_32_RRR1_MSUBADR_H_16_LL: 7748 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7749 cpu_gpr_d[r2], n, MODE_LL); 7750 break; 7751 case OPC2_32_RRR1_MSUBADR_H_16_LU: 7752 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7753 cpu_gpr_d[r2], n, MODE_LU); 7754 break; 7755 case OPC2_32_RRR1_MSUBADR_H_16_UL: 7756 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7757 cpu_gpr_d[r2], n, MODE_UL); 7758 break; 7759 case OPC2_32_RRR1_MSUBADR_H_16_UU: 7760 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7761 cpu_gpr_d[r2], n, MODE_UU); 7762 break; 7763 case OPC2_32_RRR1_MSUBADRS_H_16_LL: 7764 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7765 cpu_gpr_d[r2], n, MODE_LL); 7766 break; 7767 case OPC2_32_RRR1_MSUBADRS_H_16_LU: 7768 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7769 cpu_gpr_d[r2], n, MODE_LU); 7770 break; 7771 case OPC2_32_RRR1_MSUBADRS_H_16_UL: 7772 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7773 cpu_gpr_d[r2], n, MODE_UL); 7774 break; 7775 case OPC2_32_RRR1_MSUBADRS_H_16_UU: 7776 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7777 cpu_gpr_d[r2], n, MODE_UU); 7778 break; 7779 default: 7780 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7781 } 7782 } 7783 7784 /* RRRR format */ 7785 static void decode_rrrr_extract_insert(DisasContext *ctx) 7786 { 7787 uint32_t op2; 7788 int r1, r2, r3, r4; 7789 TCGv tmp_width, tmp_pos; 7790 7791 r1 = MASK_OP_RRRR_S1(ctx->opcode); 7792 r2 = MASK_OP_RRRR_S2(ctx->opcode); 7793 r3 = MASK_OP_RRRR_S3(ctx->opcode); 7794 r4 = MASK_OP_RRRR_D(ctx->opcode); 7795 op2 = MASK_OP_RRRR_OP2(ctx->opcode); 7796 7797 tmp_pos = tcg_temp_new(); 7798 tmp_width = tcg_temp_new(); 7799 7800 switch (op2) { 7801 case OPC2_32_RRRR_DEXTR: 7802 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f); 7803 if (r1 == r2) { 7804 tcg_gen_rotl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos); 7805 } else { 7806 TCGv msw = tcg_temp_new(); 7807 TCGv zero = tcg_constant_tl(0); 7808 tcg_gen_shl_tl(tmp_width, cpu_gpr_d[r1], tmp_pos); 7809 tcg_gen_subfi_tl(msw, 32, tmp_pos); 7810 tcg_gen_shr_tl(msw, cpu_gpr_d[r2], msw); 7811 /* 7812 * if pos == 0, then we do cpu_gpr_d[r2] << 32, which is undefined 7813 * behaviour. So check that case here and set the low bits to zero 7814 * which effectivly returns cpu_gpr_d[r1] 7815 */ 7816 tcg_gen_movcond_tl(TCG_COND_EQ, msw, tmp_pos, zero, zero, msw); 7817 tcg_gen_or_tl(cpu_gpr_d[r4], tmp_width, msw); 7818 } 7819 break; 7820 case OPC2_32_RRRR_EXTR: 7821 case OPC2_32_RRRR_EXTR_U: 7822 CHECK_REG_PAIR(r3); 7823 tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f); 7824 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f); 7825 tcg_gen_add_tl(tmp_pos, tmp_pos, tmp_width); 7826 tcg_gen_subfi_tl(tmp_pos, 32, tmp_pos); 7827 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos); 7828 tcg_gen_subfi_tl(tmp_width, 32, tmp_width); 7829 if (op2 == OPC2_32_RRRR_EXTR) { 7830 tcg_gen_sar_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width); 7831 } else { 7832 tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width); 7833 } 7834 break; 7835 case OPC2_32_RRRR_INSERT: 7836 CHECK_REG_PAIR(r3); 7837 tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f); 7838 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f); 7839 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], tmp_width, 7840 tmp_pos); 7841 break; 7842 default: 7843 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7844 } 7845 } 7846 7847 /* RRRW format */ 7848 static void decode_rrrw_extract_insert(DisasContext *ctx) 7849 { 7850 uint32_t op2; 7851 int r1, r2, r3, r4; 7852 int32_t width; 7853 7854 TCGv temp, temp2; 7855 7856 op2 = MASK_OP_RRRW_OP2(ctx->opcode); 7857 r1 = MASK_OP_RRRW_S1(ctx->opcode); 7858 r2 = MASK_OP_RRRW_S2(ctx->opcode); 7859 r3 = MASK_OP_RRRW_S3(ctx->opcode); 7860 r4 = MASK_OP_RRRW_D(ctx->opcode); 7861 width = MASK_OP_RRRW_WIDTH(ctx->opcode); 7862 7863 temp = tcg_temp_new(); 7864 7865 switch (op2) { 7866 case OPC2_32_RRRW_EXTR: 7867 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); 7868 tcg_gen_addi_tl(temp, temp, width); 7869 tcg_gen_subfi_tl(temp, 32, temp); 7870 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp); 7871 tcg_gen_sari_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], 32 - width); 7872 break; 7873 case OPC2_32_RRRW_EXTR_U: 7874 if (width == 0) { 7875 tcg_gen_movi_tl(cpu_gpr_d[r4], 0); 7876 } else { 7877 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); 7878 tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp); 7879 tcg_gen_andi_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], ~0u >> (32-width)); 7880 } 7881 break; 7882 case OPC2_32_RRRW_IMASK: 7883 temp2 = tcg_temp_new(); 7884 CHECK_REG_PAIR(r4); 7885 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); 7886 tcg_gen_movi_tl(temp2, (1 << width) - 1); 7887 tcg_gen_shl_tl(temp2, temp2, temp); 7888 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r2], temp); 7889 tcg_gen_mov_tl(cpu_gpr_d[r4+1], temp2); 7890 break; 7891 case OPC2_32_RRRW_INSERT: 7892 temp2 = tcg_temp_new(); 7893 7894 tcg_gen_movi_tl(temp, width); 7895 tcg_gen_andi_tl(temp2, cpu_gpr_d[r3], 0x1f); 7896 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], temp, temp2); 7897 break; 7898 default: 7899 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7900 } 7901 } 7902 7903 /* SYS Format*/ 7904 static void decode_sys_interrupts(DisasContext *ctx) 7905 { 7906 uint32_t op2; 7907 uint32_t r1; 7908 TCGLabel *l1; 7909 TCGv tmp; 7910 7911 op2 = MASK_OP_SYS_OP2(ctx->opcode); 7912 r1 = MASK_OP_SYS_S1D(ctx->opcode); 7913 7914 switch (op2) { 7915 case OPC2_32_SYS_DEBUG: 7916 /* raise EXCP_DEBUG */ 7917 break; 7918 case OPC2_32_SYS_DISABLE: 7919 if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) { 7920 tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~ctx->icr_ie_mask); 7921 } else { 7922 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); 7923 } 7924 break; 7925 case OPC2_32_SYS_DISABLE_D: 7926 if (has_feature(ctx, TRICORE_FEATURE_16)) { 7927 if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) { 7928 tcg_gen_extract_tl(cpu_gpr_d[r1], cpu_ICR, 7929 ctx->icr_ie_offset, 1); 7930 tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~ctx->icr_ie_mask); 7931 } else { 7932 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); 7933 } 7934 } else { 7935 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7936 } 7937 case OPC2_32_SYS_DSYNC: 7938 break; 7939 case OPC2_32_SYS_ENABLE: 7940 if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) { 7941 tcg_gen_ori_tl(cpu_ICR, cpu_ICR, ctx->icr_ie_mask); 7942 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 7943 } else { 7944 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); 7945 } 7946 break; 7947 case OPC2_32_SYS_ISYNC: 7948 break; 7949 case OPC2_32_SYS_NOP: 7950 break; 7951 case OPC2_32_SYS_RET: 7952 gen_compute_branch(ctx, op2, 0, 0, 0, 0); 7953 break; 7954 case OPC2_32_SYS_FRET: 7955 gen_fret(ctx); 7956 break; 7957 case OPC2_32_SYS_RFE: 7958 gen_helper_rfe(tcg_env); 7959 ctx->base.is_jmp = DISAS_EXIT; 7960 break; 7961 case OPC2_32_SYS_RFM: 7962 if (ctx->priv == TRICORE_PRIV_SM) { 7963 tmp = tcg_temp_new(); 7964 l1 = gen_new_label(); 7965 7966 tcg_gen_ld32u_tl(tmp, tcg_env, offsetof(CPUTriCoreState, DBGSR)); 7967 tcg_gen_andi_tl(tmp, tmp, MASK_DBGSR_DE); 7968 tcg_gen_brcondi_tl(TCG_COND_NE, tmp, 1, l1); 7969 gen_helper_rfm(tcg_env); 7970 gen_set_label(l1); 7971 ctx->base.is_jmp = DISAS_EXIT; 7972 } else { 7973 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); 7974 } 7975 break; 7976 case OPC2_32_SYS_RSLCX: 7977 gen_helper_rslcx(tcg_env); 7978 break; 7979 case OPC2_32_SYS_SVLCX: 7980 gen_helper_svlcx(tcg_env); 7981 break; 7982 case OPC2_32_SYS_RESTORE: 7983 if (has_feature(ctx, TRICORE_FEATURE_16)) { 7984 if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) { 7985 tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], 7986 ctx->icr_ie_offset, 1); 7987 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 7988 } else { 7989 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); 7990 } 7991 } else { 7992 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7993 } 7994 break; 7995 case OPC2_32_SYS_TRAPSV: 7996 l1 = gen_new_label(); 7997 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_SV, 0, l1); 7998 generate_trap(ctx, TRAPC_ASSERT, TIN5_SOVF); 7999 gen_set_label(l1); 8000 break; 8001 case OPC2_32_SYS_TRAPV: 8002 l1 = gen_new_label(); 8003 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_V, 0, l1); 8004 generate_trap(ctx, TRAPC_ASSERT, TIN5_OVF); 8005 gen_set_label(l1); 8006 break; 8007 default: 8008 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 8009 } 8010 } 8011 8012 static void decode_32Bit_opc(DisasContext *ctx) 8013 { 8014 int op1, op2; 8015 int32_t r1, r2, r3; 8016 int32_t address, const16; 8017 int8_t b, const4; 8018 int32_t bpos; 8019 TCGv temp, temp2, temp3; 8020 8021 op1 = MASK_OP_MAJOR(ctx->opcode); 8022 8023 /* handle JNZ.T opcode only being 7 bit long */ 8024 if (unlikely((op1 & 0x7f) == OPCM_32_BRN_JTT)) { 8025 op1 = OPCM_32_BRN_JTT; 8026 } 8027 8028 switch (op1) { 8029 /* ABS-format */ 8030 case OPCM_32_ABS_LDW: 8031 decode_abs_ldw(ctx); 8032 break; 8033 case OPCM_32_ABS_LDB: 8034 decode_abs_ldb(ctx); 8035 break; 8036 case OPCM_32_ABS_LDMST_SWAP: 8037 decode_abs_ldst_swap(ctx); 8038 break; 8039 case OPCM_32_ABS_LDST_CONTEXT: 8040 decode_abs_ldst_context(ctx); 8041 break; 8042 case OPCM_32_ABS_STORE: 8043 decode_abs_store(ctx); 8044 break; 8045 case OPCM_32_ABS_STOREB_H: 8046 decode_abs_storeb_h(ctx); 8047 break; 8048 case OPC1_32_ABS_STOREQ: 8049 address = MASK_OP_ABS_OFF18(ctx->opcode); 8050 r1 = MASK_OP_ABS_S1D(ctx->opcode); 8051 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 8052 temp2 = tcg_temp_new(); 8053 8054 tcg_gen_shri_tl(temp2, cpu_gpr_d[r1], 16); 8055 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_LEUW); 8056 break; 8057 case OPC1_32_ABS_LD_Q: 8058 address = MASK_OP_ABS_OFF18(ctx->opcode); 8059 r1 = MASK_OP_ABS_S1D(ctx->opcode); 8060 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 8061 8062 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); 8063 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 8064 break; 8065 case OPCM_32_ABS_LEA_LHA: 8066 address = MASK_OP_ABS_OFF18(ctx->opcode); 8067 r1 = MASK_OP_ABS_S1D(ctx->opcode); 8068 8069 if (has_feature(ctx, TRICORE_FEATURE_162)) { 8070 op2 = MASK_OP_ABS_OP2(ctx->opcode); 8071 if (op2 == OPC2_32_ABS_LHA) { 8072 tcg_gen_movi_tl(cpu_gpr_a[r1], address << 14); 8073 break; 8074 } 8075 /* otherwise translate regular LEA */ 8076 } 8077 8078 tcg_gen_movi_tl(cpu_gpr_a[r1], EA_ABS_FORMAT(address)); 8079 break; 8080 /* ABSB-format */ 8081 case OPC1_32_ABSB_ST_T: 8082 address = MASK_OP_ABS_OFF18(ctx->opcode); 8083 b = MASK_OP_ABSB_B(ctx->opcode); 8084 bpos = MASK_OP_ABSB_BPOS(ctx->opcode); 8085 8086 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 8087 temp2 = tcg_temp_new(); 8088 8089 tcg_gen_qemu_ld_tl(temp2, temp, ctx->mem_idx, MO_UB); 8090 tcg_gen_andi_tl(temp2, temp2, ~(0x1u << bpos)); 8091 tcg_gen_ori_tl(temp2, temp2, (b << bpos)); 8092 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_UB); 8093 break; 8094 /* B-format */ 8095 case OPC1_32_B_CALL: 8096 case OPC1_32_B_CALLA: 8097 case OPC1_32_B_FCALL: 8098 case OPC1_32_B_FCALLA: 8099 case OPC1_32_B_J: 8100 case OPC1_32_B_JA: 8101 case OPC1_32_B_JL: 8102 case OPC1_32_B_JLA: 8103 address = MASK_OP_B_DISP24_SEXT(ctx->opcode); 8104 gen_compute_branch(ctx, op1, 0, 0, 0, address); 8105 break; 8106 /* Bit-format */ 8107 case OPCM_32_BIT_ANDACC: 8108 decode_bit_andacc(ctx); 8109 break; 8110 case OPCM_32_BIT_LOGICAL_T1: 8111 decode_bit_logical_t(ctx); 8112 break; 8113 case OPCM_32_BIT_INSERT: 8114 decode_bit_insert(ctx); 8115 break; 8116 case OPCM_32_BIT_LOGICAL_T2: 8117 decode_bit_logical_t2(ctx); 8118 break; 8119 case OPCM_32_BIT_ORAND: 8120 decode_bit_orand(ctx); 8121 break; 8122 case OPCM_32_BIT_SH_LOGIC1: 8123 decode_bit_sh_logic1(ctx); 8124 break; 8125 case OPCM_32_BIT_SH_LOGIC2: 8126 decode_bit_sh_logic2(ctx); 8127 break; 8128 /* BO Format */ 8129 case OPCM_32_BO_ADDRMODE_POST_PRE_BASE: 8130 decode_bo_addrmode_post_pre_base(ctx); 8131 break; 8132 case OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR: 8133 decode_bo_addrmode_bitreverse_circular(ctx); 8134 break; 8135 case OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE: 8136 decode_bo_addrmode_ld_post_pre_base(ctx); 8137 break; 8138 case OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR: 8139 decode_bo_addrmode_ld_bitreverse_circular(ctx); 8140 break; 8141 case OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE: 8142 decode_bo_addrmode_stctx_post_pre_base(ctx); 8143 break; 8144 case OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR: 8145 decode_bo_addrmode_ldmst_bitreverse_circular(ctx); 8146 break; 8147 /* BOL-format */ 8148 case OPC1_32_BOL_LD_A_LONGOFF: 8149 case OPC1_32_BOL_LD_W_LONGOFF: 8150 case OPC1_32_BOL_LEA_LONGOFF: 8151 case OPC1_32_BOL_ST_W_LONGOFF: 8152 case OPC1_32_BOL_ST_A_LONGOFF: 8153 case OPC1_32_BOL_LD_B_LONGOFF: 8154 case OPC1_32_BOL_LD_BU_LONGOFF: 8155 case OPC1_32_BOL_LD_H_LONGOFF: 8156 case OPC1_32_BOL_LD_HU_LONGOFF: 8157 case OPC1_32_BOL_ST_B_LONGOFF: 8158 case OPC1_32_BOL_ST_H_LONGOFF: 8159 decode_bol_opc(ctx, op1); 8160 break; 8161 /* BRC Format */ 8162 case OPCM_32_BRC_EQ_NEQ: 8163 case OPCM_32_BRC_GE: 8164 case OPCM_32_BRC_JLT: 8165 case OPCM_32_BRC_JNE: 8166 const4 = MASK_OP_BRC_CONST4_SEXT(ctx->opcode); 8167 address = MASK_OP_BRC_DISP15_SEXT(ctx->opcode); 8168 r1 = MASK_OP_BRC_S1(ctx->opcode); 8169 gen_compute_branch(ctx, op1, r1, 0, const4, address); 8170 break; 8171 /* BRN Format */ 8172 case OPCM_32_BRN_JTT: 8173 address = MASK_OP_BRN_DISP15_SEXT(ctx->opcode); 8174 r1 = MASK_OP_BRN_S1(ctx->opcode); 8175 gen_compute_branch(ctx, op1, r1, 0, 0, address); 8176 break; 8177 /* BRR Format */ 8178 case OPCM_32_BRR_EQ_NEQ: 8179 case OPCM_32_BRR_ADDR_EQ_NEQ: 8180 case OPCM_32_BRR_GE: 8181 case OPCM_32_BRR_JLT: 8182 case OPCM_32_BRR_JNE: 8183 case OPCM_32_BRR_JNZ: 8184 case OPCM_32_BRR_LOOP: 8185 address = MASK_OP_BRR_DISP15_SEXT(ctx->opcode); 8186 r2 = MASK_OP_BRR_S2(ctx->opcode); 8187 r1 = MASK_OP_BRR_S1(ctx->opcode); 8188 gen_compute_branch(ctx, op1, r1, r2, 0, address); 8189 break; 8190 /* RC Format */ 8191 case OPCM_32_RC_LOGICAL_SHIFT: 8192 decode_rc_logical_shift(ctx); 8193 break; 8194 case OPCM_32_RC_ACCUMULATOR: 8195 decode_rc_accumulator(ctx); 8196 break; 8197 case OPCM_32_RC_SERVICEROUTINE: 8198 decode_rc_serviceroutine(ctx); 8199 break; 8200 case OPCM_32_RC_MUL: 8201 decode_rc_mul(ctx); 8202 break; 8203 /* RCPW Format */ 8204 case OPCM_32_RCPW_MASK_INSERT: 8205 decode_rcpw_insert(ctx); 8206 break; 8207 /* RCRR Format */ 8208 case OPC1_32_RCRR_INSERT: 8209 r1 = MASK_OP_RCRR_S1(ctx->opcode); 8210 r2 = MASK_OP_RCRR_S3(ctx->opcode); 8211 r3 = MASK_OP_RCRR_D(ctx->opcode); 8212 const16 = MASK_OP_RCRR_CONST4(ctx->opcode); 8213 temp = tcg_constant_i32(const16); 8214 temp2 = tcg_temp_new(); /* width*/ 8215 temp3 = tcg_temp_new(); /* pos */ 8216 8217 CHECK_REG_PAIR(r2); 8218 8219 tcg_gen_andi_tl(temp2, cpu_gpr_d[r2 + 1], 0x1f); 8220 tcg_gen_andi_tl(temp3, cpu_gpr_d[r2], 0x1f); 8221 8222 gen_insert(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, temp2, temp3); 8223 break; 8224 /* RCRW Format */ 8225 case OPCM_32_RCRW_MASK_INSERT: 8226 decode_rcrw_insert(ctx); 8227 break; 8228 /* RCR Format */ 8229 case OPCM_32_RCR_COND_SELECT: 8230 decode_rcr_cond_select(ctx); 8231 break; 8232 case OPCM_32_RCR_MADD: 8233 decode_rcr_madd(ctx); 8234 break; 8235 case OPCM_32_RCR_MSUB: 8236 decode_rcr_msub(ctx); 8237 break; 8238 /* RLC Format */ 8239 case OPC1_32_RLC_ADDI: 8240 case OPC1_32_RLC_ADDIH: 8241 case OPC1_32_RLC_ADDIH_A: 8242 case OPC1_32_RLC_MFCR: 8243 case OPC1_32_RLC_MOV: 8244 case OPC1_32_RLC_MOV_64: 8245 case OPC1_32_RLC_MOV_U: 8246 case OPC1_32_RLC_MOV_H: 8247 case OPC1_32_RLC_MOVH_A: 8248 case OPC1_32_RLC_MTCR: 8249 decode_rlc_opc(ctx, op1); 8250 break; 8251 /* RR Format */ 8252 case OPCM_32_RR_ACCUMULATOR: 8253 decode_rr_accumulator(ctx); 8254 break; 8255 case OPCM_32_RR_LOGICAL_SHIFT: 8256 decode_rr_logical_shift(ctx); 8257 break; 8258 case OPCM_32_RR_ADDRESS: 8259 decode_rr_address(ctx); 8260 break; 8261 case OPCM_32_RR_IDIRECT: 8262 decode_rr_idirect(ctx); 8263 break; 8264 case OPCM_32_RR_DIVIDE: 8265 decode_rr_divide(ctx); 8266 break; 8267 /* RR1 Format */ 8268 case OPCM_32_RR1_MUL: 8269 decode_rr1_mul(ctx); 8270 break; 8271 case OPCM_32_RR1_MULQ: 8272 decode_rr1_mulq(ctx); 8273 break; 8274 /* RR2 format */ 8275 case OPCM_32_RR2_MUL: 8276 decode_rr2_mul(ctx); 8277 break; 8278 /* RRPW format */ 8279 case OPCM_32_RRPW_EXTRACT_INSERT: 8280 decode_rrpw_extract_insert(ctx); 8281 break; 8282 case OPC1_32_RRPW_DEXTR: 8283 r1 = MASK_OP_RRPW_S1(ctx->opcode); 8284 r2 = MASK_OP_RRPW_S2(ctx->opcode); 8285 r3 = MASK_OP_RRPW_D(ctx->opcode); 8286 const16 = MASK_OP_RRPW_POS(ctx->opcode); 8287 8288 tcg_gen_extract2_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], cpu_gpr_d[r1], 8289 32 - const16); 8290 break; 8291 /* RRR Format */ 8292 case OPCM_32_RRR_COND_SELECT: 8293 decode_rrr_cond_select(ctx); 8294 break; 8295 case OPCM_32_RRR_DIVIDE: 8296 decode_rrr_divide(ctx); 8297 break; 8298 /* RRR2 Format */ 8299 case OPCM_32_RRR2_MADD: 8300 decode_rrr2_madd(ctx); 8301 break; 8302 case OPCM_32_RRR2_MSUB: 8303 decode_rrr2_msub(ctx); 8304 break; 8305 /* RRR1 format */ 8306 case OPCM_32_RRR1_MADD: 8307 decode_rrr1_madd(ctx); 8308 break; 8309 case OPCM_32_RRR1_MADDQ_H: 8310 decode_rrr1_maddq_h(ctx); 8311 break; 8312 case OPCM_32_RRR1_MADDSU_H: 8313 decode_rrr1_maddsu_h(ctx); 8314 break; 8315 case OPCM_32_RRR1_MSUB_H: 8316 decode_rrr1_msub(ctx); 8317 break; 8318 case OPCM_32_RRR1_MSUB_Q: 8319 decode_rrr1_msubq_h(ctx); 8320 break; 8321 case OPCM_32_RRR1_MSUBAD_H: 8322 decode_rrr1_msubad_h(ctx); 8323 break; 8324 /* RRRR format */ 8325 case OPCM_32_RRRR_EXTRACT_INSERT: 8326 decode_rrrr_extract_insert(ctx); 8327 break; 8328 /* RRRW format */ 8329 case OPCM_32_RRRW_EXTRACT_INSERT: 8330 decode_rrrw_extract_insert(ctx); 8331 break; 8332 /* SYS format */ 8333 case OPCM_32_SYS_INTERRUPTS: 8334 decode_sys_interrupts(ctx); 8335 break; 8336 case OPC1_32_SYS_RSTV: 8337 tcg_gen_movi_tl(cpu_PSW_V, 0); 8338 tcg_gen_mov_tl(cpu_PSW_SV, cpu_PSW_V); 8339 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 8340 tcg_gen_mov_tl(cpu_PSW_SAV, cpu_PSW_V); 8341 break; 8342 default: 8343 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 8344 } 8345 } 8346 8347 static bool tricore_insn_is_16bit(uint32_t insn) 8348 { 8349 return (insn & 0x1) == 0; 8350 } 8351 8352 static void tricore_tr_init_disas_context(DisasContextBase *dcbase, 8353 CPUState *cs) 8354 { 8355 DisasContext *ctx = container_of(dcbase, DisasContext, base); 8356 CPUTriCoreState *env = cpu_env(cs); 8357 ctx->mem_idx = cpu_mmu_index(cs, false); 8358 8359 uint32_t tb_flags = (uint32_t)ctx->base.tb->flags; 8360 ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV); 8361 8362 ctx->features = env->features; 8363 if (has_feature(ctx, TRICORE_FEATURE_161)) { 8364 ctx->icr_ie_mask = R_ICR_IE_161_MASK; 8365 ctx->icr_ie_offset = R_ICR_IE_161_SHIFT; 8366 } else { 8367 ctx->icr_ie_mask = R_ICR_IE_13_MASK; 8368 ctx->icr_ie_offset = R_ICR_IE_13_SHIFT; 8369 } 8370 } 8371 8372 static void tricore_tr_tb_start(DisasContextBase *db, CPUState *cpu) 8373 { 8374 } 8375 8376 static void tricore_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 8377 { 8378 DisasContext *ctx = container_of(dcbase, DisasContext, base); 8379 8380 tcg_gen_insn_start(ctx->base.pc_next); 8381 } 8382 8383 static bool insn_crosses_page(CPUTriCoreState *env, DisasContext *ctx) 8384 { 8385 /* 8386 * Return true if the insn at ctx->base.pc_next might cross a page boundary. 8387 * (False positives are OK, false negatives are not.) 8388 * Our caller ensures we are only called if dc->base.pc_next is less than 8389 * 4 bytes from the page boundary, so we cross the page if the first 8390 * 16 bits indicate that this is a 32 bit insn. 8391 */ 8392 uint16_t insn = translator_lduw(env, &ctx->base, ctx->base.pc_next); 8393 8394 return !tricore_insn_is_16bit(insn); 8395 } 8396 8397 8398 static void tricore_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 8399 { 8400 DisasContext *ctx = container_of(dcbase, DisasContext, base); 8401 CPUTriCoreState *env = cpu_env(cpu); 8402 uint16_t insn_lo; 8403 bool is_16bit; 8404 8405 insn_lo = translator_lduw(env, &ctx->base, ctx->base.pc_next); 8406 is_16bit = tricore_insn_is_16bit(insn_lo); 8407 if (is_16bit) { 8408 ctx->opcode = insn_lo; 8409 ctx->pc_succ_insn = ctx->base.pc_next + 2; 8410 decode_16Bit_opc(ctx); 8411 } else { 8412 uint32_t insn_hi = translator_lduw(env, &ctx->base, 8413 ctx->base.pc_next + 2); 8414 ctx->opcode = insn_hi << 16 | insn_lo; 8415 ctx->pc_succ_insn = ctx->base.pc_next + 4; 8416 decode_32Bit_opc(ctx); 8417 } 8418 ctx->base.pc_next = ctx->pc_succ_insn; 8419 8420 if (ctx->base.is_jmp == DISAS_NEXT) { 8421 target_ulong page_start; 8422 8423 page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 8424 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE 8425 || (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE - 3 8426 && insn_crosses_page(env, ctx))) { 8427 ctx->base.is_jmp = DISAS_TOO_MANY; 8428 } 8429 } 8430 } 8431 8432 static void tricore_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 8433 { 8434 DisasContext *ctx = container_of(dcbase, DisasContext, base); 8435 8436 switch (ctx->base.is_jmp) { 8437 case DISAS_TOO_MANY: 8438 gen_goto_tb(ctx, 0, ctx->base.pc_next); 8439 break; 8440 case DISAS_EXIT_UPDATE: 8441 gen_save_pc(ctx->base.pc_next); 8442 /* fall through */ 8443 case DISAS_EXIT: 8444 tcg_gen_exit_tb(NULL, 0); 8445 break; 8446 case DISAS_JUMP: 8447 tcg_gen_lookup_and_goto_ptr(); 8448 break; 8449 case DISAS_NORETURN: 8450 break; 8451 default: 8452 g_assert_not_reached(); 8453 } 8454 } 8455 8456 static const TranslatorOps tricore_tr_ops = { 8457 .init_disas_context = tricore_tr_init_disas_context, 8458 .tb_start = tricore_tr_tb_start, 8459 .insn_start = tricore_tr_insn_start, 8460 .translate_insn = tricore_tr_translate_insn, 8461 .tb_stop = tricore_tr_tb_stop, 8462 }; 8463 8464 void tricore_translate_code(CPUState *cs, TranslationBlock *tb, 8465 int *max_insns, vaddr pc, void *host_pc) 8466 { 8467 DisasContext ctx; 8468 translator_loop(cs, tb, max_insns, pc, host_pc, 8469 &tricore_tr_ops, &ctx.base); 8470 } 8471 8472 /* 8473 * 8474 * Initialization 8475 * 8476 */ 8477 8478 void cpu_state_reset(CPUTriCoreState *env) 8479 { 8480 /* Reset Regs to Default Value */ 8481 env->PSW = 0xb80; 8482 fpu_set_state(env); 8483 } 8484 8485 static void tricore_tcg_init_csfr(void) 8486 { 8487 cpu_PCXI = tcg_global_mem_new(tcg_env, 8488 offsetof(CPUTriCoreState, PCXI), "PCXI"); 8489 cpu_PSW = tcg_global_mem_new(tcg_env, 8490 offsetof(CPUTriCoreState, PSW), "PSW"); 8491 cpu_PC = tcg_global_mem_new(tcg_env, 8492 offsetof(CPUTriCoreState, PC), "PC"); 8493 cpu_ICR = tcg_global_mem_new(tcg_env, 8494 offsetof(CPUTriCoreState, ICR), "ICR"); 8495 } 8496 8497 void tricore_tcg_init(void) 8498 { 8499 int i; 8500 8501 /* reg init */ 8502 for (i = 0 ; i < 16 ; i++) { 8503 cpu_gpr_a[i] = tcg_global_mem_new(tcg_env, 8504 offsetof(CPUTriCoreState, gpr_a[i]), 8505 regnames_a[i]); 8506 } 8507 for (i = 0 ; i < 16 ; i++) { 8508 cpu_gpr_d[i] = tcg_global_mem_new(tcg_env, 8509 offsetof(CPUTriCoreState, gpr_d[i]), 8510 regnames_d[i]); 8511 } 8512 tricore_tcg_init_csfr(); 8513 /* init PSW flag cache */ 8514 cpu_PSW_C = tcg_global_mem_new(tcg_env, 8515 offsetof(CPUTriCoreState, PSW_USB_C), 8516 "PSW_C"); 8517 cpu_PSW_V = tcg_global_mem_new(tcg_env, 8518 offsetof(CPUTriCoreState, PSW_USB_V), 8519 "PSW_V"); 8520 cpu_PSW_SV = tcg_global_mem_new(tcg_env, 8521 offsetof(CPUTriCoreState, PSW_USB_SV), 8522 "PSW_SV"); 8523 cpu_PSW_AV = tcg_global_mem_new(tcg_env, 8524 offsetof(CPUTriCoreState, PSW_USB_AV), 8525 "PSW_AV"); 8526 cpu_PSW_SAV = tcg_global_mem_new(tcg_env, 8527 offsetof(CPUTriCoreState, PSW_USB_SAV), 8528 "PSW_SAV"); 8529 } 8530