1 /* 2 * TriCore emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2013-2014 Bastian Koppelmann C-Lab/University Paderborn 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "tcg/tcg-op.h" 24 #include "accel/tcg/cpu-ldst.h" 25 #include "qemu/qemu-print.h" 26 27 #include "exec/helper-proto.h" 28 #include "exec/helper-gen.h" 29 30 #include "tricore-opcodes.h" 31 #include "exec/translator.h" 32 #include "exec/translation-block.h" 33 #include "exec/target_page.h" 34 #include "exec/log.h" 35 36 #define HELPER_H "helper.h" 37 #include "exec/helper-info.c.inc" 38 #undef HELPER_H 39 40 #define DISAS_EXIT DISAS_TARGET_0 41 #define DISAS_EXIT_UPDATE DISAS_TARGET_1 42 #define DISAS_JUMP DISAS_TARGET_2 43 44 /* 45 * TCG registers 46 */ 47 static TCGv cpu_PC; 48 static TCGv cpu_PCXI; 49 static TCGv cpu_PSW; 50 static TCGv cpu_ICR; 51 /* GPR registers */ 52 static TCGv cpu_gpr_a[16]; 53 static TCGv cpu_gpr_d[16]; 54 /* PSW Flag cache */ 55 static TCGv cpu_PSW_C; 56 static TCGv cpu_PSW_V; 57 static TCGv cpu_PSW_SV; 58 static TCGv cpu_PSW_AV; 59 static TCGv cpu_PSW_SAV; 60 61 static const char *regnames_a[] = { 62 "a0" , "a1" , "a2" , "a3" , "a4" , "a5" , 63 "a6" , "a7" , "a8" , "a9" , "sp" , "a11" , 64 "a12" , "a13" , "a14" , "a15", 65 }; 66 67 static const char *regnames_d[] = { 68 "d0" , "d1" , "d2" , "d3" , "d4" , "d5" , 69 "d6" , "d7" , "d8" , "d9" , "d10" , "d11" , 70 "d12" , "d13" , "d14" , "d15", 71 }; 72 73 typedef struct DisasContext { 74 DisasContextBase base; 75 target_ulong pc_succ_insn; 76 uint32_t opcode; 77 /* Routine used to access memory */ 78 int mem_idx; 79 int priv; 80 uint64_t features; 81 uint32_t icr_ie_mask, icr_ie_offset; 82 } DisasContext; 83 84 static int has_feature(DisasContext *ctx, int feature) 85 { 86 return (ctx->features & (1ULL << feature)) != 0; 87 } 88 89 enum { 90 MODE_LL = 0, 91 MODE_LU = 1, 92 MODE_UL = 2, 93 MODE_UU = 3, 94 }; 95 96 void tricore_cpu_dump_state(CPUState *cs, FILE *f, int flags) 97 { 98 CPUTriCoreState *env = cpu_env(cs); 99 uint32_t psw; 100 int i; 101 102 psw = psw_read(env); 103 104 qemu_fprintf(f, "PC: " TARGET_FMT_lx, env->PC); 105 qemu_fprintf(f, " PSW: " TARGET_FMT_lx, psw); 106 qemu_fprintf(f, " ICR: " TARGET_FMT_lx, env->ICR); 107 qemu_fprintf(f, "\nPCXI: " TARGET_FMT_lx, env->PCXI); 108 qemu_fprintf(f, " FCX: " TARGET_FMT_lx, env->FCX); 109 qemu_fprintf(f, " LCX: " TARGET_FMT_lx, env->LCX); 110 111 for (i = 0; i < 16; ++i) { 112 if ((i & 3) == 0) { 113 qemu_fprintf(f, "\nGPR A%02d:", i); 114 } 115 qemu_fprintf(f, " " TARGET_FMT_lx, env->gpr_a[i]); 116 } 117 for (i = 0; i < 16; ++i) { 118 if ((i & 3) == 0) { 119 qemu_fprintf(f, "\nGPR D%02d:", i); 120 } 121 qemu_fprintf(f, " " TARGET_FMT_lx, env->gpr_d[i]); 122 } 123 qemu_fprintf(f, "\n"); 124 } 125 126 /* 127 * Functions to generate micro-ops 128 */ 129 130 /* Macros for generating helpers */ 131 132 #define gen_helper_1arg(name, arg) do { \ 133 TCGv_i32 helper_tmp = tcg_constant_i32(arg); \ 134 gen_helper_##name(tcg_env, helper_tmp); \ 135 } while (0) 136 137 #define GEN_HELPER_LL(name, ret, arg0, arg1, n) do { \ 138 TCGv arg00 = tcg_temp_new(); \ 139 TCGv arg01 = tcg_temp_new(); \ 140 TCGv arg11 = tcg_temp_new(); \ 141 tcg_gen_sari_tl(arg00, arg0, 16); \ 142 tcg_gen_ext16s_tl(arg01, arg0); \ 143 tcg_gen_ext16s_tl(arg11, arg1); \ 144 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \ 145 } while (0) 146 147 #define GEN_HELPER_LU(name, ret, arg0, arg1, n) do { \ 148 TCGv arg00 = tcg_temp_new(); \ 149 TCGv arg01 = tcg_temp_new(); \ 150 TCGv arg10 = tcg_temp_new(); \ 151 TCGv arg11 = tcg_temp_new(); \ 152 tcg_gen_sari_tl(arg00, arg0, 16); \ 153 tcg_gen_ext16s_tl(arg01, arg0); \ 154 tcg_gen_sari_tl(arg11, arg1, 16); \ 155 tcg_gen_ext16s_tl(arg10, arg1); \ 156 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \ 157 } while (0) 158 159 #define GEN_HELPER_UL(name, ret, arg0, arg1, n) do { \ 160 TCGv arg00 = tcg_temp_new(); \ 161 TCGv arg01 = tcg_temp_new(); \ 162 TCGv arg10 = tcg_temp_new(); \ 163 TCGv arg11 = tcg_temp_new(); \ 164 tcg_gen_sari_tl(arg00, arg0, 16); \ 165 tcg_gen_ext16s_tl(arg01, arg0); \ 166 tcg_gen_sari_tl(arg10, arg1, 16); \ 167 tcg_gen_ext16s_tl(arg11, arg1); \ 168 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \ 169 } while (0) 170 171 #define GEN_HELPER_UU(name, ret, arg0, arg1, n) do { \ 172 TCGv arg00 = tcg_temp_new(); \ 173 TCGv arg01 = tcg_temp_new(); \ 174 TCGv arg11 = tcg_temp_new(); \ 175 tcg_gen_sari_tl(arg01, arg0, 16); \ 176 tcg_gen_ext16s_tl(arg00, arg0); \ 177 tcg_gen_sari_tl(arg11, arg1, 16); \ 178 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \ 179 } while (0) 180 181 #define GEN_HELPER_RRR(name, rl, rh, al1, ah1, arg2) do { \ 182 TCGv_i64 ret = tcg_temp_new_i64(); \ 183 TCGv_i64 arg1 = tcg_temp_new_i64(); \ 184 \ 185 tcg_gen_concat_i32_i64(arg1, al1, ah1); \ 186 gen_helper_##name(ret, arg1, arg2); \ 187 tcg_gen_extr_i64_i32(rl, rh, ret); \ 188 } while (0) 189 190 #define GEN_HELPER_RR(name, rl, rh, arg1, arg2) do { \ 191 TCGv_i64 ret = tcg_temp_new_i64(); \ 192 \ 193 gen_helper_##name(ret, tcg_env, arg1, arg2); \ 194 tcg_gen_extr_i64_i32(rl, rh, ret); \ 195 } while (0) 196 197 #define EA_ABS_FORMAT(con) (((con & 0x3C000) << 14) + (con & 0x3FFF)) 198 #define EA_B_ABSOLUT(con) (((offset & 0xf00000) << 8) | \ 199 ((offset & 0x0fffff) << 1)) 200 201 /* For two 32-bit registers used a 64-bit register, the first 202 registernumber needs to be even. Otherwise we trap. */ 203 static inline void generate_trap(DisasContext *ctx, int class, int tin); 204 #define CHECK_REG_PAIR(reg) do { \ 205 if (reg & 0x1) { \ 206 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_OPD); \ 207 } \ 208 } while (0) 209 210 /* Functions for load/save to/from memory */ 211 212 static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2, 213 int16_t con, MemOp mop) 214 { 215 TCGv temp = tcg_temp_new(); 216 tcg_gen_addi_tl(temp, r2, con); 217 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop); 218 } 219 220 static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2, 221 int16_t con, MemOp mop) 222 { 223 TCGv temp = tcg_temp_new(); 224 tcg_gen_addi_tl(temp, r2, con); 225 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop); 226 } 227 228 static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx) 229 { 230 TCGv_i64 temp = tcg_temp_new_i64(); 231 232 tcg_gen_concat_i32_i64(temp, rl, rh); 233 tcg_gen_qemu_st_i64(temp, address, ctx->mem_idx, MO_LEUQ); 234 } 235 236 static void gen_offset_st_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con, 237 DisasContext *ctx) 238 { 239 TCGv temp = tcg_temp_new(); 240 tcg_gen_addi_tl(temp, base, con); 241 gen_st_2regs_64(rh, rl, temp, ctx); 242 } 243 244 static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx) 245 { 246 TCGv_i64 temp = tcg_temp_new_i64(); 247 248 tcg_gen_qemu_ld_i64(temp, address, ctx->mem_idx, MO_LEUQ); 249 /* write back to two 32 bit regs */ 250 tcg_gen_extr_i64_i32(rl, rh, temp); 251 } 252 253 static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con, 254 DisasContext *ctx) 255 { 256 TCGv temp = tcg_temp_new(); 257 tcg_gen_addi_tl(temp, base, con); 258 gen_ld_2regs_64(rh, rl, temp, ctx); 259 } 260 261 static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off, 262 MemOp mop) 263 { 264 TCGv temp = tcg_temp_new(); 265 tcg_gen_addi_tl(temp, r2, off); 266 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop); 267 tcg_gen_mov_tl(r2, temp); 268 } 269 270 static void gen_ld_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off, 271 MemOp mop) 272 { 273 TCGv temp = tcg_temp_new(); 274 tcg_gen_addi_tl(temp, r2, off); 275 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop); 276 tcg_gen_mov_tl(r2, temp); 277 } 278 279 /* M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32]); */ 280 static void gen_ldmst(DisasContext *ctx, int ereg, TCGv ea) 281 { 282 TCGv temp = tcg_temp_new(); 283 TCGv temp2 = tcg_temp_new(); 284 285 CHECK_REG_PAIR(ereg); 286 /* temp = (M(EA, word) */ 287 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); 288 /* temp = temp & ~E[a][63:32]) */ 289 tcg_gen_andc_tl(temp, temp, cpu_gpr_d[ereg+1]); 290 /* temp2 = (E[a][31:0] & E[a][63:32]); */ 291 tcg_gen_and_tl(temp2, cpu_gpr_d[ereg], cpu_gpr_d[ereg+1]); 292 /* temp = temp | temp2; */ 293 tcg_gen_or_tl(temp, temp, temp2); 294 /* M(EA, word) = temp; */ 295 tcg_gen_qemu_st_tl(temp, ea, ctx->mem_idx, MO_LEUL); 296 } 297 298 /* tmp = M(EA, word); 299 M(EA, word) = D[a]; 300 D[a] = tmp[31:0];*/ 301 static void gen_swap(DisasContext *ctx, int reg, TCGv ea) 302 { 303 TCGv temp = tcg_temp_new(); 304 305 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); 306 tcg_gen_qemu_st_tl(cpu_gpr_d[reg], ea, ctx->mem_idx, MO_LEUL); 307 tcg_gen_mov_tl(cpu_gpr_d[reg], temp); 308 } 309 310 static void gen_cmpswap(DisasContext *ctx, int reg, TCGv ea) 311 { 312 TCGv temp = tcg_temp_new(); 313 TCGv temp2 = tcg_temp_new(); 314 CHECK_REG_PAIR(reg); 315 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); 316 tcg_gen_movcond_tl(TCG_COND_EQ, temp2, cpu_gpr_d[reg+1], temp, 317 cpu_gpr_d[reg], temp); 318 tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL); 319 tcg_gen_mov_tl(cpu_gpr_d[reg], temp); 320 } 321 322 static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea) 323 { 324 TCGv temp = tcg_temp_new(); 325 TCGv temp2 = tcg_temp_new(); 326 TCGv temp3 = tcg_temp_new(); 327 CHECK_REG_PAIR(reg); 328 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); 329 tcg_gen_and_tl(temp2, cpu_gpr_d[reg], cpu_gpr_d[reg+1]); 330 tcg_gen_andc_tl(temp3, temp, cpu_gpr_d[reg+1]); 331 tcg_gen_or_tl(temp2, temp2, temp3); 332 tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL); 333 tcg_gen_mov_tl(cpu_gpr_d[reg], temp); 334 } 335 336 /* We generate loads and store to core special function register (csfr) through 337 the function gen_mfcr and gen_mtcr. To handle access permissions, we use 3 338 macros R, A and E, which allow read-only, all and endinit protected access. 339 These macros also specify in which ISA version the csfr was introduced. */ 340 #define R(ADDRESS, REG, FEATURE) \ 341 case ADDRESS: \ 342 if (has_feature(ctx, FEATURE)) { \ 343 tcg_gen_ld_tl(ret, tcg_env, offsetof(CPUTriCoreState, REG)); \ 344 } \ 345 break; 346 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) 347 #define E(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) 348 static inline void gen_mfcr(DisasContext *ctx, TCGv ret, int32_t offset) 349 { 350 /* since we're caching PSW make this a special case */ 351 if (offset == 0xfe04) { 352 gen_helper_psw_read(ret, tcg_env); 353 } else { 354 switch (offset) { 355 #include "csfr.h.inc" 356 } 357 } 358 } 359 #undef R 360 #undef A 361 #undef E 362 363 #define R(ADDRESS, REG, FEATURE) /* don't gen writes to read-only reg, 364 since no exception occurs */ 365 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \ 366 case ADDRESS: \ 367 if (has_feature(ctx, FEATURE)) { \ 368 tcg_gen_st_tl(r1, tcg_env, offsetof(CPUTriCoreState, REG)); \ 369 } \ 370 break; 371 /* Endinit protected registers 372 TODO: Since the endinit bit is in a register of a not yet implemented 373 watchdog device, we handle endinit protected registers like 374 all-access registers for now. */ 375 #define E(ADDRESS, REG, FEATURE) A(ADDRESS, REG, FEATURE) 376 static inline void gen_mtcr(DisasContext *ctx, TCGv r1, 377 int32_t offset) 378 { 379 if (ctx->priv == TRICORE_PRIV_SM) { 380 /* since we're caching PSW make this a special case */ 381 if (offset == 0xfe04) { 382 gen_helper_psw_write(tcg_env, r1); 383 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 384 } else { 385 switch (offset) { 386 #include "csfr.h.inc" 387 } 388 } 389 } else { 390 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); 391 } 392 } 393 394 /* Functions for arithmetic instructions */ 395 396 static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2) 397 { 398 TCGv t0 = tcg_temp_new_i32(); 399 TCGv result = tcg_temp_new_i32(); 400 /* Addition and set V/SV bits */ 401 tcg_gen_add_tl(result, r1, r2); 402 /* calc V bit */ 403 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 404 tcg_gen_xor_tl(t0, r1, r2); 405 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0); 406 /* Calc SV bit */ 407 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 408 /* Calc AV/SAV bits */ 409 tcg_gen_add_tl(cpu_PSW_AV, result, result); 410 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 411 /* calc SAV */ 412 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 413 /* write back result */ 414 tcg_gen_mov_tl(ret, result); 415 } 416 417 static inline void 418 gen_add64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2) 419 { 420 TCGv temp = tcg_temp_new(); 421 TCGv_i64 t0 = tcg_temp_new_i64(); 422 TCGv_i64 t1 = tcg_temp_new_i64(); 423 TCGv_i64 result = tcg_temp_new_i64(); 424 425 tcg_gen_add_i64(result, r1, r2); 426 /* calc v bit */ 427 tcg_gen_xor_i64(t1, result, r1); 428 tcg_gen_xor_i64(t0, r1, r2); 429 tcg_gen_andc_i64(t1, t1, t0); 430 tcg_gen_extrh_i64_i32(cpu_PSW_V, t1); 431 /* calc SV bit */ 432 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 433 /* calc AV/SAV bits */ 434 tcg_gen_extrh_i64_i32(temp, result); 435 tcg_gen_add_tl(cpu_PSW_AV, temp, temp); 436 tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV); 437 /* calc SAV */ 438 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 439 /* write back result */ 440 tcg_gen_mov_i64(ret, result); 441 } 442 443 static inline void 444 gen_addsub64_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 445 TCGv r3, void(*op1)(TCGv, TCGv, TCGv), 446 void(*op2)(TCGv, TCGv, TCGv)) 447 { 448 TCGv temp = tcg_temp_new(); 449 TCGv temp2 = tcg_temp_new(); 450 TCGv temp3 = tcg_temp_new(); 451 TCGv temp4 = tcg_temp_new(); 452 453 (*op1)(temp, r1_low, r2); 454 /* calc V0 bit */ 455 tcg_gen_xor_tl(temp2, temp, r1_low); 456 tcg_gen_xor_tl(temp3, r1_low, r2); 457 if (op1 == tcg_gen_add_tl) { 458 tcg_gen_andc_tl(temp2, temp2, temp3); 459 } else { 460 tcg_gen_and_tl(temp2, temp2, temp3); 461 } 462 463 (*op2)(temp3, r1_high, r3); 464 /* calc V1 bit */ 465 tcg_gen_xor_tl(cpu_PSW_V, temp3, r1_high); 466 tcg_gen_xor_tl(temp4, r1_high, r3); 467 if (op2 == tcg_gen_add_tl) { 468 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, temp4); 469 } else { 470 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp4); 471 } 472 /* combine V0/V1 bits */ 473 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp2); 474 /* calc sv bit */ 475 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 476 /* write result */ 477 tcg_gen_mov_tl(ret_low, temp); 478 tcg_gen_mov_tl(ret_high, temp3); 479 /* calc AV bit */ 480 tcg_gen_add_tl(temp, ret_low, ret_low); 481 tcg_gen_xor_tl(temp, temp, ret_low); 482 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 483 tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, ret_high); 484 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp); 485 /* calc SAV bit */ 486 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 487 } 488 489 /* ret = r2 + (r1 * r3); */ 490 static inline void gen_madd32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3) 491 { 492 TCGv_i64 t1 = tcg_temp_new_i64(); 493 TCGv_i64 t2 = tcg_temp_new_i64(); 494 TCGv_i64 t3 = tcg_temp_new_i64(); 495 496 tcg_gen_ext_i32_i64(t1, r1); 497 tcg_gen_ext_i32_i64(t2, r2); 498 tcg_gen_ext_i32_i64(t3, r3); 499 500 tcg_gen_mul_i64(t1, t1, t3); 501 tcg_gen_add_i64(t1, t2, t1); 502 503 tcg_gen_extrl_i64_i32(ret, t1); 504 /* calc V 505 t1 > 0x7fffffff */ 506 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); 507 /* t1 < -0x80000000 */ 508 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); 509 tcg_gen_or_i64(t2, t2, t3); 510 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2); 511 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 512 /* Calc SV bit */ 513 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 514 /* Calc AV/SAV bits */ 515 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 516 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 517 /* calc SAV */ 518 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 519 } 520 521 static inline void gen_maddi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con) 522 { 523 TCGv temp = tcg_constant_i32(con); 524 gen_madd32_d(ret, r1, r2, temp); 525 } 526 527 static inline void 528 gen_madd64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 529 TCGv r3) 530 { 531 TCGv t1 = tcg_temp_new(); 532 TCGv t2 = tcg_temp_new(); 533 TCGv t3 = tcg_temp_new(); 534 TCGv t4 = tcg_temp_new(); 535 536 tcg_gen_muls2_tl(t1, t2, r1, r3); 537 /* only the add can overflow */ 538 tcg_gen_add2_tl(t3, t4, r2_low, r2_high, t1, t2); 539 /* calc V bit */ 540 tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high); 541 tcg_gen_xor_tl(t1, r2_high, t2); 542 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t1); 543 /* Calc SV bit */ 544 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 545 /* Calc AV/SAV bits */ 546 tcg_gen_add_tl(cpu_PSW_AV, t4, t4); 547 tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV); 548 /* calc SAV */ 549 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 550 /* write back the result */ 551 tcg_gen_mov_tl(ret_low, t3); 552 tcg_gen_mov_tl(ret_high, t4); 553 } 554 555 static inline void 556 gen_maddu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 557 TCGv r3) 558 { 559 TCGv_i64 t1 = tcg_temp_new_i64(); 560 TCGv_i64 t2 = tcg_temp_new_i64(); 561 TCGv_i64 t3 = tcg_temp_new_i64(); 562 563 tcg_gen_extu_i32_i64(t1, r1); 564 tcg_gen_concat_i32_i64(t2, r2_low, r2_high); 565 tcg_gen_extu_i32_i64(t3, r3); 566 567 tcg_gen_mul_i64(t1, t1, t3); 568 tcg_gen_add_i64(t2, t2, t1); 569 /* write back result */ 570 tcg_gen_extr_i64_i32(ret_low, ret_high, t2); 571 /* only the add overflows, if t2 < t1 572 calc V bit */ 573 tcg_gen_setcond_i64(TCG_COND_LTU, t2, t2, t1); 574 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2); 575 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 576 /* Calc SV bit */ 577 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 578 /* Calc AV/SAV bits */ 579 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 580 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); 581 /* calc SAV */ 582 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 583 } 584 585 static inline void 586 gen_maddi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 587 int32_t con) 588 { 589 TCGv temp = tcg_constant_i32(con); 590 gen_madd64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); 591 } 592 593 static inline void 594 gen_maddui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 595 int32_t con) 596 { 597 TCGv temp = tcg_constant_i32(con); 598 gen_maddu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); 599 } 600 601 static inline void 602 gen_madd_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 603 TCGv r3, uint32_t n, uint32_t mode) 604 { 605 TCGv t_n = tcg_constant_i32(n); 606 TCGv temp = tcg_temp_new(); 607 TCGv temp2 = tcg_temp_new(); 608 TCGv_i64 temp64 = tcg_temp_new_i64(); 609 switch (mode) { 610 case MODE_LL: 611 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 612 break; 613 case MODE_LU: 614 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 615 break; 616 case MODE_UL: 617 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 618 break; 619 case MODE_UU: 620 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 621 break; 622 } 623 tcg_gen_extr_i64_i32(temp, temp2, temp64); 624 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, 625 tcg_gen_add_tl, tcg_gen_add_tl); 626 } 627 628 static inline void 629 gen_maddsu_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 630 TCGv r3, uint32_t n, uint32_t mode) 631 { 632 TCGv t_n = tcg_constant_i32(n); 633 TCGv temp = tcg_temp_new(); 634 TCGv temp2 = tcg_temp_new(); 635 TCGv_i64 temp64 = tcg_temp_new_i64(); 636 switch (mode) { 637 case MODE_LL: 638 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 639 break; 640 case MODE_LU: 641 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 642 break; 643 case MODE_UL: 644 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 645 break; 646 case MODE_UU: 647 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 648 break; 649 } 650 tcg_gen_extr_i64_i32(temp, temp2, temp64); 651 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, 652 tcg_gen_sub_tl, tcg_gen_add_tl); 653 } 654 655 static inline void 656 gen_maddsum_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 657 TCGv r3, uint32_t n, uint32_t mode) 658 { 659 TCGv t_n = tcg_constant_i32(n); 660 TCGv_i64 temp64 = tcg_temp_new_i64(); 661 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 662 TCGv_i64 temp64_3 = tcg_temp_new_i64(); 663 switch (mode) { 664 case MODE_LL: 665 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 666 break; 667 case MODE_LU: 668 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 669 break; 670 case MODE_UL: 671 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 672 break; 673 case MODE_UU: 674 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 675 break; 676 } 677 tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high); 678 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ 679 tcg_gen_ext32s_i64(temp64, temp64); /* low */ 680 tcg_gen_sub_i64(temp64, temp64_2, temp64); 681 tcg_gen_shli_i64(temp64, temp64, 16); 682 683 gen_add64_d(temp64_2, temp64_3, temp64); 684 /* write back result */ 685 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2); 686 } 687 688 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2); 689 690 static inline void 691 gen_madds_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 692 TCGv r3, uint32_t n, uint32_t mode) 693 { 694 TCGv t_n = tcg_constant_i32(n); 695 TCGv temp = tcg_temp_new(); 696 TCGv temp2 = tcg_temp_new(); 697 TCGv temp3 = tcg_temp_new(); 698 TCGv_i64 temp64 = tcg_temp_new_i64(); 699 700 switch (mode) { 701 case MODE_LL: 702 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 703 break; 704 case MODE_LU: 705 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 706 break; 707 case MODE_UL: 708 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 709 break; 710 case MODE_UU: 711 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 712 break; 713 } 714 tcg_gen_extr_i64_i32(temp, temp2, temp64); 715 gen_adds(ret_low, r1_low, temp); 716 tcg_gen_mov_tl(temp, cpu_PSW_V); 717 tcg_gen_mov_tl(temp3, cpu_PSW_AV); 718 gen_adds(ret_high, r1_high, temp2); 719 /* combine v bits */ 720 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); 721 /* combine av bits */ 722 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); 723 } 724 725 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2); 726 727 static inline void 728 gen_maddsus_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 729 TCGv r3, uint32_t n, uint32_t mode) 730 { 731 TCGv t_n = tcg_constant_i32(n); 732 TCGv temp = tcg_temp_new(); 733 TCGv temp2 = tcg_temp_new(); 734 TCGv temp3 = tcg_temp_new(); 735 TCGv_i64 temp64 = tcg_temp_new_i64(); 736 737 switch (mode) { 738 case MODE_LL: 739 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 740 break; 741 case MODE_LU: 742 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 743 break; 744 case MODE_UL: 745 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 746 break; 747 case MODE_UU: 748 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 749 break; 750 } 751 tcg_gen_extr_i64_i32(temp, temp2, temp64); 752 gen_subs(ret_low, r1_low, temp); 753 tcg_gen_mov_tl(temp, cpu_PSW_V); 754 tcg_gen_mov_tl(temp3, cpu_PSW_AV); 755 gen_adds(ret_high, r1_high, temp2); 756 /* combine v bits */ 757 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); 758 /* combine av bits */ 759 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); 760 } 761 762 static inline void 763 gen_maddsums_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 764 TCGv r3, uint32_t n, uint32_t mode) 765 { 766 TCGv t_n = tcg_constant_i32(n); 767 TCGv_i64 temp64 = tcg_temp_new_i64(); 768 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 769 770 switch (mode) { 771 case MODE_LL: 772 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 773 break; 774 case MODE_LU: 775 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 776 break; 777 case MODE_UL: 778 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 779 break; 780 case MODE_UU: 781 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 782 break; 783 } 784 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ 785 tcg_gen_ext32s_i64(temp64, temp64); /* low */ 786 tcg_gen_sub_i64(temp64, temp64_2, temp64); 787 tcg_gen_shli_i64(temp64, temp64, 16); 788 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 789 790 gen_helper_add64_ssov(temp64, tcg_env, temp64_2, temp64); 791 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 792 } 793 794 795 static inline void 796 gen_maddm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 797 TCGv r3, uint32_t n, uint32_t mode) 798 { 799 TCGv t_n = tcg_constant_i32(n); 800 TCGv_i64 temp64 = tcg_temp_new_i64(); 801 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 802 TCGv_i64 temp64_3 = tcg_temp_new_i64(); 803 switch (mode) { 804 case MODE_LL: 805 GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n); 806 break; 807 case MODE_LU: 808 GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n); 809 break; 810 case MODE_UL: 811 GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n); 812 break; 813 case MODE_UU: 814 GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n); 815 break; 816 } 817 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 818 gen_add64_d(temp64_3, temp64_2, temp64); 819 /* write back result */ 820 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3); 821 } 822 823 static inline void 824 gen_maddms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 825 TCGv r3, uint32_t n, uint32_t mode) 826 { 827 TCGv t_n = tcg_constant_i32(n); 828 TCGv_i64 temp64 = tcg_temp_new_i64(); 829 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 830 switch (mode) { 831 case MODE_LL: 832 GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n); 833 break; 834 case MODE_LU: 835 GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n); 836 break; 837 case MODE_UL: 838 GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n); 839 break; 840 case MODE_UU: 841 GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n); 842 break; 843 } 844 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 845 gen_helper_add64_ssov(temp64, tcg_env, temp64_2, temp64); 846 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 847 } 848 849 static inline void 850 gen_maddr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, 851 uint32_t mode) 852 { 853 TCGv t_n = tcg_constant_i32(n); 854 TCGv_i64 temp64 = tcg_temp_new_i64(); 855 switch (mode) { 856 case MODE_LL: 857 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 858 break; 859 case MODE_LU: 860 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 861 break; 862 case MODE_UL: 863 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 864 break; 865 case MODE_UU: 866 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 867 break; 868 } 869 gen_helper_addr_h(ret, tcg_env, temp64, r1_low, r1_high); 870 } 871 872 static inline void 873 gen_maddr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 874 { 875 TCGv temp = tcg_temp_new(); 876 TCGv temp2 = tcg_temp_new(); 877 878 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 879 tcg_gen_shli_tl(temp, r1, 16); 880 gen_maddr64_h(ret, temp, temp2, r2, r3, n, mode); 881 } 882 883 static inline void 884 gen_maddsur32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 885 { 886 TCGv t_n = tcg_constant_i32(n); 887 TCGv temp = tcg_temp_new(); 888 TCGv temp2 = tcg_temp_new(); 889 TCGv_i64 temp64 = tcg_temp_new_i64(); 890 switch (mode) { 891 case MODE_LL: 892 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 893 break; 894 case MODE_LU: 895 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 896 break; 897 case MODE_UL: 898 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 899 break; 900 case MODE_UU: 901 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 902 break; 903 } 904 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 905 tcg_gen_shli_tl(temp, r1, 16); 906 gen_helper_addsur_h(ret, tcg_env, temp64, temp, temp2); 907 } 908 909 910 static inline void 911 gen_maddr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, 912 uint32_t n, uint32_t mode) 913 { 914 TCGv t_n = tcg_constant_i32(n); 915 TCGv_i64 temp64 = tcg_temp_new_i64(); 916 switch (mode) { 917 case MODE_LL: 918 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 919 break; 920 case MODE_LU: 921 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 922 break; 923 case MODE_UL: 924 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 925 break; 926 case MODE_UU: 927 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 928 break; 929 } 930 gen_helper_addr_h_ssov(ret, tcg_env, temp64, r1_low, r1_high); 931 } 932 933 static inline void 934 gen_maddr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 935 { 936 TCGv temp = tcg_temp_new(); 937 TCGv temp2 = tcg_temp_new(); 938 939 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 940 tcg_gen_shli_tl(temp, r1, 16); 941 gen_maddr64s_h(ret, temp, temp2, r2, r3, n, mode); 942 } 943 944 static inline void 945 gen_maddsur32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 946 { 947 TCGv t_n = tcg_constant_i32(n); 948 TCGv temp = tcg_temp_new(); 949 TCGv temp2 = tcg_temp_new(); 950 TCGv_i64 temp64 = tcg_temp_new_i64(); 951 switch (mode) { 952 case MODE_LL: 953 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 954 break; 955 case MODE_LU: 956 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 957 break; 958 case MODE_UL: 959 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 960 break; 961 case MODE_UU: 962 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 963 break; 964 } 965 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 966 tcg_gen_shli_tl(temp, r1, 16); 967 gen_helper_addsur_h_ssov(ret, tcg_env, temp64, temp, temp2); 968 } 969 970 static inline void 971 gen_maddr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) 972 { 973 TCGv t_n = tcg_constant_i32(n); 974 gen_helper_maddr_q(ret, tcg_env, r1, r2, r3, t_n); 975 } 976 977 static inline void 978 gen_maddrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) 979 { 980 TCGv t_n = tcg_constant_i32(n); 981 gen_helper_maddr_q_ssov(ret, tcg_env, r1, r2, r3, t_n); 982 } 983 984 static inline void 985 gen_madd32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, 986 uint32_t up_shift) 987 { 988 TCGv temp = tcg_temp_new(); 989 TCGv temp2 = tcg_temp_new(); 990 TCGv temp3 = tcg_temp_new(); 991 TCGv_i64 t1 = tcg_temp_new_i64(); 992 TCGv_i64 t2 = tcg_temp_new_i64(); 993 TCGv_i64 t3 = tcg_temp_new_i64(); 994 995 tcg_gen_ext_i32_i64(t2, arg2); 996 tcg_gen_ext_i32_i64(t3, arg3); 997 998 tcg_gen_mul_i64(t2, t2, t3); 999 tcg_gen_shli_i64(t2, t2, n); 1000 1001 tcg_gen_ext_i32_i64(t1, arg1); 1002 tcg_gen_sari_i64(t2, t2, up_shift); 1003 1004 tcg_gen_add_i64(t3, t1, t2); 1005 tcg_gen_extrl_i64_i32(temp3, t3); 1006 /* calc v bit */ 1007 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); 1008 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); 1009 tcg_gen_or_i64(t1, t1, t2); 1010 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1); 1011 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 1012 /* We produce an overflow on the host if the mul before was 1013 (0x80000000 * 0x80000000) << 1). If this is the 1014 case, we negate the ovf. */ 1015 if (n == 1) { 1016 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000); 1017 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3); 1018 tcg_gen_and_tl(temp, temp, temp2); 1019 tcg_gen_shli_tl(temp, temp, 31); 1020 /* negate v bit, if special condition */ 1021 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); 1022 } 1023 /* Calc SV bit */ 1024 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1025 /* Calc AV/SAV bits */ 1026 tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3); 1027 tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV); 1028 /* calc SAV */ 1029 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1030 /* write back result */ 1031 tcg_gen_mov_tl(ret, temp3); 1032 } 1033 1034 static inline void 1035 gen_m16add32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) 1036 { 1037 TCGv temp = tcg_temp_new(); 1038 TCGv temp2 = tcg_temp_new(); 1039 if (n == 0) { 1040 tcg_gen_mul_tl(temp, arg2, arg3); 1041 } else { /* n is expected to be 1 */ 1042 tcg_gen_mul_tl(temp, arg2, arg3); 1043 tcg_gen_shli_tl(temp, temp, 1); 1044 /* catch special case r1 = r2 = 0x8000 */ 1045 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1046 tcg_gen_sub_tl(temp, temp, temp2); 1047 } 1048 gen_add_d(ret, arg1, temp); 1049 } 1050 1051 static inline void 1052 gen_m16adds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) 1053 { 1054 TCGv temp = tcg_temp_new(); 1055 TCGv temp2 = tcg_temp_new(); 1056 if (n == 0) { 1057 tcg_gen_mul_tl(temp, arg2, arg3); 1058 } else { /* n is expected to be 1 */ 1059 tcg_gen_mul_tl(temp, arg2, arg3); 1060 tcg_gen_shli_tl(temp, temp, 1); 1061 /* catch special case r1 = r2 = 0x8000 */ 1062 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1063 tcg_gen_sub_tl(temp, temp, temp2); 1064 } 1065 gen_adds(ret, arg1, temp); 1066 } 1067 1068 static inline void 1069 gen_m16add64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1070 TCGv arg3, uint32_t n) 1071 { 1072 TCGv temp = tcg_temp_new(); 1073 TCGv temp2 = tcg_temp_new(); 1074 TCGv_i64 t1 = tcg_temp_new_i64(); 1075 TCGv_i64 t2 = tcg_temp_new_i64(); 1076 TCGv_i64 t3 = tcg_temp_new_i64(); 1077 1078 if (n == 0) { 1079 tcg_gen_mul_tl(temp, arg2, arg3); 1080 } else { /* n is expected to be 1 */ 1081 tcg_gen_mul_tl(temp, arg2, arg3); 1082 tcg_gen_shli_tl(temp, temp, 1); 1083 /* catch special case r1 = r2 = 0x8000 */ 1084 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1085 tcg_gen_sub_tl(temp, temp, temp2); 1086 } 1087 tcg_gen_ext_i32_i64(t2, temp); 1088 tcg_gen_shli_i64(t2, t2, 16); 1089 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1090 gen_add64_d(t3, t1, t2); 1091 /* write back result */ 1092 tcg_gen_extr_i64_i32(rl, rh, t3); 1093 } 1094 1095 static inline void 1096 gen_m16adds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1097 TCGv arg3, uint32_t n) 1098 { 1099 TCGv temp = tcg_temp_new(); 1100 TCGv temp2 = tcg_temp_new(); 1101 TCGv_i64 t1 = tcg_temp_new_i64(); 1102 TCGv_i64 t2 = tcg_temp_new_i64(); 1103 1104 if (n == 0) { 1105 tcg_gen_mul_tl(temp, arg2, arg3); 1106 } else { /* n is expected to be 1 */ 1107 tcg_gen_mul_tl(temp, arg2, arg3); 1108 tcg_gen_shli_tl(temp, temp, 1); 1109 /* catch special case r1 = r2 = 0x8000 */ 1110 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1111 tcg_gen_sub_tl(temp, temp, temp2); 1112 } 1113 tcg_gen_ext_i32_i64(t2, temp); 1114 tcg_gen_shli_i64(t2, t2, 16); 1115 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1116 1117 gen_helper_add64_ssov(t1, tcg_env, t1, t2); 1118 tcg_gen_extr_i64_i32(rl, rh, t1); 1119 } 1120 1121 static inline void 1122 gen_madd64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1123 TCGv arg3, uint32_t n) 1124 { 1125 TCGv_i64 t1 = tcg_temp_new_i64(); 1126 TCGv_i64 t2 = tcg_temp_new_i64(); 1127 TCGv_i64 t3 = tcg_temp_new_i64(); 1128 TCGv_i64 t4 = tcg_temp_new_i64(); 1129 TCGv temp, temp2; 1130 1131 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1132 tcg_gen_ext_i32_i64(t2, arg2); 1133 tcg_gen_ext_i32_i64(t3, arg3); 1134 1135 tcg_gen_mul_i64(t2, t2, t3); 1136 if (n != 0) { 1137 tcg_gen_shli_i64(t2, t2, 1); 1138 } 1139 tcg_gen_add_i64(t4, t1, t2); 1140 /* calc v bit */ 1141 tcg_gen_xor_i64(t3, t4, t1); 1142 tcg_gen_xor_i64(t2, t1, t2); 1143 tcg_gen_andc_i64(t3, t3, t2); 1144 tcg_gen_extrh_i64_i32(cpu_PSW_V, t3); 1145 /* We produce an overflow on the host if the mul before was 1146 (0x80000000 * 0x80000000) << 1). If this is the 1147 case, we negate the ovf. */ 1148 if (n == 1) { 1149 temp = tcg_temp_new(); 1150 temp2 = tcg_temp_new(); 1151 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000); 1152 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3); 1153 tcg_gen_and_tl(temp, temp, temp2); 1154 tcg_gen_shli_tl(temp, temp, 31); 1155 /* negate v bit, if special condition */ 1156 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); 1157 } 1158 /* write back result */ 1159 tcg_gen_extr_i64_i32(rl, rh, t4); 1160 /* Calc SV bit */ 1161 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1162 /* Calc AV/SAV bits */ 1163 tcg_gen_add_tl(cpu_PSW_AV, rh, rh); 1164 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV); 1165 /* calc SAV */ 1166 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1167 } 1168 1169 static inline void 1170 gen_madds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, 1171 uint32_t up_shift) 1172 { 1173 TCGv_i64 t1 = tcg_temp_new_i64(); 1174 TCGv_i64 t2 = tcg_temp_new_i64(); 1175 TCGv_i64 t3 = tcg_temp_new_i64(); 1176 1177 tcg_gen_ext_i32_i64(t1, arg1); 1178 tcg_gen_ext_i32_i64(t2, arg2); 1179 tcg_gen_ext_i32_i64(t3, arg3); 1180 1181 tcg_gen_mul_i64(t2, t2, t3); 1182 tcg_gen_sari_i64(t2, t2, up_shift - n); 1183 1184 gen_helper_madd32_q_add_ssov(ret, tcg_env, t1, t2); 1185 } 1186 1187 static inline void 1188 gen_madds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1189 TCGv arg3, uint32_t n) 1190 { 1191 TCGv_i64 r1 = tcg_temp_new_i64(); 1192 TCGv t_n = tcg_constant_i32(n); 1193 1194 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high); 1195 gen_helper_madd64_q_ssov(r1, tcg_env, r1, arg2, arg3, t_n); 1196 tcg_gen_extr_i64_i32(rl, rh, r1); 1197 } 1198 1199 /* ret = r2 - (r1 * r3); */ 1200 static inline void gen_msub32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3) 1201 { 1202 TCGv_i64 t1 = tcg_temp_new_i64(); 1203 TCGv_i64 t2 = tcg_temp_new_i64(); 1204 TCGv_i64 t3 = tcg_temp_new_i64(); 1205 1206 tcg_gen_ext_i32_i64(t1, r1); 1207 tcg_gen_ext_i32_i64(t2, r2); 1208 tcg_gen_ext_i32_i64(t3, r3); 1209 1210 tcg_gen_mul_i64(t1, t1, t3); 1211 tcg_gen_sub_i64(t1, t2, t1); 1212 1213 tcg_gen_extrl_i64_i32(ret, t1); 1214 /* calc V 1215 t2 > 0x7fffffff */ 1216 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); 1217 /* result < -0x80000000 */ 1218 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); 1219 tcg_gen_or_i64(t2, t2, t3); 1220 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2); 1221 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 1222 1223 /* Calc SV bit */ 1224 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1225 /* Calc AV/SAV bits */ 1226 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 1227 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 1228 /* calc SAV */ 1229 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1230 } 1231 1232 static inline void gen_msubi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con) 1233 { 1234 TCGv temp = tcg_constant_i32(con); 1235 gen_msub32_d(ret, r1, r2, temp); 1236 } 1237 1238 static inline void 1239 gen_msub64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 1240 TCGv r3) 1241 { 1242 TCGv t1 = tcg_temp_new(); 1243 TCGv t2 = tcg_temp_new(); 1244 TCGv t3 = tcg_temp_new(); 1245 TCGv t4 = tcg_temp_new(); 1246 1247 tcg_gen_muls2_tl(t1, t2, r1, r3); 1248 /* only the sub can overflow */ 1249 tcg_gen_sub2_tl(t3, t4, r2_low, r2_high, t1, t2); 1250 /* calc V bit */ 1251 tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high); 1252 tcg_gen_xor_tl(t1, r2_high, t2); 1253 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, t1); 1254 /* Calc SV bit */ 1255 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1256 /* Calc AV/SAV bits */ 1257 tcg_gen_add_tl(cpu_PSW_AV, t4, t4); 1258 tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV); 1259 /* calc SAV */ 1260 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1261 /* write back the result */ 1262 tcg_gen_mov_tl(ret_low, t3); 1263 tcg_gen_mov_tl(ret_high, t4); 1264 } 1265 1266 static inline void 1267 gen_msubi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 1268 int32_t con) 1269 { 1270 TCGv temp = tcg_constant_i32(con); 1271 gen_msub64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); 1272 } 1273 1274 static inline void 1275 gen_msubu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 1276 TCGv r3) 1277 { 1278 TCGv_i64 t1 = tcg_temp_new_i64(); 1279 TCGv_i64 t2 = tcg_temp_new_i64(); 1280 TCGv_i64 t3 = tcg_temp_new_i64(); 1281 1282 tcg_gen_extu_i32_i64(t1, r1); 1283 tcg_gen_concat_i32_i64(t2, r2_low, r2_high); 1284 tcg_gen_extu_i32_i64(t3, r3); 1285 1286 tcg_gen_mul_i64(t1, t1, t3); 1287 tcg_gen_sub_i64(t3, t2, t1); 1288 tcg_gen_extr_i64_i32(ret_low, ret_high, t3); 1289 /* calc V bit, only the sub can overflow, if t1 > t2 */ 1290 tcg_gen_setcond_i64(TCG_COND_GTU, t1, t1, t2); 1291 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1); 1292 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 1293 /* Calc SV bit */ 1294 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1295 /* Calc AV/SAV bits */ 1296 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 1297 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); 1298 /* calc SAV */ 1299 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1300 } 1301 1302 static inline void 1303 gen_msubui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 1304 int32_t con) 1305 { 1306 TCGv temp = tcg_constant_i32(con); 1307 gen_msubu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); 1308 } 1309 1310 static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2) 1311 { 1312 TCGv temp = tcg_constant_i32(r2); 1313 gen_add_d(ret, r1, temp); 1314 } 1315 1316 /* calculate the carry bit too */ 1317 static inline void gen_add_CC(TCGv ret, TCGv r1, TCGv r2) 1318 { 1319 TCGv t0 = tcg_temp_new_i32(); 1320 TCGv result = tcg_temp_new_i32(); 1321 1322 tcg_gen_movi_tl(t0, 0); 1323 /* Addition and set C/V/SV bits */ 1324 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, r2, t0); 1325 /* calc V bit */ 1326 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 1327 tcg_gen_xor_tl(t0, r1, r2); 1328 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0); 1329 /* Calc SV bit */ 1330 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1331 /* Calc AV/SAV bits */ 1332 tcg_gen_add_tl(cpu_PSW_AV, result, result); 1333 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 1334 /* calc SAV */ 1335 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1336 /* write back result */ 1337 tcg_gen_mov_tl(ret, result); 1338 } 1339 1340 static inline void gen_addi_CC(TCGv ret, TCGv r1, int32_t con) 1341 { 1342 TCGv temp = tcg_constant_i32(con); 1343 gen_add_CC(ret, r1, temp); 1344 } 1345 1346 static inline void gen_addc_CC(TCGv ret, TCGv r1, TCGv r2) 1347 { 1348 TCGv t0 = tcg_temp_new_i32(); 1349 TCGv result = tcg_temp_new_i32(); 1350 1351 /* Addition, carry and set C/V/SV bits */ 1352 tcg_gen_addcio_i32(result, cpu_PSW_C, r1, r2, cpu_PSW_C); 1353 /* calc V bit */ 1354 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 1355 tcg_gen_xor_tl(t0, r1, r2); 1356 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0); 1357 /* Calc SV bit */ 1358 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1359 /* Calc AV/SAV bits */ 1360 tcg_gen_add_tl(cpu_PSW_AV, result, result); 1361 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 1362 /* calc SAV */ 1363 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1364 /* write back result */ 1365 tcg_gen_mov_tl(ret, result); 1366 } 1367 1368 static inline void gen_addci_CC(TCGv ret, TCGv r1, int32_t con) 1369 { 1370 TCGv temp = tcg_constant_i32(con); 1371 gen_addc_CC(ret, r1, temp); 1372 } 1373 1374 static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3, 1375 TCGv r4) 1376 { 1377 TCGv temp = tcg_temp_new(); 1378 TCGv temp2 = tcg_temp_new(); 1379 TCGv result = tcg_temp_new(); 1380 TCGv mask = tcg_temp_new(); 1381 TCGv t0 = tcg_constant_i32(0); 1382 1383 /* create mask for sticky bits */ 1384 tcg_gen_setcond_tl(cond, mask, r4, t0); 1385 tcg_gen_shli_tl(mask, mask, 31); 1386 1387 tcg_gen_add_tl(result, r1, r2); 1388 /* Calc PSW_V */ 1389 tcg_gen_xor_tl(temp, result, r1); 1390 tcg_gen_xor_tl(temp2, r1, r2); 1391 tcg_gen_andc_tl(temp, temp, temp2); 1392 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V); 1393 /* Set PSW_SV */ 1394 tcg_gen_and_tl(temp, temp, mask); 1395 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV); 1396 /* calc AV bit */ 1397 tcg_gen_add_tl(temp, result, result); 1398 tcg_gen_xor_tl(temp, temp, result); 1399 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV); 1400 /* calc SAV bit */ 1401 tcg_gen_and_tl(temp, temp, mask); 1402 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV); 1403 /* write back result */ 1404 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1); 1405 } 1406 1407 static inline void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2, 1408 TCGv r3, TCGv r4) 1409 { 1410 TCGv temp = tcg_constant_i32(r2); 1411 gen_cond_add(cond, r1, temp, r3, r4); 1412 } 1413 1414 static inline void gen_sub_d(TCGv ret, TCGv r1, TCGv r2) 1415 { 1416 TCGv temp = tcg_temp_new_i32(); 1417 TCGv result = tcg_temp_new_i32(); 1418 1419 tcg_gen_sub_tl(result, r1, r2); 1420 /* calc V bit */ 1421 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 1422 tcg_gen_xor_tl(temp, r1, r2); 1423 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp); 1424 /* calc SV bit */ 1425 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1426 /* Calc AV bit */ 1427 tcg_gen_add_tl(cpu_PSW_AV, result, result); 1428 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 1429 /* calc SAV bit */ 1430 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1431 /* write back result */ 1432 tcg_gen_mov_tl(ret, result); 1433 } 1434 1435 static inline void 1436 gen_sub64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2) 1437 { 1438 TCGv temp = tcg_temp_new(); 1439 TCGv_i64 t0 = tcg_temp_new_i64(); 1440 TCGv_i64 t1 = tcg_temp_new_i64(); 1441 TCGv_i64 result = tcg_temp_new_i64(); 1442 1443 tcg_gen_sub_i64(result, r1, r2); 1444 /* calc v bit */ 1445 tcg_gen_xor_i64(t1, result, r1); 1446 tcg_gen_xor_i64(t0, r1, r2); 1447 tcg_gen_and_i64(t1, t1, t0); 1448 tcg_gen_extrh_i64_i32(cpu_PSW_V, t1); 1449 /* calc SV bit */ 1450 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1451 /* calc AV/SAV bits */ 1452 tcg_gen_extrh_i64_i32(temp, result); 1453 tcg_gen_add_tl(cpu_PSW_AV, temp, temp); 1454 tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV); 1455 /* calc SAV */ 1456 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1457 /* write back result */ 1458 tcg_gen_mov_i64(ret, result); 1459 } 1460 1461 static inline void gen_sub_CC(TCGv ret, TCGv r1, TCGv r2) 1462 { 1463 TCGv result = tcg_temp_new(); 1464 TCGv temp = tcg_temp_new(); 1465 1466 tcg_gen_sub_tl(result, r1, r2); 1467 /* calc C bit */ 1468 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_PSW_C, r1, r2); 1469 /* calc V bit */ 1470 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 1471 tcg_gen_xor_tl(temp, r1, r2); 1472 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp); 1473 /* calc SV bit */ 1474 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1475 /* Calc AV bit */ 1476 tcg_gen_add_tl(cpu_PSW_AV, result, result); 1477 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 1478 /* calc SAV bit */ 1479 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1480 /* write back result */ 1481 tcg_gen_mov_tl(ret, result); 1482 } 1483 1484 static inline void gen_subc_CC(TCGv ret, TCGv r1, TCGv r2) 1485 { 1486 TCGv temp = tcg_temp_new(); 1487 tcg_gen_not_tl(temp, r2); 1488 gen_addc_CC(ret, r1, temp); 1489 } 1490 1491 static inline void gen_cond_sub(TCGCond cond, TCGv r1, TCGv r2, TCGv r3, 1492 TCGv r4) 1493 { 1494 TCGv temp = tcg_temp_new(); 1495 TCGv temp2 = tcg_temp_new(); 1496 TCGv result = tcg_temp_new(); 1497 TCGv mask = tcg_temp_new(); 1498 TCGv t0 = tcg_constant_i32(0); 1499 1500 /* create mask for sticky bits */ 1501 tcg_gen_setcond_tl(cond, mask, r4, t0); 1502 tcg_gen_shli_tl(mask, mask, 31); 1503 1504 tcg_gen_sub_tl(result, r1, r2); 1505 /* Calc PSW_V */ 1506 tcg_gen_xor_tl(temp, result, r1); 1507 tcg_gen_xor_tl(temp2, r1, r2); 1508 tcg_gen_and_tl(temp, temp, temp2); 1509 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V); 1510 /* Set PSW_SV */ 1511 tcg_gen_and_tl(temp, temp, mask); 1512 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV); 1513 /* calc AV bit */ 1514 tcg_gen_add_tl(temp, result, result); 1515 tcg_gen_xor_tl(temp, temp, result); 1516 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV); 1517 /* calc SAV bit */ 1518 tcg_gen_and_tl(temp, temp, mask); 1519 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV); 1520 /* write back result */ 1521 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1); 1522 } 1523 1524 static inline void 1525 gen_msub_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1526 TCGv r3, uint32_t n, uint32_t mode) 1527 { 1528 TCGv t_n = tcg_constant_i32(n); 1529 TCGv temp = tcg_temp_new(); 1530 TCGv temp2 = tcg_temp_new(); 1531 TCGv_i64 temp64 = tcg_temp_new_i64(); 1532 switch (mode) { 1533 case MODE_LL: 1534 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 1535 break; 1536 case MODE_LU: 1537 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 1538 break; 1539 case MODE_UL: 1540 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 1541 break; 1542 case MODE_UU: 1543 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 1544 break; 1545 } 1546 tcg_gen_extr_i64_i32(temp, temp2, temp64); 1547 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, 1548 tcg_gen_sub_tl, tcg_gen_sub_tl); 1549 } 1550 1551 static inline void 1552 gen_msubs_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1553 TCGv r3, uint32_t n, uint32_t mode) 1554 { 1555 TCGv t_n = tcg_constant_i32(n); 1556 TCGv temp = tcg_temp_new(); 1557 TCGv temp2 = tcg_temp_new(); 1558 TCGv temp3 = tcg_temp_new(); 1559 TCGv_i64 temp64 = tcg_temp_new_i64(); 1560 1561 switch (mode) { 1562 case MODE_LL: 1563 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 1564 break; 1565 case MODE_LU: 1566 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 1567 break; 1568 case MODE_UL: 1569 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 1570 break; 1571 case MODE_UU: 1572 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 1573 break; 1574 } 1575 tcg_gen_extr_i64_i32(temp, temp2, temp64); 1576 gen_subs(ret_low, r1_low, temp); 1577 tcg_gen_mov_tl(temp, cpu_PSW_V); 1578 tcg_gen_mov_tl(temp3, cpu_PSW_AV); 1579 gen_subs(ret_high, r1_high, temp2); 1580 /* combine v bits */ 1581 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); 1582 /* combine av bits */ 1583 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); 1584 } 1585 1586 static inline void 1587 gen_msubm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1588 TCGv r3, uint32_t n, uint32_t mode) 1589 { 1590 TCGv t_n = tcg_constant_i32(n); 1591 TCGv_i64 temp64 = tcg_temp_new_i64(); 1592 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 1593 TCGv_i64 temp64_3 = tcg_temp_new_i64(); 1594 switch (mode) { 1595 case MODE_LL: 1596 GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n); 1597 break; 1598 case MODE_LU: 1599 GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n); 1600 break; 1601 case MODE_UL: 1602 GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n); 1603 break; 1604 case MODE_UU: 1605 GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n); 1606 break; 1607 } 1608 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 1609 gen_sub64_d(temp64_3, temp64_2, temp64); 1610 /* write back result */ 1611 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3); 1612 } 1613 1614 static inline void 1615 gen_msubms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1616 TCGv r3, uint32_t n, uint32_t mode) 1617 { 1618 TCGv t_n = tcg_constant_i32(n); 1619 TCGv_i64 temp64 = tcg_temp_new_i64(); 1620 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 1621 switch (mode) { 1622 case MODE_LL: 1623 GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n); 1624 break; 1625 case MODE_LU: 1626 GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n); 1627 break; 1628 case MODE_UL: 1629 GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n); 1630 break; 1631 case MODE_UU: 1632 GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n); 1633 break; 1634 } 1635 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 1636 gen_helper_sub64_ssov(temp64, tcg_env, temp64_2, temp64); 1637 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 1638 } 1639 1640 static inline void 1641 gen_msubr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, 1642 uint32_t mode) 1643 { 1644 TCGv t_n = tcg_constant_i32(n); 1645 TCGv_i64 temp64 = tcg_temp_new_i64(); 1646 switch (mode) { 1647 case MODE_LL: 1648 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 1649 break; 1650 case MODE_LU: 1651 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 1652 break; 1653 case MODE_UL: 1654 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 1655 break; 1656 case MODE_UU: 1657 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 1658 break; 1659 } 1660 gen_helper_subr_h(ret, tcg_env, temp64, r1_low, r1_high); 1661 } 1662 1663 static inline void 1664 gen_msubr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 1665 { 1666 TCGv temp = tcg_temp_new(); 1667 TCGv temp2 = tcg_temp_new(); 1668 1669 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 1670 tcg_gen_shli_tl(temp, r1, 16); 1671 gen_msubr64_h(ret, temp, temp2, r2, r3, n, mode); 1672 } 1673 1674 static inline void 1675 gen_msubr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, 1676 uint32_t n, uint32_t mode) 1677 { 1678 TCGv t_n = tcg_constant_i32(n); 1679 TCGv_i64 temp64 = tcg_temp_new_i64(); 1680 switch (mode) { 1681 case MODE_LL: 1682 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 1683 break; 1684 case MODE_LU: 1685 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 1686 break; 1687 case MODE_UL: 1688 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 1689 break; 1690 case MODE_UU: 1691 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 1692 break; 1693 } 1694 gen_helper_subr_h_ssov(ret, tcg_env, temp64, r1_low, r1_high); 1695 } 1696 1697 static inline void 1698 gen_msubr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 1699 { 1700 TCGv temp = tcg_temp_new(); 1701 TCGv temp2 = tcg_temp_new(); 1702 1703 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 1704 tcg_gen_shli_tl(temp, r1, 16); 1705 gen_msubr64s_h(ret, temp, temp2, r2, r3, n, mode); 1706 } 1707 1708 static inline void 1709 gen_msubr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) 1710 { 1711 TCGv temp = tcg_constant_i32(n); 1712 gen_helper_msubr_q(ret, tcg_env, r1, r2, r3, temp); 1713 } 1714 1715 static inline void 1716 gen_msubrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) 1717 { 1718 TCGv temp = tcg_constant_i32(n); 1719 gen_helper_msubr_q_ssov(ret, tcg_env, r1, r2, r3, temp); 1720 } 1721 1722 static inline void 1723 gen_msub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, 1724 uint32_t up_shift) 1725 { 1726 TCGv temp3 = tcg_temp_new(); 1727 TCGv_i64 t1 = tcg_temp_new_i64(); 1728 TCGv_i64 t2 = tcg_temp_new_i64(); 1729 TCGv_i64 t3 = tcg_temp_new_i64(); 1730 TCGv_i64 t4 = tcg_temp_new_i64(); 1731 1732 tcg_gen_ext_i32_i64(t2, arg2); 1733 tcg_gen_ext_i32_i64(t3, arg3); 1734 1735 tcg_gen_mul_i64(t2, t2, t3); 1736 1737 tcg_gen_ext_i32_i64(t1, arg1); 1738 /* if we shift part of the fraction out, we need to round up */ 1739 tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1); 1740 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); 1741 tcg_gen_sari_i64(t2, t2, up_shift - n); 1742 tcg_gen_add_i64(t2, t2, t4); 1743 1744 tcg_gen_sub_i64(t3, t1, t2); 1745 tcg_gen_extrl_i64_i32(temp3, t3); 1746 /* calc v bit */ 1747 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); 1748 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); 1749 tcg_gen_or_i64(t1, t1, t2); 1750 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1); 1751 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 1752 /* Calc SV bit */ 1753 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1754 /* Calc AV/SAV bits */ 1755 tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3); 1756 tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV); 1757 /* calc SAV */ 1758 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1759 /* write back result */ 1760 tcg_gen_mov_tl(ret, temp3); 1761 } 1762 1763 static inline void 1764 gen_m16sub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) 1765 { 1766 TCGv temp = tcg_temp_new(); 1767 TCGv temp2 = tcg_temp_new(); 1768 if (n == 0) { 1769 tcg_gen_mul_tl(temp, arg2, arg3); 1770 } else { /* n is expected to be 1 */ 1771 tcg_gen_mul_tl(temp, arg2, arg3); 1772 tcg_gen_shli_tl(temp, temp, 1); 1773 /* catch special case r1 = r2 = 0x8000 */ 1774 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1775 tcg_gen_sub_tl(temp, temp, temp2); 1776 } 1777 gen_sub_d(ret, arg1, temp); 1778 } 1779 1780 static inline void 1781 gen_m16subs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) 1782 { 1783 TCGv temp = tcg_temp_new(); 1784 TCGv temp2 = tcg_temp_new(); 1785 if (n == 0) { 1786 tcg_gen_mul_tl(temp, arg2, arg3); 1787 } else { /* n is expected to be 1 */ 1788 tcg_gen_mul_tl(temp, arg2, arg3); 1789 tcg_gen_shli_tl(temp, temp, 1); 1790 /* catch special case r1 = r2 = 0x8000 */ 1791 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1792 tcg_gen_sub_tl(temp, temp, temp2); 1793 } 1794 gen_subs(ret, arg1, temp); 1795 } 1796 1797 static inline void 1798 gen_m16sub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1799 TCGv arg3, uint32_t n) 1800 { 1801 TCGv temp = tcg_temp_new(); 1802 TCGv temp2 = tcg_temp_new(); 1803 TCGv_i64 t1 = tcg_temp_new_i64(); 1804 TCGv_i64 t2 = tcg_temp_new_i64(); 1805 TCGv_i64 t3 = tcg_temp_new_i64(); 1806 1807 if (n == 0) { 1808 tcg_gen_mul_tl(temp, arg2, arg3); 1809 } else { /* n is expected to be 1 */ 1810 tcg_gen_mul_tl(temp, arg2, arg3); 1811 tcg_gen_shli_tl(temp, temp, 1); 1812 /* catch special case r1 = r2 = 0x8000 */ 1813 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1814 tcg_gen_sub_tl(temp, temp, temp2); 1815 } 1816 tcg_gen_ext_i32_i64(t2, temp); 1817 tcg_gen_shli_i64(t2, t2, 16); 1818 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1819 gen_sub64_d(t3, t1, t2); 1820 /* write back result */ 1821 tcg_gen_extr_i64_i32(rl, rh, t3); 1822 } 1823 1824 static inline void 1825 gen_m16subs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1826 TCGv arg3, uint32_t n) 1827 { 1828 TCGv temp = tcg_temp_new(); 1829 TCGv temp2 = tcg_temp_new(); 1830 TCGv_i64 t1 = tcg_temp_new_i64(); 1831 TCGv_i64 t2 = tcg_temp_new_i64(); 1832 1833 if (n == 0) { 1834 tcg_gen_mul_tl(temp, arg2, arg3); 1835 } else { /* n is expected to be 1 */ 1836 tcg_gen_mul_tl(temp, arg2, arg3); 1837 tcg_gen_shli_tl(temp, temp, 1); 1838 /* catch special case r1 = r2 = 0x8000 */ 1839 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1840 tcg_gen_sub_tl(temp, temp, temp2); 1841 } 1842 tcg_gen_ext_i32_i64(t2, temp); 1843 tcg_gen_shli_i64(t2, t2, 16); 1844 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1845 1846 gen_helper_sub64_ssov(t1, tcg_env, t1, t2); 1847 tcg_gen_extr_i64_i32(rl, rh, t1); 1848 } 1849 1850 static inline void 1851 gen_msub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1852 TCGv arg3, uint32_t n) 1853 { 1854 TCGv_i64 t1 = tcg_temp_new_i64(); 1855 TCGv_i64 t2 = tcg_temp_new_i64(); 1856 TCGv_i64 t3 = tcg_temp_new_i64(); 1857 TCGv_i64 t4 = tcg_temp_new_i64(); 1858 TCGv temp, temp2; 1859 1860 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1861 tcg_gen_ext_i32_i64(t2, arg2); 1862 tcg_gen_ext_i32_i64(t3, arg3); 1863 1864 tcg_gen_mul_i64(t2, t2, t3); 1865 if (n != 0) { 1866 tcg_gen_shli_i64(t2, t2, 1); 1867 } 1868 tcg_gen_sub_i64(t4, t1, t2); 1869 /* calc v bit */ 1870 tcg_gen_xor_i64(t3, t4, t1); 1871 tcg_gen_xor_i64(t2, t1, t2); 1872 tcg_gen_and_i64(t3, t3, t2); 1873 tcg_gen_extrh_i64_i32(cpu_PSW_V, t3); 1874 /* We produce an overflow on the host if the mul before was 1875 (0x80000000 * 0x80000000) << 1). If this is the 1876 case, we negate the ovf. */ 1877 if (n == 1) { 1878 temp = tcg_temp_new(); 1879 temp2 = tcg_temp_new(); 1880 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000); 1881 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3); 1882 tcg_gen_and_tl(temp, temp, temp2); 1883 tcg_gen_shli_tl(temp, temp, 31); 1884 /* negate v bit, if special condition */ 1885 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); 1886 } 1887 /* write back result */ 1888 tcg_gen_extr_i64_i32(rl, rh, t4); 1889 /* Calc SV bit */ 1890 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1891 /* Calc AV/SAV bits */ 1892 tcg_gen_add_tl(cpu_PSW_AV, rh, rh); 1893 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV); 1894 /* calc SAV */ 1895 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1896 } 1897 1898 static inline void 1899 gen_msubs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, 1900 uint32_t up_shift) 1901 { 1902 TCGv_i64 t1 = tcg_temp_new_i64(); 1903 TCGv_i64 t2 = tcg_temp_new_i64(); 1904 TCGv_i64 t3 = tcg_temp_new_i64(); 1905 TCGv_i64 t4 = tcg_temp_new_i64(); 1906 1907 tcg_gen_ext_i32_i64(t1, arg1); 1908 tcg_gen_ext_i32_i64(t2, arg2); 1909 tcg_gen_ext_i32_i64(t3, arg3); 1910 1911 tcg_gen_mul_i64(t2, t2, t3); 1912 /* if we shift part of the fraction out, we need to round up */ 1913 tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1); 1914 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); 1915 tcg_gen_sari_i64(t3, t2, up_shift - n); 1916 tcg_gen_add_i64(t3, t3, t4); 1917 1918 gen_helper_msub32_q_sub_ssov(ret, tcg_env, t1, t3); 1919 } 1920 1921 static inline void 1922 gen_msubs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1923 TCGv arg3, uint32_t n) 1924 { 1925 TCGv_i64 r1 = tcg_temp_new_i64(); 1926 TCGv t_n = tcg_constant_i32(n); 1927 1928 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high); 1929 gen_helper_msub64_q_ssov(r1, tcg_env, r1, arg2, arg3, t_n); 1930 tcg_gen_extr_i64_i32(rl, rh, r1); 1931 } 1932 1933 static inline void 1934 gen_msubad_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1935 TCGv r3, uint32_t n, uint32_t mode) 1936 { 1937 TCGv t_n = tcg_constant_i32(n); 1938 TCGv temp = tcg_temp_new(); 1939 TCGv temp2 = tcg_temp_new(); 1940 TCGv_i64 temp64 = tcg_temp_new_i64(); 1941 switch (mode) { 1942 case MODE_LL: 1943 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 1944 break; 1945 case MODE_LU: 1946 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 1947 break; 1948 case MODE_UL: 1949 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 1950 break; 1951 case MODE_UU: 1952 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 1953 break; 1954 } 1955 tcg_gen_extr_i64_i32(temp, temp2, temp64); 1956 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, 1957 tcg_gen_add_tl, tcg_gen_sub_tl); 1958 } 1959 1960 static inline void 1961 gen_msubadm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1962 TCGv r3, uint32_t n, uint32_t mode) 1963 { 1964 TCGv t_n = tcg_constant_i32(n); 1965 TCGv_i64 temp64 = tcg_temp_new_i64(); 1966 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 1967 TCGv_i64 temp64_3 = tcg_temp_new_i64(); 1968 switch (mode) { 1969 case MODE_LL: 1970 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 1971 break; 1972 case MODE_LU: 1973 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 1974 break; 1975 case MODE_UL: 1976 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 1977 break; 1978 case MODE_UU: 1979 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 1980 break; 1981 } 1982 tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high); 1983 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ 1984 tcg_gen_ext32s_i64(temp64, temp64); /* low */ 1985 tcg_gen_sub_i64(temp64, temp64_2, temp64); 1986 tcg_gen_shli_i64(temp64, temp64, 16); 1987 1988 gen_sub64_d(temp64_2, temp64_3, temp64); 1989 /* write back result */ 1990 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2); 1991 } 1992 1993 static inline void 1994 gen_msubadr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 1995 { 1996 TCGv t_n = tcg_constant_i32(n); 1997 TCGv temp = tcg_temp_new(); 1998 TCGv temp2 = tcg_temp_new(); 1999 TCGv_i64 temp64 = tcg_temp_new_i64(); 2000 switch (mode) { 2001 case MODE_LL: 2002 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 2003 break; 2004 case MODE_LU: 2005 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 2006 break; 2007 case MODE_UL: 2008 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 2009 break; 2010 case MODE_UU: 2011 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 2012 break; 2013 } 2014 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 2015 tcg_gen_shli_tl(temp, r1, 16); 2016 gen_helper_subadr_h(ret, tcg_env, temp64, temp, temp2); 2017 } 2018 2019 static inline void 2020 gen_msubads_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 2021 TCGv r3, uint32_t n, uint32_t mode) 2022 { 2023 TCGv t_n = tcg_constant_i32(n); 2024 TCGv temp = tcg_temp_new(); 2025 TCGv temp2 = tcg_temp_new(); 2026 TCGv temp3 = tcg_temp_new(); 2027 TCGv_i64 temp64 = tcg_temp_new_i64(); 2028 2029 switch (mode) { 2030 case MODE_LL: 2031 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 2032 break; 2033 case MODE_LU: 2034 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 2035 break; 2036 case MODE_UL: 2037 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 2038 break; 2039 case MODE_UU: 2040 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 2041 break; 2042 } 2043 tcg_gen_extr_i64_i32(temp, temp2, temp64); 2044 gen_adds(ret_low, r1_low, temp); 2045 tcg_gen_mov_tl(temp, cpu_PSW_V); 2046 tcg_gen_mov_tl(temp3, cpu_PSW_AV); 2047 gen_subs(ret_high, r1_high, temp2); 2048 /* combine v bits */ 2049 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); 2050 /* combine av bits */ 2051 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); 2052 } 2053 2054 static inline void 2055 gen_msubadms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 2056 TCGv r3, uint32_t n, uint32_t mode) 2057 { 2058 TCGv t_n = tcg_constant_i32(n); 2059 TCGv_i64 temp64 = tcg_temp_new_i64(); 2060 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 2061 2062 switch (mode) { 2063 case MODE_LL: 2064 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 2065 break; 2066 case MODE_LU: 2067 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 2068 break; 2069 case MODE_UL: 2070 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 2071 break; 2072 case MODE_UU: 2073 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 2074 break; 2075 } 2076 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ 2077 tcg_gen_ext32s_i64(temp64, temp64); /* low */ 2078 tcg_gen_sub_i64(temp64, temp64_2, temp64); 2079 tcg_gen_shli_i64(temp64, temp64, 16); 2080 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 2081 2082 gen_helper_sub64_ssov(temp64, tcg_env, temp64_2, temp64); 2083 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2084 } 2085 2086 static inline void 2087 gen_msubadr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 2088 { 2089 TCGv t_n = tcg_constant_i32(n); 2090 TCGv temp = tcg_temp_new(); 2091 TCGv temp2 = tcg_temp_new(); 2092 TCGv_i64 temp64 = tcg_temp_new_i64(); 2093 switch (mode) { 2094 case MODE_LL: 2095 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 2096 break; 2097 case MODE_LU: 2098 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 2099 break; 2100 case MODE_UL: 2101 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 2102 break; 2103 case MODE_UU: 2104 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 2105 break; 2106 } 2107 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 2108 tcg_gen_shli_tl(temp, r1, 16); 2109 gen_helper_subadr_h_ssov(ret, tcg_env, temp64, temp, temp2); 2110 } 2111 2112 static inline void gen_abs(TCGv ret, TCGv r1) 2113 { 2114 tcg_gen_abs_tl(ret, r1); 2115 /* overflow can only happen, if r1 = 0x80000000 */ 2116 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, r1, 0x80000000); 2117 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 2118 /* calc SV bit */ 2119 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2120 /* Calc AV bit */ 2121 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2122 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2123 /* calc SAV bit */ 2124 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2125 } 2126 2127 static inline void gen_absdif(TCGv ret, TCGv r1, TCGv r2) 2128 { 2129 TCGv temp = tcg_temp_new_i32(); 2130 TCGv result = tcg_temp_new_i32(); 2131 2132 tcg_gen_sub_tl(result, r1, r2); 2133 tcg_gen_sub_tl(temp, r2, r1); 2134 tcg_gen_movcond_tl(TCG_COND_GT, result, r1, r2, result, temp); 2135 2136 /* calc V bit */ 2137 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 2138 tcg_gen_xor_tl(temp, result, r2); 2139 tcg_gen_movcond_tl(TCG_COND_GT, cpu_PSW_V, r1, r2, cpu_PSW_V, temp); 2140 tcg_gen_xor_tl(temp, r1, r2); 2141 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp); 2142 /* calc SV bit */ 2143 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2144 /* Calc AV bit */ 2145 tcg_gen_add_tl(cpu_PSW_AV, result, result); 2146 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 2147 /* calc SAV bit */ 2148 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2149 /* write back result */ 2150 tcg_gen_mov_tl(ret, result); 2151 } 2152 2153 static inline void gen_absdifi(TCGv ret, TCGv r1, int32_t con) 2154 { 2155 TCGv temp = tcg_constant_i32(con); 2156 gen_absdif(ret, r1, temp); 2157 } 2158 2159 static inline void gen_absdifsi(TCGv ret, TCGv r1, int32_t con) 2160 { 2161 TCGv temp = tcg_constant_i32(con); 2162 gen_helper_absdif_ssov(ret, tcg_env, r1, temp); 2163 } 2164 2165 static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2) 2166 { 2167 TCGv high = tcg_temp_new(); 2168 TCGv low = tcg_temp_new(); 2169 2170 tcg_gen_muls2_tl(low, high, r1, r2); 2171 tcg_gen_mov_tl(ret, low); 2172 /* calc V bit */ 2173 tcg_gen_sari_tl(low, low, 31); 2174 tcg_gen_setcond_tl(TCG_COND_NE, cpu_PSW_V, high, low); 2175 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 2176 /* calc SV bit */ 2177 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2178 /* Calc AV bit */ 2179 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2180 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2181 /* calc SAV bit */ 2182 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2183 } 2184 2185 static inline void gen_muli_i32s(TCGv ret, TCGv r1, int32_t con) 2186 { 2187 TCGv temp = tcg_constant_i32(con); 2188 gen_mul_i32s(ret, r1, temp); 2189 } 2190 2191 static inline void gen_mul_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2) 2192 { 2193 tcg_gen_muls2_tl(ret_low, ret_high, r1, r2); 2194 /* clear V bit */ 2195 tcg_gen_movi_tl(cpu_PSW_V, 0); 2196 /* calc SV bit */ 2197 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2198 /* Calc AV bit */ 2199 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 2200 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); 2201 /* calc SAV bit */ 2202 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2203 } 2204 2205 static inline void gen_muli_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, 2206 int32_t con) 2207 { 2208 TCGv temp = tcg_constant_i32(con); 2209 gen_mul_i64s(ret_low, ret_high, r1, temp); 2210 } 2211 2212 static inline void gen_mul_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2) 2213 { 2214 tcg_gen_mulu2_tl(ret_low, ret_high, r1, r2); 2215 /* clear V bit */ 2216 tcg_gen_movi_tl(cpu_PSW_V, 0); 2217 /* calc SV bit */ 2218 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2219 /* Calc AV bit */ 2220 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 2221 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); 2222 /* calc SAV bit */ 2223 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2224 } 2225 2226 static inline void gen_muli_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, 2227 int32_t con) 2228 { 2229 TCGv temp = tcg_constant_i32(con); 2230 gen_mul_i64u(ret_low, ret_high, r1, temp); 2231 } 2232 2233 static inline void gen_mulsi_i32(TCGv ret, TCGv r1, int32_t con) 2234 { 2235 TCGv temp = tcg_constant_i32(con); 2236 gen_helper_mul_ssov(ret, tcg_env, r1, temp); 2237 } 2238 2239 static inline void gen_mulsui_i32(TCGv ret, TCGv r1, int32_t con) 2240 { 2241 TCGv temp = tcg_constant_i32(con); 2242 gen_helper_mul_suov(ret, tcg_env, r1, temp); 2243 } 2244 2245 /* gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); */ 2246 static inline void gen_maddsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) 2247 { 2248 TCGv temp = tcg_constant_i32(con); 2249 gen_helper_madd32_ssov(ret, tcg_env, r1, r2, temp); 2250 } 2251 2252 static inline void gen_maddsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) 2253 { 2254 TCGv temp = tcg_constant_i32(con); 2255 gen_helper_madd32_suov(ret, tcg_env, r1, r2, temp); 2256 } 2257 2258 static void 2259 gen_mul_q(TCGv rl, TCGv rh, TCGv arg1, TCGv arg2, uint32_t n, uint32_t up_shift) 2260 { 2261 TCGv_i64 temp_64 = tcg_temp_new_i64(); 2262 TCGv_i64 temp2_64 = tcg_temp_new_i64(); 2263 2264 if (n == 0) { 2265 if (up_shift == 32) { 2266 tcg_gen_muls2_tl(rh, rl, arg1, arg2); 2267 } else if (up_shift == 16) { 2268 tcg_gen_ext_i32_i64(temp_64, arg1); 2269 tcg_gen_ext_i32_i64(temp2_64, arg2); 2270 2271 tcg_gen_mul_i64(temp_64, temp_64, temp2_64); 2272 tcg_gen_shri_i64(temp_64, temp_64, up_shift); 2273 tcg_gen_extr_i64_i32(rl, rh, temp_64); 2274 } else { 2275 tcg_gen_muls2_tl(rl, rh, arg1, arg2); 2276 } 2277 /* reset v bit */ 2278 tcg_gen_movi_tl(cpu_PSW_V, 0); 2279 } else { /* n is expected to be 1 */ 2280 tcg_gen_ext_i32_i64(temp_64, arg1); 2281 tcg_gen_ext_i32_i64(temp2_64, arg2); 2282 2283 tcg_gen_mul_i64(temp_64, temp_64, temp2_64); 2284 2285 if (up_shift == 0) { 2286 tcg_gen_shli_i64(temp_64, temp_64, 1); 2287 } else { 2288 tcg_gen_shri_i64(temp_64, temp_64, up_shift - 1); 2289 } 2290 tcg_gen_extr_i64_i32(rl, rh, temp_64); 2291 /* overflow only occurs if r1 = r2 = 0x8000 */ 2292 if (up_shift == 0) {/* result is 64 bit */ 2293 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rh, 2294 0x80000000); 2295 } else { /* result is 32 bit */ 2296 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rl, 2297 0x80000000); 2298 } 2299 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 2300 /* calc sv overflow bit */ 2301 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2302 } 2303 /* calc av overflow bit */ 2304 if (up_shift == 0) { 2305 tcg_gen_add_tl(cpu_PSW_AV, rh, rh); 2306 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV); 2307 } else { 2308 tcg_gen_add_tl(cpu_PSW_AV, rl, rl); 2309 tcg_gen_xor_tl(cpu_PSW_AV, rl, cpu_PSW_AV); 2310 } 2311 /* calc sav overflow bit */ 2312 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2313 } 2314 2315 static void 2316 gen_mul_q_16(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n) 2317 { 2318 TCGv temp = tcg_temp_new(); 2319 if (n == 0) { 2320 tcg_gen_mul_tl(ret, arg1, arg2); 2321 } else { /* n is expected to be 1 */ 2322 tcg_gen_mul_tl(ret, arg1, arg2); 2323 tcg_gen_shli_tl(ret, ret, 1); 2324 /* catch special case r1 = r2 = 0x8000 */ 2325 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80000000); 2326 tcg_gen_sub_tl(ret, ret, temp); 2327 } 2328 /* reset v bit */ 2329 tcg_gen_movi_tl(cpu_PSW_V, 0); 2330 /* calc av overflow bit */ 2331 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2332 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2333 /* calc sav overflow bit */ 2334 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2335 } 2336 2337 static void gen_mulr_q(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n) 2338 { 2339 TCGv temp = tcg_temp_new(); 2340 if (n == 0) { 2341 tcg_gen_mul_tl(ret, arg1, arg2); 2342 tcg_gen_addi_tl(ret, ret, 0x8000); 2343 } else { 2344 tcg_gen_mul_tl(ret, arg1, arg2); 2345 tcg_gen_shli_tl(ret, ret, 1); 2346 tcg_gen_addi_tl(ret, ret, 0x8000); 2347 /* catch special case r1 = r2 = 0x8000 */ 2348 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80008000); 2349 tcg_gen_muli_tl(temp, temp, 0x8001); 2350 tcg_gen_sub_tl(ret, ret, temp); 2351 } 2352 /* reset v bit */ 2353 tcg_gen_movi_tl(cpu_PSW_V, 0); 2354 /* calc av overflow bit */ 2355 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2356 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2357 /* calc sav overflow bit */ 2358 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2359 /* cut halfword off */ 2360 tcg_gen_andi_tl(ret, ret, 0xffff0000); 2361 } 2362 2363 static inline void 2364 gen_madds_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2365 TCGv r3) 2366 { 2367 TCGv_i64 temp64 = tcg_temp_new_i64(); 2368 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); 2369 gen_helper_madd64_ssov(temp64, tcg_env, r1, temp64, r3); 2370 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2371 } 2372 2373 static inline void 2374 gen_maddsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2375 int32_t con) 2376 { 2377 TCGv temp = tcg_constant_i32(con); 2378 gen_madds_64(ret_low, ret_high, r1, r2_low, r2_high, temp); 2379 } 2380 2381 static inline void 2382 gen_maddsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2383 TCGv r3) 2384 { 2385 TCGv_i64 temp64 = tcg_temp_new_i64(); 2386 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); 2387 gen_helper_madd64_suov(temp64, tcg_env, r1, temp64, r3); 2388 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2389 } 2390 2391 static inline void 2392 gen_maddsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2393 int32_t con) 2394 { 2395 TCGv temp = tcg_constant_i32(con); 2396 gen_maddsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp); 2397 } 2398 2399 static inline void gen_msubsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) 2400 { 2401 TCGv temp = tcg_constant_i32(con); 2402 gen_helper_msub32_ssov(ret, tcg_env, r1, r2, temp); 2403 } 2404 2405 static inline void gen_msubsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) 2406 { 2407 TCGv temp = tcg_constant_i32(con); 2408 gen_helper_msub32_suov(ret, tcg_env, r1, r2, temp); 2409 } 2410 2411 static inline void 2412 gen_msubs_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2413 TCGv r3) 2414 { 2415 TCGv_i64 temp64 = tcg_temp_new_i64(); 2416 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); 2417 gen_helper_msub64_ssov(temp64, tcg_env, r1, temp64, r3); 2418 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2419 } 2420 2421 static inline void 2422 gen_msubsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2423 int32_t con) 2424 { 2425 TCGv temp = tcg_constant_i32(con); 2426 gen_msubs_64(ret_low, ret_high, r1, r2_low, r2_high, temp); 2427 } 2428 2429 static inline void 2430 gen_msubsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2431 TCGv r3) 2432 { 2433 TCGv_i64 temp64 = tcg_temp_new_i64(); 2434 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); 2435 gen_helper_msub64_suov(temp64, tcg_env, r1, temp64, r3); 2436 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2437 } 2438 2439 static inline void 2440 gen_msubsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2441 int32_t con) 2442 { 2443 TCGv temp = tcg_constant_i32(con); 2444 gen_msubsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp); 2445 } 2446 2447 static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low) 2448 { 2449 tcg_gen_smax_tl(ret, arg, tcg_constant_i32(low)); 2450 tcg_gen_smin_tl(ret, ret, tcg_constant_i32(up)); 2451 } 2452 2453 static void gen_saturate_u(TCGv ret, TCGv arg, int32_t up) 2454 { 2455 tcg_gen_umin_tl(ret, arg, tcg_constant_i32(up)); 2456 } 2457 2458 static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count) 2459 { 2460 if (shift_count == -32) { 2461 tcg_gen_movi_tl(ret, 0); 2462 } else if (shift_count >= 0) { 2463 tcg_gen_shli_tl(ret, r1, shift_count); 2464 } else { 2465 tcg_gen_shri_tl(ret, r1, -shift_count); 2466 } 2467 } 2468 2469 static void gen_sh_hi(TCGv ret, TCGv r1, int32_t shiftcount) 2470 { 2471 TCGv temp_low, temp_high; 2472 2473 if (shiftcount == -16) { 2474 tcg_gen_movi_tl(ret, 0); 2475 } else { 2476 temp_high = tcg_temp_new(); 2477 temp_low = tcg_temp_new(); 2478 2479 tcg_gen_andi_tl(temp_low, r1, 0xffff); 2480 tcg_gen_andi_tl(temp_high, r1, 0xffff0000); 2481 gen_shi(temp_low, temp_low, shiftcount); 2482 gen_shi(ret, temp_high, shiftcount); 2483 tcg_gen_deposit_tl(ret, ret, temp_low, 0, 16); 2484 } 2485 } 2486 2487 static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count) 2488 { 2489 uint32_t msk, msk_start; 2490 TCGv temp = tcg_temp_new(); 2491 TCGv temp2 = tcg_temp_new(); 2492 2493 if (shift_count == 0) { 2494 /* Clear PSW.C and PSW.V */ 2495 tcg_gen_movi_tl(cpu_PSW_C, 0); 2496 tcg_gen_mov_tl(cpu_PSW_V, cpu_PSW_C); 2497 tcg_gen_mov_tl(ret, r1); 2498 } else if (shift_count == -32) { 2499 /* set PSW.C */ 2500 tcg_gen_mov_tl(cpu_PSW_C, r1); 2501 /* fill ret completely with sign bit */ 2502 tcg_gen_sari_tl(ret, r1, 31); 2503 /* clear PSW.V */ 2504 tcg_gen_movi_tl(cpu_PSW_V, 0); 2505 } else if (shift_count > 0) { 2506 TCGv t_max = tcg_constant_i32(0x7FFFFFFF >> shift_count); 2507 TCGv t_min = tcg_constant_i32(((int32_t) -0x80000000) >> shift_count); 2508 2509 /* calc carry */ 2510 msk_start = 32 - shift_count; 2511 msk = ((1 << shift_count) - 1) << msk_start; 2512 tcg_gen_andi_tl(cpu_PSW_C, r1, msk); 2513 /* calc v/sv bits */ 2514 tcg_gen_setcond_tl(TCG_COND_GT, temp, r1, t_max); 2515 tcg_gen_setcond_tl(TCG_COND_LT, temp2, r1, t_min); 2516 tcg_gen_or_tl(cpu_PSW_V, temp, temp2); 2517 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 2518 /* calc sv */ 2519 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_V, cpu_PSW_SV); 2520 /* do shift */ 2521 tcg_gen_shli_tl(ret, r1, shift_count); 2522 } else { 2523 /* clear PSW.V */ 2524 tcg_gen_movi_tl(cpu_PSW_V, 0); 2525 /* calc carry */ 2526 msk = (1 << -shift_count) - 1; 2527 tcg_gen_andi_tl(cpu_PSW_C, r1, msk); 2528 /* do shift */ 2529 tcg_gen_sari_tl(ret, r1, -shift_count); 2530 } 2531 /* calc av overflow bit */ 2532 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2533 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2534 /* calc sav overflow bit */ 2535 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2536 } 2537 2538 static void gen_shas(TCGv ret, TCGv r1, TCGv r2) 2539 { 2540 gen_helper_sha_ssov(ret, tcg_env, r1, r2); 2541 } 2542 2543 static void gen_shasi(TCGv ret, TCGv r1, int32_t con) 2544 { 2545 TCGv temp = tcg_constant_i32(con); 2546 gen_shas(ret, r1, temp); 2547 } 2548 2549 static void gen_sha_hi(TCGv ret, TCGv r1, int32_t shift_count) 2550 { 2551 TCGv low, high; 2552 2553 if (shift_count == 0) { 2554 tcg_gen_mov_tl(ret, r1); 2555 } else if (shift_count > 0) { 2556 low = tcg_temp_new(); 2557 high = tcg_temp_new(); 2558 2559 tcg_gen_andi_tl(high, r1, 0xffff0000); 2560 tcg_gen_shli_tl(low, r1, shift_count); 2561 tcg_gen_shli_tl(ret, high, shift_count); 2562 tcg_gen_deposit_tl(ret, ret, low, 0, 16); 2563 } else { 2564 low = tcg_temp_new(); 2565 high = tcg_temp_new(); 2566 2567 tcg_gen_ext16s_tl(low, r1); 2568 tcg_gen_sari_tl(low, low, -shift_count); 2569 tcg_gen_sari_tl(ret, r1, -shift_count); 2570 tcg_gen_deposit_tl(ret, ret, low, 0, 16); 2571 } 2572 } 2573 2574 /* ret = {ret[30:0], (r1 cond r2)}; */ 2575 static void gen_sh_cond(int cond, TCGv ret, TCGv r1, TCGv r2) 2576 { 2577 TCGv temp = tcg_temp_new(); 2578 TCGv temp2 = tcg_temp_new(); 2579 2580 tcg_gen_shli_tl(temp, ret, 1); 2581 tcg_gen_setcond_tl(cond, temp2, r1, r2); 2582 tcg_gen_or_tl(ret, temp, temp2); 2583 } 2584 2585 static void gen_sh_condi(int cond, TCGv ret, TCGv r1, int32_t con) 2586 { 2587 TCGv temp = tcg_constant_i32(con); 2588 gen_sh_cond(cond, ret, r1, temp); 2589 } 2590 2591 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2) 2592 { 2593 gen_helper_add_ssov(ret, tcg_env, r1, r2); 2594 } 2595 2596 static inline void gen_addsi(TCGv ret, TCGv r1, int32_t con) 2597 { 2598 TCGv temp = tcg_constant_i32(con); 2599 gen_helper_add_ssov(ret, tcg_env, r1, temp); 2600 } 2601 2602 static inline void gen_addsui(TCGv ret, TCGv r1, int32_t con) 2603 { 2604 TCGv temp = tcg_constant_i32(con); 2605 gen_helper_add_suov(ret, tcg_env, r1, temp); 2606 } 2607 2608 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2) 2609 { 2610 gen_helper_sub_ssov(ret, tcg_env, r1, r2); 2611 } 2612 2613 static inline void gen_subsu(TCGv ret, TCGv r1, TCGv r2) 2614 { 2615 gen_helper_sub_suov(ret, tcg_env, r1, r2); 2616 } 2617 2618 static inline void gen_bit_2op(TCGv ret, TCGv r1, TCGv r2, 2619 int pos1, int pos2, 2620 void(*op1)(TCGv, TCGv, TCGv), 2621 void(*op2)(TCGv, TCGv, TCGv)) 2622 { 2623 TCGv temp1, temp2; 2624 2625 temp1 = tcg_temp_new(); 2626 temp2 = tcg_temp_new(); 2627 2628 tcg_gen_shri_tl(temp2, r2, pos2); 2629 tcg_gen_shri_tl(temp1, r1, pos1); 2630 2631 (*op1)(temp1, temp1, temp2); 2632 (*op2)(temp1 , ret, temp1); 2633 2634 tcg_gen_deposit_tl(ret, ret, temp1, 0, 1); 2635 } 2636 2637 /* ret = r1[pos1] op1 r2[pos2]; */ 2638 static inline void gen_bit_1op(TCGv ret, TCGv r1, TCGv r2, 2639 int pos1, int pos2, 2640 void(*op1)(TCGv, TCGv, TCGv)) 2641 { 2642 TCGv temp1, temp2; 2643 2644 temp1 = tcg_temp_new(); 2645 temp2 = tcg_temp_new(); 2646 2647 tcg_gen_shri_tl(temp2, r2, pos2); 2648 tcg_gen_shri_tl(temp1, r1, pos1); 2649 2650 (*op1)(ret, temp1, temp2); 2651 2652 tcg_gen_andi_tl(ret, ret, 0x1); 2653 } 2654 2655 static inline void gen_accumulating_cond(int cond, TCGv ret, TCGv r1, TCGv r2, 2656 void(*op)(TCGv, TCGv, TCGv)) 2657 { 2658 TCGv temp = tcg_temp_new(); 2659 TCGv temp2 = tcg_temp_new(); 2660 /* temp = (arg1 cond arg2 )*/ 2661 tcg_gen_setcond_tl(cond, temp, r1, r2); 2662 /* temp2 = ret[0]*/ 2663 tcg_gen_andi_tl(temp2, ret, 0x1); 2664 /* temp = temp insn temp2 */ 2665 (*op)(temp, temp, temp2); 2666 /* ret = {ret[31:1], temp} */ 2667 tcg_gen_deposit_tl(ret, ret, temp, 0, 1); 2668 } 2669 2670 static inline void 2671 gen_accumulating_condi(int cond, TCGv ret, TCGv r1, int32_t con, 2672 void(*op)(TCGv, TCGv, TCGv)) 2673 { 2674 TCGv temp = tcg_constant_i32(con); 2675 gen_accumulating_cond(cond, ret, r1, temp, op); 2676 } 2677 2678 static inline void gen_eqany_bi(TCGv ret, TCGv r1, int32_t con) 2679 { 2680 TCGv b0 = tcg_temp_new(); 2681 TCGv b1 = tcg_temp_new(); 2682 TCGv b2 = tcg_temp_new(); 2683 TCGv b3 = tcg_temp_new(); 2684 2685 /* byte 0 */ 2686 tcg_gen_andi_tl(b0, r1, 0xff); 2687 tcg_gen_setcondi_tl(TCG_COND_EQ, b0, b0, con & 0xff); 2688 2689 /* byte 1 */ 2690 tcg_gen_andi_tl(b1, r1, 0xff00); 2691 tcg_gen_setcondi_tl(TCG_COND_EQ, b1, b1, con & 0xff00); 2692 2693 /* byte 2 */ 2694 tcg_gen_andi_tl(b2, r1, 0xff0000); 2695 tcg_gen_setcondi_tl(TCG_COND_EQ, b2, b2, con & 0xff0000); 2696 2697 /* byte 3 */ 2698 tcg_gen_andi_tl(b3, r1, 0xff000000); 2699 tcg_gen_setcondi_tl(TCG_COND_EQ, b3, b3, con & 0xff000000); 2700 2701 /* combine them */ 2702 tcg_gen_or_tl(ret, b0, b1); 2703 tcg_gen_or_tl(ret, ret, b2); 2704 tcg_gen_or_tl(ret, ret, b3); 2705 } 2706 2707 static inline void gen_eqany_hi(TCGv ret, TCGv r1, int32_t con) 2708 { 2709 TCGv h0 = tcg_temp_new(); 2710 TCGv h1 = tcg_temp_new(); 2711 2712 /* halfword 0 */ 2713 tcg_gen_andi_tl(h0, r1, 0xffff); 2714 tcg_gen_setcondi_tl(TCG_COND_EQ, h0, h0, con & 0xffff); 2715 2716 /* halfword 1 */ 2717 tcg_gen_andi_tl(h1, r1, 0xffff0000); 2718 tcg_gen_setcondi_tl(TCG_COND_EQ, h1, h1, con & 0xffff0000); 2719 2720 /* combine them */ 2721 tcg_gen_or_tl(ret, h0, h1); 2722 } 2723 2724 /* mask = ((1 << width) -1) << pos; 2725 ret = (r1 & ~mask) | (r2 << pos) & mask); */ 2726 static inline void gen_insert(TCGv ret, TCGv r1, TCGv r2, TCGv width, TCGv pos) 2727 { 2728 TCGv mask = tcg_temp_new(); 2729 TCGv temp = tcg_temp_new(); 2730 TCGv temp2 = tcg_temp_new(); 2731 2732 tcg_gen_shl_tl(mask, tcg_constant_tl(1), width); 2733 tcg_gen_subi_tl(mask, mask, 1); 2734 tcg_gen_shl_tl(mask, mask, pos); 2735 2736 tcg_gen_shl_tl(temp, r2, pos); 2737 tcg_gen_and_tl(temp, temp, mask); 2738 tcg_gen_andc_tl(temp2, r1, mask); 2739 tcg_gen_or_tl(ret, temp, temp2); 2740 } 2741 2742 static inline void gen_bsplit(TCGv rl, TCGv rh, TCGv r1) 2743 { 2744 TCGv_i64 temp = tcg_temp_new_i64(); 2745 2746 gen_helper_bsplit(temp, r1); 2747 tcg_gen_extr_i64_i32(rl, rh, temp); 2748 } 2749 2750 static inline void gen_unpack(TCGv rl, TCGv rh, TCGv r1) 2751 { 2752 TCGv_i64 temp = tcg_temp_new_i64(); 2753 2754 gen_helper_unpack(temp, r1); 2755 tcg_gen_extr_i64_i32(rl, rh, temp); 2756 } 2757 2758 static inline void 2759 gen_dvinit_b(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2) 2760 { 2761 TCGv_i64 ret = tcg_temp_new_i64(); 2762 2763 if (!has_feature(ctx, TRICORE_FEATURE_131)) { 2764 gen_helper_dvinit_b_13(ret, tcg_env, r1, r2); 2765 } else { 2766 gen_helper_dvinit_b_131(ret, tcg_env, r1, r2); 2767 } 2768 tcg_gen_extr_i64_i32(rl, rh, ret); 2769 } 2770 2771 static inline void 2772 gen_dvinit_h(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2) 2773 { 2774 TCGv_i64 ret = tcg_temp_new_i64(); 2775 2776 if (!has_feature(ctx, TRICORE_FEATURE_131)) { 2777 gen_helper_dvinit_h_13(ret, tcg_env, r1, r2); 2778 } else { 2779 gen_helper_dvinit_h_131(ret, tcg_env, r1, r2); 2780 } 2781 tcg_gen_extr_i64_i32(rl, rh, ret); 2782 } 2783 2784 static void gen_calc_usb_mul_h(TCGv arg_low, TCGv arg_high) 2785 { 2786 TCGv temp = tcg_temp_new(); 2787 /* calc AV bit */ 2788 tcg_gen_add_tl(temp, arg_low, arg_low); 2789 tcg_gen_xor_tl(temp, temp, arg_low); 2790 tcg_gen_add_tl(cpu_PSW_AV, arg_high, arg_high); 2791 tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, arg_high); 2792 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp); 2793 /* calc SAV bit */ 2794 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2795 tcg_gen_movi_tl(cpu_PSW_V, 0); 2796 } 2797 2798 static void gen_calc_usb_mulr_h(TCGv arg) 2799 { 2800 TCGv temp = tcg_temp_new(); 2801 /* calc AV bit */ 2802 tcg_gen_add_tl(temp, arg, arg); 2803 tcg_gen_xor_tl(temp, temp, arg); 2804 tcg_gen_shli_tl(cpu_PSW_AV, temp, 16); 2805 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp); 2806 /* calc SAV bit */ 2807 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2808 /* clear V bit */ 2809 tcg_gen_movi_tl(cpu_PSW_V, 0); 2810 } 2811 2812 /* helpers for generating program flow micro-ops */ 2813 2814 static inline void gen_save_pc(target_ulong pc) 2815 { 2816 tcg_gen_movi_tl(cpu_PC, pc); 2817 } 2818 2819 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 2820 { 2821 if (translator_use_goto_tb(&ctx->base, dest)) { 2822 tcg_gen_goto_tb(n); 2823 gen_save_pc(dest); 2824 tcg_gen_exit_tb(ctx->base.tb, n); 2825 } else { 2826 gen_save_pc(dest); 2827 tcg_gen_lookup_and_goto_ptr(); 2828 } 2829 ctx->base.is_jmp = DISAS_NORETURN; 2830 } 2831 2832 static void generate_trap(DisasContext *ctx, int class, int tin) 2833 { 2834 TCGv_i32 classtemp = tcg_constant_i32(class); 2835 TCGv_i32 tintemp = tcg_constant_i32(tin); 2836 2837 gen_save_pc(ctx->base.pc_next); 2838 gen_helper_raise_exception_sync(tcg_env, classtemp, tintemp); 2839 ctx->base.is_jmp = DISAS_NORETURN; 2840 } 2841 2842 static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1, 2843 TCGv r2, int16_t address) 2844 { 2845 TCGLabel *jumpLabel = gen_new_label(); 2846 tcg_gen_brcond_tl(cond, r1, r2, jumpLabel); 2847 2848 gen_goto_tb(ctx, 1, ctx->pc_succ_insn); 2849 2850 gen_set_label(jumpLabel); 2851 gen_goto_tb(ctx, 0, ctx->base.pc_next + address * 2); 2852 } 2853 2854 static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv r1, 2855 int r2, int16_t address) 2856 { 2857 TCGv temp = tcg_constant_i32(r2); 2858 gen_branch_cond(ctx, cond, r1, temp, address); 2859 } 2860 2861 static void gen_loop(DisasContext *ctx, int r1, int32_t offset) 2862 { 2863 TCGLabel *l1 = gen_new_label(); 2864 2865 tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1); 2866 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], -1, l1); 2867 gen_goto_tb(ctx, 1, ctx->base.pc_next + offset); 2868 gen_set_label(l1); 2869 gen_goto_tb(ctx, 0, ctx->pc_succ_insn); 2870 } 2871 2872 static void gen_fcall_save_ctx(DisasContext *ctx) 2873 { 2874 TCGv temp = tcg_temp_new(); 2875 2876 tcg_gen_addi_tl(temp, cpu_gpr_a[10], -4); 2877 tcg_gen_qemu_st_tl(cpu_gpr_a[11], temp, ctx->mem_idx, MO_LESL); 2878 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); 2879 tcg_gen_mov_tl(cpu_gpr_a[10], temp); 2880 } 2881 2882 static void gen_fret(DisasContext *ctx) 2883 { 2884 TCGv temp = tcg_temp_new(); 2885 2886 tcg_gen_andi_tl(temp, cpu_gpr_a[11], ~0x1); 2887 tcg_gen_qemu_ld_tl(cpu_gpr_a[11], cpu_gpr_a[10], ctx->mem_idx, MO_LESL); 2888 tcg_gen_addi_tl(cpu_gpr_a[10], cpu_gpr_a[10], 4); 2889 tcg_gen_mov_tl(cpu_PC, temp); 2890 ctx->base.is_jmp = DISAS_EXIT; 2891 } 2892 2893 static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, 2894 int r2 , int32_t constant , int32_t offset) 2895 { 2896 TCGv temp, temp2; 2897 int n; 2898 2899 switch (opc) { 2900 /* SB-format jumps */ 2901 case OPC1_16_SB_J: 2902 case OPC1_32_B_J: 2903 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); 2904 break; 2905 case OPC1_32_B_CALL: 2906 case OPC1_16_SB_CALL: 2907 gen_helper_1arg(call, ctx->pc_succ_insn); 2908 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); 2909 break; 2910 case OPC1_16_SB_JZ: 2911 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], 0, offset); 2912 break; 2913 case OPC1_16_SB_JNZ: 2914 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 0, offset); 2915 break; 2916 /* SBC-format jumps */ 2917 case OPC1_16_SBC_JEQ: 2918 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset); 2919 break; 2920 case OPC1_16_SBC_JEQ2: 2921 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, 2922 offset + 16); 2923 break; 2924 case OPC1_16_SBC_JNE: 2925 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset); 2926 break; 2927 case OPC1_16_SBC_JNE2: 2928 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 2929 constant, offset + 16); 2930 break; 2931 /* SBRN-format jumps */ 2932 case OPC1_16_SBRN_JZ_T: 2933 temp = tcg_temp_new(); 2934 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant); 2935 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset); 2936 break; 2937 case OPC1_16_SBRN_JNZ_T: 2938 temp = tcg_temp_new(); 2939 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant); 2940 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset); 2941 break; 2942 /* SBR-format jumps */ 2943 case OPC1_16_SBR_JEQ: 2944 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], 2945 offset); 2946 break; 2947 case OPC1_16_SBR_JEQ2: 2948 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], 2949 offset + 16); 2950 break; 2951 case OPC1_16_SBR_JNE: 2952 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], 2953 offset); 2954 break; 2955 case OPC1_16_SBR_JNE2: 2956 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], 2957 offset + 16); 2958 break; 2959 case OPC1_16_SBR_JNZ: 2960 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], 0, offset); 2961 break; 2962 case OPC1_16_SBR_JNZ_A: 2963 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset); 2964 break; 2965 case OPC1_16_SBR_JGEZ: 2966 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], 0, offset); 2967 break; 2968 case OPC1_16_SBR_JGTZ: 2969 gen_branch_condi(ctx, TCG_COND_GT, cpu_gpr_d[r1], 0, offset); 2970 break; 2971 case OPC1_16_SBR_JLEZ: 2972 gen_branch_condi(ctx, TCG_COND_LE, cpu_gpr_d[r1], 0, offset); 2973 break; 2974 case OPC1_16_SBR_JLTZ: 2975 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], 0, offset); 2976 break; 2977 case OPC1_16_SBR_JZ: 2978 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], 0, offset); 2979 break; 2980 case OPC1_16_SBR_JZ_A: 2981 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset); 2982 break; 2983 case OPC1_16_SBR_LOOP: 2984 gen_loop(ctx, r1, offset * 2 - 32); 2985 break; 2986 /* SR-format jumps */ 2987 case OPC1_16_SR_JI: 2988 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], 0xfffffffe); 2989 ctx->base.is_jmp = DISAS_EXIT; 2990 break; 2991 case OPC2_32_SYS_RET: 2992 case OPC2_16_SR_RET: 2993 gen_helper_ret(tcg_env); 2994 ctx->base.is_jmp = DISAS_EXIT; 2995 break; 2996 /* B-format */ 2997 case OPC1_32_B_CALLA: 2998 gen_helper_1arg(call, ctx->pc_succ_insn); 2999 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); 3000 break; 3001 case OPC1_32_B_FCALL: 3002 gen_fcall_save_ctx(ctx); 3003 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); 3004 break; 3005 case OPC1_32_B_FCALLA: 3006 gen_fcall_save_ctx(ctx); 3007 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); 3008 break; 3009 case OPC1_32_B_JLA: 3010 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); 3011 /* fall through */ 3012 case OPC1_32_B_JA: 3013 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); 3014 break; 3015 case OPC1_32_B_JL: 3016 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); 3017 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); 3018 break; 3019 /* BOL format */ 3020 case OPCM_32_BRC_EQ_NEQ: 3021 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JEQ) { 3022 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], constant, offset); 3023 } else { 3024 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], constant, offset); 3025 } 3026 break; 3027 case OPCM_32_BRC_GE: 3028 if (MASK_OP_BRC_OP2(ctx->opcode) == OP2_32_BRC_JGE) { 3029 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], constant, offset); 3030 } else { 3031 constant = MASK_OP_BRC_CONST4(ctx->opcode); 3032 gen_branch_condi(ctx, TCG_COND_GEU, cpu_gpr_d[r1], constant, 3033 offset); 3034 } 3035 break; 3036 case OPCM_32_BRC_JLT: 3037 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JLT) { 3038 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], constant, offset); 3039 } else { 3040 constant = MASK_OP_BRC_CONST4(ctx->opcode); 3041 gen_branch_condi(ctx, TCG_COND_LTU, cpu_gpr_d[r1], constant, 3042 offset); 3043 } 3044 break; 3045 case OPCM_32_BRC_JNE: 3046 temp = tcg_temp_new(); 3047 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JNED) { 3048 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 3049 /* subi is unconditional */ 3050 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); 3051 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset); 3052 } else { 3053 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 3054 /* addi is unconditional */ 3055 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); 3056 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset); 3057 } 3058 break; 3059 /* BRN format */ 3060 case OPCM_32_BRN_JTT: 3061 n = MASK_OP_BRN_N(ctx->opcode); 3062 3063 temp = tcg_temp_new(); 3064 tcg_gen_andi_tl(temp, cpu_gpr_d[r1], (1 << n)); 3065 3066 if (MASK_OP_BRN_OP2(ctx->opcode) == OPC2_32_BRN_JNZ_T) { 3067 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset); 3068 } else { 3069 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset); 3070 } 3071 break; 3072 /* BRR Format */ 3073 case OPCM_32_BRR_EQ_NEQ: 3074 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ) { 3075 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], 3076 offset); 3077 } else { 3078 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], 3079 offset); 3080 } 3081 break; 3082 case OPCM_32_BRR_ADDR_EQ_NEQ: 3083 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ_A) { 3084 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_a[r1], cpu_gpr_a[r2], 3085 offset); 3086 } else { 3087 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_a[r1], cpu_gpr_a[r2], 3088 offset); 3089 } 3090 break; 3091 case OPCM_32_BRR_GE: 3092 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JGE) { 3093 gen_branch_cond(ctx, TCG_COND_GE, cpu_gpr_d[r1], cpu_gpr_d[r2], 3094 offset); 3095 } else { 3096 gen_branch_cond(ctx, TCG_COND_GEU, cpu_gpr_d[r1], cpu_gpr_d[r2], 3097 offset); 3098 } 3099 break; 3100 case OPCM_32_BRR_JLT: 3101 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JLT) { 3102 gen_branch_cond(ctx, TCG_COND_LT, cpu_gpr_d[r1], cpu_gpr_d[r2], 3103 offset); 3104 } else { 3105 gen_branch_cond(ctx, TCG_COND_LTU, cpu_gpr_d[r1], cpu_gpr_d[r2], 3106 offset); 3107 } 3108 break; 3109 case OPCM_32_BRR_LOOP: 3110 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_LOOP) { 3111 gen_loop(ctx, r2, offset * 2); 3112 } else { 3113 /* OPC2_32_BRR_LOOPU */ 3114 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); 3115 } 3116 break; 3117 case OPCM_32_BRR_JNE: 3118 temp = tcg_temp_new(); 3119 temp2 = tcg_temp_new(); 3120 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRR_JNED) { 3121 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 3122 /* also save r2, in case of r1 == r2, so r2 is not decremented */ 3123 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]); 3124 /* subi is unconditional */ 3125 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); 3126 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset); 3127 } else { 3128 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 3129 /* also save r2, in case of r1 == r2, so r2 is not decremented */ 3130 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]); 3131 /* addi is unconditional */ 3132 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); 3133 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset); 3134 } 3135 break; 3136 case OPCM_32_BRR_JNZ: 3137 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JNZ_A) { 3138 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset); 3139 } else { 3140 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset); 3141 } 3142 break; 3143 default: 3144 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3145 } 3146 } 3147 3148 3149 /* 3150 * Functions for decoding instructions 3151 */ 3152 3153 static void decode_src_opc(DisasContext *ctx, int op1) 3154 { 3155 int r1; 3156 int32_t const4; 3157 TCGv temp, temp2; 3158 3159 r1 = MASK_OP_SRC_S1D(ctx->opcode); 3160 const4 = MASK_OP_SRC_CONST4_SEXT(ctx->opcode); 3161 3162 switch (op1) { 3163 case OPC1_16_SRC_ADD: 3164 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); 3165 break; 3166 case OPC1_16_SRC_ADD_A15: 3167 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[15], const4); 3168 break; 3169 case OPC1_16_SRC_ADD_15A: 3170 gen_addi_d(cpu_gpr_d[15], cpu_gpr_d[r1], const4); 3171 break; 3172 case OPC1_16_SRC_ADD_A: 3173 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], const4); 3174 break; 3175 case OPC1_16_SRC_CADD: 3176 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const4, cpu_gpr_d[r1], 3177 cpu_gpr_d[15]); 3178 break; 3179 case OPC1_16_SRC_CADDN: 3180 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const4, cpu_gpr_d[r1], 3181 cpu_gpr_d[15]); 3182 break; 3183 case OPC1_16_SRC_CMOV: 3184 temp = tcg_constant_tl(0); 3185 temp2 = tcg_constant_tl(const4); 3186 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp, 3187 temp2, cpu_gpr_d[r1]); 3188 break; 3189 case OPC1_16_SRC_CMOVN: 3190 temp = tcg_constant_tl(0); 3191 temp2 = tcg_constant_tl(const4); 3192 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp, 3193 temp2, cpu_gpr_d[r1]); 3194 break; 3195 case OPC1_16_SRC_EQ: 3196 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1], 3197 const4); 3198 break; 3199 case OPC1_16_SRC_LT: 3200 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1], 3201 const4); 3202 break; 3203 case OPC1_16_SRC_MOV: 3204 tcg_gen_movi_tl(cpu_gpr_d[r1], const4); 3205 break; 3206 case OPC1_16_SRC_MOV_A: 3207 const4 = MASK_OP_SRC_CONST4(ctx->opcode); 3208 tcg_gen_movi_tl(cpu_gpr_a[r1], const4); 3209 break; 3210 case OPC1_16_SRC_MOV_E: 3211 if (has_feature(ctx, TRICORE_FEATURE_16)) { 3212 CHECK_REG_PAIR(r1); 3213 tcg_gen_movi_tl(cpu_gpr_d[r1], const4); 3214 tcg_gen_sari_tl(cpu_gpr_d[r1+1], cpu_gpr_d[r1], 31); 3215 } else { 3216 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3217 } 3218 break; 3219 case OPC1_16_SRC_SH: 3220 gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); 3221 break; 3222 case OPC1_16_SRC_SHA: 3223 gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); 3224 break; 3225 default: 3226 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3227 } 3228 } 3229 3230 static void decode_srr_opc(DisasContext *ctx, int op1) 3231 { 3232 int r1, r2; 3233 TCGv temp; 3234 3235 r1 = MASK_OP_SRR_S1D(ctx->opcode); 3236 r2 = MASK_OP_SRR_S2(ctx->opcode); 3237 3238 switch (op1) { 3239 case OPC1_16_SRR_ADD: 3240 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3241 break; 3242 case OPC1_16_SRR_ADD_A15: 3243 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]); 3244 break; 3245 case OPC1_16_SRR_ADD_15A: 3246 gen_add_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3247 break; 3248 case OPC1_16_SRR_ADD_A: 3249 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], cpu_gpr_a[r2]); 3250 break; 3251 case OPC1_16_SRR_ADDS: 3252 gen_adds(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3253 break; 3254 case OPC1_16_SRR_AND: 3255 tcg_gen_and_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3256 break; 3257 case OPC1_16_SRR_CMOV: 3258 temp = tcg_constant_tl(0); 3259 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp, 3260 cpu_gpr_d[r2], cpu_gpr_d[r1]); 3261 break; 3262 case OPC1_16_SRR_CMOVN: 3263 temp = tcg_constant_tl(0); 3264 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp, 3265 cpu_gpr_d[r2], cpu_gpr_d[r1]); 3266 break; 3267 case OPC1_16_SRR_EQ: 3268 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1], 3269 cpu_gpr_d[r2]); 3270 break; 3271 case OPC1_16_SRR_LT: 3272 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1], 3273 cpu_gpr_d[r2]); 3274 break; 3275 case OPC1_16_SRR_MOV: 3276 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_d[r2]); 3277 break; 3278 case OPC1_16_SRR_MOV_A: 3279 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_d[r2]); 3280 break; 3281 case OPC1_16_SRR_MOV_AA: 3282 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_a[r2]); 3283 break; 3284 case OPC1_16_SRR_MOV_D: 3285 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_a[r2]); 3286 break; 3287 case OPC1_16_SRR_MUL: 3288 gen_mul_i32s(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3289 break; 3290 case OPC1_16_SRR_OR: 3291 tcg_gen_or_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3292 break; 3293 case OPC1_16_SRR_SUB: 3294 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3295 break; 3296 case OPC1_16_SRR_SUB_A15B: 3297 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]); 3298 break; 3299 case OPC1_16_SRR_SUB_15AB: 3300 gen_sub_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3301 break; 3302 case OPC1_16_SRR_SUBS: 3303 gen_subs(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3304 break; 3305 case OPC1_16_SRR_XOR: 3306 tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3307 break; 3308 default: 3309 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3310 } 3311 } 3312 3313 static void decode_ssr_opc(DisasContext *ctx, int op1) 3314 { 3315 int r1, r2; 3316 3317 r1 = MASK_OP_SSR_S1(ctx->opcode); 3318 r2 = MASK_OP_SSR_S2(ctx->opcode); 3319 3320 switch (op1) { 3321 case OPC1_16_SSR_ST_A: 3322 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); 3323 break; 3324 case OPC1_16_SSR_ST_A_POSTINC: 3325 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); 3326 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); 3327 break; 3328 case OPC1_16_SSR_ST_B: 3329 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); 3330 break; 3331 case OPC1_16_SSR_ST_B_POSTINC: 3332 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); 3333 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1); 3334 break; 3335 case OPC1_16_SSR_ST_H: 3336 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW); 3337 break; 3338 case OPC1_16_SSR_ST_H_POSTINC: 3339 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW); 3340 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2); 3341 break; 3342 case OPC1_16_SSR_ST_W: 3343 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); 3344 break; 3345 case OPC1_16_SSR_ST_W_POSTINC: 3346 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); 3347 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); 3348 break; 3349 default: 3350 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3351 } 3352 } 3353 3354 static void decode_sc_opc(DisasContext *ctx, int op1) 3355 { 3356 int32_t const16; 3357 3358 const16 = MASK_OP_SC_CONST8(ctx->opcode); 3359 3360 switch (op1) { 3361 case OPC1_16_SC_AND: 3362 tcg_gen_andi_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16); 3363 break; 3364 case OPC1_16_SC_BISR: 3365 if (ctx->priv == TRICORE_PRIV_SM) { 3366 gen_helper_1arg(bisr, const16 & 0xff); 3367 } else { 3368 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); 3369 } 3370 break; 3371 case OPC1_16_SC_LD_A: 3372 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL); 3373 break; 3374 case OPC1_16_SC_LD_W: 3375 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL); 3376 break; 3377 case OPC1_16_SC_MOV: 3378 tcg_gen_movi_tl(cpu_gpr_d[15], const16); 3379 break; 3380 case OPC1_16_SC_OR: 3381 tcg_gen_ori_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16); 3382 break; 3383 case OPC1_16_SC_ST_A: 3384 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL); 3385 break; 3386 case OPC1_16_SC_ST_W: 3387 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL); 3388 break; 3389 case OPC1_16_SC_SUB_A: 3390 tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16); 3391 break; 3392 default: 3393 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3394 } 3395 } 3396 3397 static void decode_slr_opc(DisasContext *ctx, int op1) 3398 { 3399 int r1, r2; 3400 3401 r1 = MASK_OP_SLR_D(ctx->opcode); 3402 r2 = MASK_OP_SLR_S2(ctx->opcode); 3403 3404 switch (op1) { 3405 /* SLR-format */ 3406 case OPC1_16_SLR_LD_A: 3407 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); 3408 break; 3409 case OPC1_16_SLR_LD_A_POSTINC: 3410 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); 3411 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); 3412 break; 3413 case OPC1_16_SLR_LD_BU: 3414 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); 3415 break; 3416 case OPC1_16_SLR_LD_BU_POSTINC: 3417 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); 3418 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1); 3419 break; 3420 case OPC1_16_SLR_LD_H: 3421 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW); 3422 break; 3423 case OPC1_16_SLR_LD_H_POSTINC: 3424 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW); 3425 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2); 3426 break; 3427 case OPC1_16_SLR_LD_W: 3428 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); 3429 break; 3430 case OPC1_16_SLR_LD_W_POSTINC: 3431 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); 3432 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); 3433 break; 3434 default: 3435 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3436 } 3437 } 3438 3439 static void decode_sro_opc(DisasContext *ctx, int op1) 3440 { 3441 int r2; 3442 int32_t address; 3443 3444 r2 = MASK_OP_SRO_S2(ctx->opcode); 3445 address = MASK_OP_SRO_OFF4(ctx->opcode); 3446 3447 /* SRO-format */ 3448 switch (op1) { 3449 case OPC1_16_SRO_LD_A: 3450 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL); 3451 break; 3452 case OPC1_16_SRO_LD_BU: 3453 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB); 3454 break; 3455 case OPC1_16_SRO_LD_H: 3456 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW); 3457 break; 3458 case OPC1_16_SRO_LD_W: 3459 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL); 3460 break; 3461 case OPC1_16_SRO_ST_A: 3462 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL); 3463 break; 3464 case OPC1_16_SRO_ST_B: 3465 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB); 3466 break; 3467 case OPC1_16_SRO_ST_H: 3468 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW); 3469 break; 3470 case OPC1_16_SRO_ST_W: 3471 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL); 3472 break; 3473 default: 3474 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3475 } 3476 } 3477 3478 static void decode_sr_system(DisasContext *ctx) 3479 { 3480 uint32_t op2; 3481 op2 = MASK_OP_SR_OP2(ctx->opcode); 3482 3483 switch (op2) { 3484 case OPC2_16_SR_NOP: 3485 break; 3486 case OPC2_16_SR_RET: 3487 gen_compute_branch(ctx, op2, 0, 0, 0, 0); 3488 break; 3489 case OPC2_16_SR_RFE: 3490 gen_helper_rfe(tcg_env); 3491 ctx->base.is_jmp = DISAS_EXIT; 3492 break; 3493 case OPC2_16_SR_DEBUG: 3494 /* raise EXCP_DEBUG */ 3495 break; 3496 case OPC2_16_SR_FRET: 3497 gen_fret(ctx); 3498 break; 3499 default: 3500 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3501 } 3502 } 3503 3504 static void decode_sr_accu(DisasContext *ctx) 3505 { 3506 uint32_t op2; 3507 uint32_t r1; 3508 3509 r1 = MASK_OP_SR_S1D(ctx->opcode); 3510 op2 = MASK_OP_SR_OP2(ctx->opcode); 3511 3512 switch (op2) { 3513 case OPC2_16_SR_RSUB: 3514 /* calc V bit -- overflow only if r1 = -0x80000000 */ 3515 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], -0x80000000); 3516 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 3517 /* calc SV bit */ 3518 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 3519 /* sub */ 3520 tcg_gen_neg_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]); 3521 /* calc av */ 3522 tcg_gen_add_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_gpr_d[r1]); 3523 tcg_gen_xor_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_PSW_AV); 3524 /* calc sav */ 3525 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 3526 break; 3527 case OPC2_16_SR_SAT_B: 3528 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7f, -0x80); 3529 break; 3530 case OPC2_16_SR_SAT_BU: 3531 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xff); 3532 break; 3533 case OPC2_16_SR_SAT_H: 3534 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7fff, -0x8000); 3535 break; 3536 case OPC2_16_SR_SAT_HU: 3537 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xffff); 3538 break; 3539 default: 3540 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3541 } 3542 } 3543 3544 static void decode_16Bit_opc(DisasContext *ctx) 3545 { 3546 int op1; 3547 int r1, r2; 3548 int32_t const16; 3549 int32_t address; 3550 TCGv temp; 3551 3552 op1 = MASK_OP_MAJOR(ctx->opcode); 3553 3554 /* handle ADDSC.A opcode only being 6 bit long */ 3555 if (unlikely((op1 & 0x3f) == OPC1_16_SRRS_ADDSC_A)) { 3556 op1 = OPC1_16_SRRS_ADDSC_A; 3557 } 3558 3559 switch (op1) { 3560 case OPC1_16_SRC_ADD: 3561 case OPC1_16_SRC_ADD_A15: 3562 case OPC1_16_SRC_ADD_15A: 3563 case OPC1_16_SRC_ADD_A: 3564 case OPC1_16_SRC_CADD: 3565 case OPC1_16_SRC_CADDN: 3566 case OPC1_16_SRC_CMOV: 3567 case OPC1_16_SRC_CMOVN: 3568 case OPC1_16_SRC_EQ: 3569 case OPC1_16_SRC_LT: 3570 case OPC1_16_SRC_MOV: 3571 case OPC1_16_SRC_MOV_A: 3572 case OPC1_16_SRC_MOV_E: 3573 case OPC1_16_SRC_SH: 3574 case OPC1_16_SRC_SHA: 3575 decode_src_opc(ctx, op1); 3576 break; 3577 /* SRR-format */ 3578 case OPC1_16_SRR_ADD: 3579 case OPC1_16_SRR_ADD_A15: 3580 case OPC1_16_SRR_ADD_15A: 3581 case OPC1_16_SRR_ADD_A: 3582 case OPC1_16_SRR_ADDS: 3583 case OPC1_16_SRR_AND: 3584 case OPC1_16_SRR_CMOV: 3585 case OPC1_16_SRR_CMOVN: 3586 case OPC1_16_SRR_EQ: 3587 case OPC1_16_SRR_LT: 3588 case OPC1_16_SRR_MOV: 3589 case OPC1_16_SRR_MOV_A: 3590 case OPC1_16_SRR_MOV_AA: 3591 case OPC1_16_SRR_MOV_D: 3592 case OPC1_16_SRR_MUL: 3593 case OPC1_16_SRR_OR: 3594 case OPC1_16_SRR_SUB: 3595 case OPC1_16_SRR_SUB_A15B: 3596 case OPC1_16_SRR_SUB_15AB: 3597 case OPC1_16_SRR_SUBS: 3598 case OPC1_16_SRR_XOR: 3599 decode_srr_opc(ctx, op1); 3600 break; 3601 /* SSR-format */ 3602 case OPC1_16_SSR_ST_A: 3603 case OPC1_16_SSR_ST_A_POSTINC: 3604 case OPC1_16_SSR_ST_B: 3605 case OPC1_16_SSR_ST_B_POSTINC: 3606 case OPC1_16_SSR_ST_H: 3607 case OPC1_16_SSR_ST_H_POSTINC: 3608 case OPC1_16_SSR_ST_W: 3609 case OPC1_16_SSR_ST_W_POSTINC: 3610 decode_ssr_opc(ctx, op1); 3611 break; 3612 /* SRRS-format */ 3613 case OPC1_16_SRRS_ADDSC_A: 3614 r2 = MASK_OP_SRRS_S2(ctx->opcode); 3615 r1 = MASK_OP_SRRS_S1D(ctx->opcode); 3616 const16 = MASK_OP_SRRS_N(ctx->opcode); 3617 temp = tcg_temp_new(); 3618 tcg_gen_shli_tl(temp, cpu_gpr_d[15], const16); 3619 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], temp); 3620 break; 3621 /* SLRO-format */ 3622 case OPC1_16_SLRO_LD_A: 3623 r1 = MASK_OP_SLRO_D(ctx->opcode); 3624 const16 = MASK_OP_SLRO_OFF4(ctx->opcode); 3625 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); 3626 break; 3627 case OPC1_16_SLRO_LD_BU: 3628 r1 = MASK_OP_SLRO_D(ctx->opcode); 3629 const16 = MASK_OP_SLRO_OFF4(ctx->opcode); 3630 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB); 3631 break; 3632 case OPC1_16_SLRO_LD_H: 3633 r1 = MASK_OP_SLRO_D(ctx->opcode); 3634 const16 = MASK_OP_SLRO_OFF4(ctx->opcode); 3635 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW); 3636 break; 3637 case OPC1_16_SLRO_LD_W: 3638 r1 = MASK_OP_SLRO_D(ctx->opcode); 3639 const16 = MASK_OP_SLRO_OFF4(ctx->opcode); 3640 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); 3641 break; 3642 /* SB-format */ 3643 case OPC1_16_SB_CALL: 3644 case OPC1_16_SB_J: 3645 case OPC1_16_SB_JNZ: 3646 case OPC1_16_SB_JZ: 3647 address = MASK_OP_SB_DISP8_SEXT(ctx->opcode); 3648 gen_compute_branch(ctx, op1, 0, 0, 0, address); 3649 break; 3650 /* SBC-format */ 3651 case OPC1_16_SBC_JEQ: 3652 case OPC1_16_SBC_JNE: 3653 address = MASK_OP_SBC_DISP4(ctx->opcode); 3654 const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode); 3655 gen_compute_branch(ctx, op1, 0, 0, const16, address); 3656 break; 3657 case OPC1_16_SBC_JEQ2: 3658 case OPC1_16_SBC_JNE2: 3659 if (has_feature(ctx, TRICORE_FEATURE_16)) { 3660 address = MASK_OP_SBC_DISP4(ctx->opcode); 3661 const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode); 3662 gen_compute_branch(ctx, op1, 0, 0, const16, address); 3663 } else { 3664 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3665 } 3666 break; 3667 /* SBRN-format */ 3668 case OPC1_16_SBRN_JNZ_T: 3669 case OPC1_16_SBRN_JZ_T: 3670 address = MASK_OP_SBRN_DISP4(ctx->opcode); 3671 const16 = MASK_OP_SBRN_N(ctx->opcode); 3672 gen_compute_branch(ctx, op1, 0, 0, const16, address); 3673 break; 3674 /* SBR-format */ 3675 case OPC1_16_SBR_JEQ2: 3676 case OPC1_16_SBR_JNE2: 3677 if (has_feature(ctx, TRICORE_FEATURE_16)) { 3678 r1 = MASK_OP_SBR_S2(ctx->opcode); 3679 address = MASK_OP_SBR_DISP4(ctx->opcode); 3680 gen_compute_branch(ctx, op1, r1, 0, 0, address); 3681 } else { 3682 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3683 } 3684 break; 3685 case OPC1_16_SBR_JEQ: 3686 case OPC1_16_SBR_JGEZ: 3687 case OPC1_16_SBR_JGTZ: 3688 case OPC1_16_SBR_JLEZ: 3689 case OPC1_16_SBR_JLTZ: 3690 case OPC1_16_SBR_JNE: 3691 case OPC1_16_SBR_JNZ: 3692 case OPC1_16_SBR_JNZ_A: 3693 case OPC1_16_SBR_JZ: 3694 case OPC1_16_SBR_JZ_A: 3695 case OPC1_16_SBR_LOOP: 3696 r1 = MASK_OP_SBR_S2(ctx->opcode); 3697 address = MASK_OP_SBR_DISP4(ctx->opcode); 3698 gen_compute_branch(ctx, op1, r1, 0, 0, address); 3699 break; 3700 /* SC-format */ 3701 case OPC1_16_SC_AND: 3702 case OPC1_16_SC_BISR: 3703 case OPC1_16_SC_LD_A: 3704 case OPC1_16_SC_LD_W: 3705 case OPC1_16_SC_MOV: 3706 case OPC1_16_SC_OR: 3707 case OPC1_16_SC_ST_A: 3708 case OPC1_16_SC_ST_W: 3709 case OPC1_16_SC_SUB_A: 3710 decode_sc_opc(ctx, op1); 3711 break; 3712 /* SLR-format */ 3713 case OPC1_16_SLR_LD_A: 3714 case OPC1_16_SLR_LD_A_POSTINC: 3715 case OPC1_16_SLR_LD_BU: 3716 case OPC1_16_SLR_LD_BU_POSTINC: 3717 case OPC1_16_SLR_LD_H: 3718 case OPC1_16_SLR_LD_H_POSTINC: 3719 case OPC1_16_SLR_LD_W: 3720 case OPC1_16_SLR_LD_W_POSTINC: 3721 decode_slr_opc(ctx, op1); 3722 break; 3723 /* SRO-format */ 3724 case OPC1_16_SRO_LD_A: 3725 case OPC1_16_SRO_LD_BU: 3726 case OPC1_16_SRO_LD_H: 3727 case OPC1_16_SRO_LD_W: 3728 case OPC1_16_SRO_ST_A: 3729 case OPC1_16_SRO_ST_B: 3730 case OPC1_16_SRO_ST_H: 3731 case OPC1_16_SRO_ST_W: 3732 decode_sro_opc(ctx, op1); 3733 break; 3734 /* SSRO-format */ 3735 case OPC1_16_SSRO_ST_A: 3736 r1 = MASK_OP_SSRO_S1(ctx->opcode); 3737 const16 = MASK_OP_SSRO_OFF4(ctx->opcode); 3738 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); 3739 break; 3740 case OPC1_16_SSRO_ST_B: 3741 r1 = MASK_OP_SSRO_S1(ctx->opcode); 3742 const16 = MASK_OP_SSRO_OFF4(ctx->opcode); 3743 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB); 3744 break; 3745 case OPC1_16_SSRO_ST_H: 3746 r1 = MASK_OP_SSRO_S1(ctx->opcode); 3747 const16 = MASK_OP_SSRO_OFF4(ctx->opcode); 3748 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW); 3749 break; 3750 case OPC1_16_SSRO_ST_W: 3751 r1 = MASK_OP_SSRO_S1(ctx->opcode); 3752 const16 = MASK_OP_SSRO_OFF4(ctx->opcode); 3753 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); 3754 break; 3755 /* SR-format */ 3756 case OPCM_16_SR_SYSTEM: 3757 decode_sr_system(ctx); 3758 break; 3759 case OPCM_16_SR_ACCU: 3760 decode_sr_accu(ctx); 3761 break; 3762 case OPC1_16_SR_JI: 3763 r1 = MASK_OP_SR_S1D(ctx->opcode); 3764 gen_compute_branch(ctx, op1, r1, 0, 0, 0); 3765 break; 3766 case OPC1_16_SR_NOT: 3767 r1 = MASK_OP_SR_S1D(ctx->opcode); 3768 tcg_gen_not_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]); 3769 break; 3770 default: 3771 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3772 } 3773 } 3774 3775 /* 3776 * 32 bit instructions 3777 */ 3778 3779 /* ABS-format */ 3780 static void decode_abs_ldw(DisasContext *ctx) 3781 { 3782 int32_t op2; 3783 int32_t r1; 3784 uint32_t address; 3785 TCGv temp; 3786 3787 r1 = MASK_OP_ABS_S1D(ctx->opcode); 3788 address = MASK_OP_ABS_OFF18(ctx->opcode); 3789 op2 = MASK_OP_ABS_OP2(ctx->opcode); 3790 3791 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 3792 3793 switch (op2) { 3794 case OPC2_32_ABS_LD_A: 3795 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL); 3796 break; 3797 case OPC2_32_ABS_LD_D: 3798 CHECK_REG_PAIR(r1); 3799 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); 3800 break; 3801 case OPC2_32_ABS_LD_DA: 3802 CHECK_REG_PAIR(r1); 3803 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); 3804 break; 3805 case OPC2_32_ABS_LD_W: 3806 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL); 3807 break; 3808 default: 3809 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3810 } 3811 } 3812 3813 static void decode_abs_ldb(DisasContext *ctx) 3814 { 3815 int32_t op2; 3816 int32_t r1; 3817 uint32_t address; 3818 TCGv temp; 3819 3820 r1 = MASK_OP_ABS_S1D(ctx->opcode); 3821 address = MASK_OP_ABS_OFF18(ctx->opcode); 3822 op2 = MASK_OP_ABS_OP2(ctx->opcode); 3823 3824 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 3825 3826 switch (op2) { 3827 case OPC2_32_ABS_LD_B: 3828 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_SB); 3829 break; 3830 case OPC2_32_ABS_LD_BU: 3831 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB); 3832 break; 3833 case OPC2_32_ABS_LD_H: 3834 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESW); 3835 break; 3836 case OPC2_32_ABS_LD_HU: 3837 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); 3838 break; 3839 default: 3840 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3841 } 3842 } 3843 3844 static void decode_abs_ldst_swap(DisasContext *ctx) 3845 { 3846 int32_t op2; 3847 int32_t r1; 3848 uint32_t address; 3849 TCGv temp; 3850 3851 r1 = MASK_OP_ABS_S1D(ctx->opcode); 3852 address = MASK_OP_ABS_OFF18(ctx->opcode); 3853 op2 = MASK_OP_ABS_OP2(ctx->opcode); 3854 3855 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 3856 3857 switch (op2) { 3858 case OPC2_32_ABS_LDMST: 3859 gen_ldmst(ctx, r1, temp); 3860 break; 3861 case OPC2_32_ABS_SWAP_W: 3862 gen_swap(ctx, r1, temp); 3863 break; 3864 default: 3865 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3866 } 3867 } 3868 3869 static void decode_abs_ldst_context(DisasContext *ctx) 3870 { 3871 uint32_t op2; 3872 int32_t off18; 3873 3874 off18 = MASK_OP_ABS_OFF18(ctx->opcode); 3875 op2 = MASK_OP_ABS_OP2(ctx->opcode); 3876 3877 switch (op2) { 3878 case OPC2_32_ABS_LDLCX: 3879 gen_helper_1arg(ldlcx, EA_ABS_FORMAT(off18)); 3880 break; 3881 case OPC2_32_ABS_LDUCX: 3882 gen_helper_1arg(lducx, EA_ABS_FORMAT(off18)); 3883 break; 3884 case OPC2_32_ABS_STLCX: 3885 gen_helper_1arg(stlcx, EA_ABS_FORMAT(off18)); 3886 break; 3887 case OPC2_32_ABS_STUCX: 3888 gen_helper_1arg(stucx, EA_ABS_FORMAT(off18)); 3889 break; 3890 default: 3891 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3892 } 3893 } 3894 3895 static void decode_abs_store(DisasContext *ctx) 3896 { 3897 int32_t op2; 3898 int32_t r1; 3899 uint32_t address; 3900 TCGv temp; 3901 3902 r1 = MASK_OP_ABS_S1D(ctx->opcode); 3903 address = MASK_OP_ABS_OFF18(ctx->opcode); 3904 op2 = MASK_OP_ABS_OP2(ctx->opcode); 3905 3906 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 3907 3908 switch (op2) { 3909 case OPC2_32_ABS_ST_A: 3910 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL); 3911 break; 3912 case OPC2_32_ABS_ST_D: 3913 CHECK_REG_PAIR(r1); 3914 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); 3915 break; 3916 case OPC2_32_ABS_ST_DA: 3917 CHECK_REG_PAIR(r1); 3918 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); 3919 break; 3920 case OPC2_32_ABS_ST_W: 3921 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL); 3922 break; 3923 default: 3924 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3925 } 3926 } 3927 3928 static void decode_abs_storeb_h(DisasContext *ctx) 3929 { 3930 int32_t op2; 3931 int32_t r1; 3932 uint32_t address; 3933 TCGv temp; 3934 3935 r1 = MASK_OP_ABS_S1D(ctx->opcode); 3936 address = MASK_OP_ABS_OFF18(ctx->opcode); 3937 op2 = MASK_OP_ABS_OP2(ctx->opcode); 3938 3939 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 3940 3941 switch (op2) { 3942 case OPC2_32_ABS_ST_B: 3943 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB); 3944 break; 3945 case OPC2_32_ABS_ST_H: 3946 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); 3947 break; 3948 default: 3949 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3950 } 3951 } 3952 3953 /* Bit-format */ 3954 3955 static void decode_bit_andacc(DisasContext *ctx) 3956 { 3957 uint32_t op2; 3958 int r1, r2, r3; 3959 int pos1, pos2; 3960 3961 r1 = MASK_OP_BIT_S1(ctx->opcode); 3962 r2 = MASK_OP_BIT_S2(ctx->opcode); 3963 r3 = MASK_OP_BIT_D(ctx->opcode); 3964 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 3965 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 3966 op2 = MASK_OP_BIT_OP2(ctx->opcode); 3967 3968 3969 switch (op2) { 3970 case OPC2_32_BIT_AND_AND_T: 3971 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 3972 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_and_tl); 3973 break; 3974 case OPC2_32_BIT_AND_ANDN_T: 3975 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 3976 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_and_tl); 3977 break; 3978 case OPC2_32_BIT_AND_NOR_T: 3979 if (tcg_op_supported(INDEX_op_andc, TCG_TYPE_I32, 0)) { 3980 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 3981 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_andc_tl); 3982 } else { 3983 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 3984 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_and_tl); 3985 } 3986 break; 3987 case OPC2_32_BIT_AND_OR_T: 3988 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 3989 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_and_tl); 3990 break; 3991 default: 3992 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3993 } 3994 } 3995 3996 static void decode_bit_logical_t(DisasContext *ctx) 3997 { 3998 uint32_t op2; 3999 int r1, r2, r3; 4000 int pos1, pos2; 4001 r1 = MASK_OP_BIT_S1(ctx->opcode); 4002 r2 = MASK_OP_BIT_S2(ctx->opcode); 4003 r3 = MASK_OP_BIT_D(ctx->opcode); 4004 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4005 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4006 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4007 4008 switch (op2) { 4009 case OPC2_32_BIT_AND_T: 4010 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4011 pos1, pos2, &tcg_gen_and_tl); 4012 break; 4013 case OPC2_32_BIT_ANDN_T: 4014 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4015 pos1, pos2, &tcg_gen_andc_tl); 4016 break; 4017 case OPC2_32_BIT_NOR_T: 4018 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4019 pos1, pos2, &tcg_gen_nor_tl); 4020 break; 4021 case OPC2_32_BIT_OR_T: 4022 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4023 pos1, pos2, &tcg_gen_or_tl); 4024 break; 4025 default: 4026 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4027 } 4028 } 4029 4030 static void decode_bit_insert(DisasContext *ctx) 4031 { 4032 uint32_t op2; 4033 int r1, r2, r3; 4034 int pos1, pos2; 4035 TCGv temp; 4036 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4037 r1 = MASK_OP_BIT_S1(ctx->opcode); 4038 r2 = MASK_OP_BIT_S2(ctx->opcode); 4039 r3 = MASK_OP_BIT_D(ctx->opcode); 4040 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4041 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4042 4043 temp = tcg_temp_new(); 4044 4045 tcg_gen_shri_tl(temp, cpu_gpr_d[r2], pos2); 4046 if (op2 == OPC2_32_BIT_INSN_T) { 4047 tcg_gen_not_tl(temp, temp); 4048 } 4049 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, pos1, 1); 4050 } 4051 4052 static void decode_bit_logical_t2(DisasContext *ctx) 4053 { 4054 uint32_t op2; 4055 4056 int r1, r2, r3; 4057 int pos1, pos2; 4058 4059 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4060 r1 = MASK_OP_BIT_S1(ctx->opcode); 4061 r2 = MASK_OP_BIT_S2(ctx->opcode); 4062 r3 = MASK_OP_BIT_D(ctx->opcode); 4063 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4064 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4065 4066 switch (op2) { 4067 case OPC2_32_BIT_NAND_T: 4068 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4069 pos1, pos2, &tcg_gen_nand_tl); 4070 break; 4071 case OPC2_32_BIT_ORN_T: 4072 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4073 pos1, pos2, &tcg_gen_orc_tl); 4074 break; 4075 case OPC2_32_BIT_XNOR_T: 4076 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4077 pos1, pos2, &tcg_gen_eqv_tl); 4078 break; 4079 case OPC2_32_BIT_XOR_T: 4080 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4081 pos1, pos2, &tcg_gen_xor_tl); 4082 break; 4083 default: 4084 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4085 } 4086 } 4087 4088 static void decode_bit_orand(DisasContext *ctx) 4089 { 4090 uint32_t op2; 4091 4092 int r1, r2, r3; 4093 int pos1, pos2; 4094 4095 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4096 r1 = MASK_OP_BIT_S1(ctx->opcode); 4097 r2 = MASK_OP_BIT_S2(ctx->opcode); 4098 r3 = MASK_OP_BIT_D(ctx->opcode); 4099 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4100 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4101 4102 switch (op2) { 4103 case OPC2_32_BIT_OR_AND_T: 4104 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4105 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_or_tl); 4106 break; 4107 case OPC2_32_BIT_OR_ANDN_T: 4108 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4109 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_or_tl); 4110 break; 4111 case OPC2_32_BIT_OR_NOR_T: 4112 if (tcg_op_supported(INDEX_op_orc, TCG_TYPE_I32, 0)) { 4113 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4114 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_orc_tl); 4115 } else { 4116 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4117 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_or_tl); 4118 } 4119 break; 4120 case OPC2_32_BIT_OR_OR_T: 4121 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4122 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_or_tl); 4123 break; 4124 default: 4125 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4126 } 4127 } 4128 4129 static void decode_bit_sh_logic1(DisasContext *ctx) 4130 { 4131 uint32_t op2; 4132 int r1, r2, r3; 4133 int pos1, pos2; 4134 TCGv temp; 4135 4136 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4137 r1 = MASK_OP_BIT_S1(ctx->opcode); 4138 r2 = MASK_OP_BIT_S2(ctx->opcode); 4139 r3 = MASK_OP_BIT_D(ctx->opcode); 4140 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4141 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4142 4143 temp = tcg_temp_new(); 4144 4145 switch (op2) { 4146 case OPC2_32_BIT_SH_AND_T: 4147 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4148 pos1, pos2, &tcg_gen_and_tl); 4149 break; 4150 case OPC2_32_BIT_SH_ANDN_T: 4151 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4152 pos1, pos2, &tcg_gen_andc_tl); 4153 break; 4154 case OPC2_32_BIT_SH_NOR_T: 4155 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4156 pos1, pos2, &tcg_gen_nor_tl); 4157 break; 4158 case OPC2_32_BIT_SH_OR_T: 4159 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4160 pos1, pos2, &tcg_gen_or_tl); 4161 break; 4162 default: 4163 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4164 } 4165 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1); 4166 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp); 4167 } 4168 4169 static void decode_bit_sh_logic2(DisasContext *ctx) 4170 { 4171 uint32_t op2; 4172 int r1, r2, r3; 4173 int pos1, pos2; 4174 TCGv temp; 4175 4176 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4177 r1 = MASK_OP_BIT_S1(ctx->opcode); 4178 r2 = MASK_OP_BIT_S2(ctx->opcode); 4179 r3 = MASK_OP_BIT_D(ctx->opcode); 4180 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4181 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4182 4183 temp = tcg_temp_new(); 4184 4185 switch (op2) { 4186 case OPC2_32_BIT_SH_NAND_T: 4187 gen_bit_1op(temp, cpu_gpr_d[r1] , cpu_gpr_d[r2] , 4188 pos1, pos2, &tcg_gen_nand_tl); 4189 break; 4190 case OPC2_32_BIT_SH_ORN_T: 4191 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4192 pos1, pos2, &tcg_gen_orc_tl); 4193 break; 4194 case OPC2_32_BIT_SH_XNOR_T: 4195 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4196 pos1, pos2, &tcg_gen_eqv_tl); 4197 break; 4198 case OPC2_32_BIT_SH_XOR_T: 4199 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4200 pos1, pos2, &tcg_gen_xor_tl); 4201 break; 4202 default: 4203 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4204 } 4205 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1); 4206 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp); 4207 } 4208 4209 /* BO-format */ 4210 4211 4212 static void decode_bo_addrmode_post_pre_base(DisasContext *ctx) 4213 { 4214 uint32_t op2; 4215 uint32_t off10; 4216 int32_t r1, r2; 4217 TCGv temp; 4218 4219 r1 = MASK_OP_BO_S1D(ctx->opcode); 4220 r2 = MASK_OP_BO_S2(ctx->opcode); 4221 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4222 op2 = MASK_OP_BO_OP2(ctx->opcode); 4223 4224 switch (op2) { 4225 case OPC2_32_BO_CACHEA_WI_SHORTOFF: 4226 case OPC2_32_BO_CACHEA_W_SHORTOFF: 4227 case OPC2_32_BO_CACHEA_I_SHORTOFF: 4228 /* instruction to access the cache */ 4229 break; 4230 case OPC2_32_BO_CACHEA_WI_POSTINC: 4231 case OPC2_32_BO_CACHEA_W_POSTINC: 4232 case OPC2_32_BO_CACHEA_I_POSTINC: 4233 /* instruction to access the cache, but we still need to handle 4234 the addressing mode */ 4235 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4236 break; 4237 case OPC2_32_BO_CACHEA_WI_PREINC: 4238 case OPC2_32_BO_CACHEA_W_PREINC: 4239 case OPC2_32_BO_CACHEA_I_PREINC: 4240 /* instruction to access the cache, but we still need to handle 4241 the addressing mode */ 4242 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4243 break; 4244 case OPC2_32_BO_CACHEI_WI_SHORTOFF: 4245 case OPC2_32_BO_CACHEI_W_SHORTOFF: 4246 if (!has_feature(ctx, TRICORE_FEATURE_131)) { 4247 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4248 } 4249 break; 4250 case OPC2_32_BO_CACHEI_W_POSTINC: 4251 case OPC2_32_BO_CACHEI_WI_POSTINC: 4252 if (has_feature(ctx, TRICORE_FEATURE_131)) { 4253 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4254 } else { 4255 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4256 } 4257 break; 4258 case OPC2_32_BO_CACHEI_W_PREINC: 4259 case OPC2_32_BO_CACHEI_WI_PREINC: 4260 if (has_feature(ctx, TRICORE_FEATURE_131)) { 4261 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4262 } else { 4263 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4264 } 4265 break; 4266 case OPC2_32_BO_ST_A_SHORTOFF: 4267 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL); 4268 break; 4269 case OPC2_32_BO_ST_A_POSTINC: 4270 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, 4271 MO_LESL); 4272 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4273 break; 4274 case OPC2_32_BO_ST_A_PREINC: 4275 gen_st_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL); 4276 break; 4277 case OPC2_32_BO_ST_B_SHORTOFF: 4278 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); 4279 break; 4280 case OPC2_32_BO_ST_B_POSTINC: 4281 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4282 MO_UB); 4283 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4284 break; 4285 case OPC2_32_BO_ST_B_PREINC: 4286 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); 4287 break; 4288 case OPC2_32_BO_ST_D_SHORTOFF: 4289 CHECK_REG_PAIR(r1); 4290 gen_offset_st_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], 4291 off10, ctx); 4292 break; 4293 case OPC2_32_BO_ST_D_POSTINC: 4294 CHECK_REG_PAIR(r1); 4295 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx); 4296 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4297 break; 4298 case OPC2_32_BO_ST_D_PREINC: 4299 CHECK_REG_PAIR(r1); 4300 temp = tcg_temp_new(); 4301 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4302 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); 4303 tcg_gen_mov_tl(cpu_gpr_a[r2], temp); 4304 break; 4305 case OPC2_32_BO_ST_DA_SHORTOFF: 4306 CHECK_REG_PAIR(r1); 4307 gen_offset_st_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], 4308 off10, ctx); 4309 break; 4310 case OPC2_32_BO_ST_DA_POSTINC: 4311 CHECK_REG_PAIR(r1); 4312 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx); 4313 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4314 break; 4315 case OPC2_32_BO_ST_DA_PREINC: 4316 CHECK_REG_PAIR(r1); 4317 temp = tcg_temp_new(); 4318 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4319 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); 4320 tcg_gen_mov_tl(cpu_gpr_a[r2], temp); 4321 break; 4322 case OPC2_32_BO_ST_H_SHORTOFF: 4323 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4324 break; 4325 case OPC2_32_BO_ST_H_POSTINC: 4326 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4327 MO_LEUW); 4328 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4329 break; 4330 case OPC2_32_BO_ST_H_PREINC: 4331 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4332 break; 4333 case OPC2_32_BO_ST_Q_SHORTOFF: 4334 temp = tcg_temp_new(); 4335 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4336 gen_offset_st(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW); 4337 break; 4338 case OPC2_32_BO_ST_Q_POSTINC: 4339 temp = tcg_temp_new(); 4340 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4341 tcg_gen_qemu_st_tl(temp, cpu_gpr_a[r2], ctx->mem_idx, 4342 MO_LEUW); 4343 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4344 break; 4345 case OPC2_32_BO_ST_Q_PREINC: 4346 temp = tcg_temp_new(); 4347 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4348 gen_st_preincr(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW); 4349 break; 4350 case OPC2_32_BO_ST_W_SHORTOFF: 4351 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4352 break; 4353 case OPC2_32_BO_ST_W_POSTINC: 4354 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4355 MO_LEUL); 4356 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4357 break; 4358 case OPC2_32_BO_ST_W_PREINC: 4359 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4360 break; 4361 default: 4362 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4363 } 4364 } 4365 4366 static void decode_bo_addrmode_bitreverse_circular(DisasContext *ctx) 4367 { 4368 uint32_t op2; 4369 uint32_t off10; 4370 int32_t r1, r2; 4371 TCGv temp, temp2, t_off10; 4372 4373 r1 = MASK_OP_BO_S1D(ctx->opcode); 4374 r2 = MASK_OP_BO_S2(ctx->opcode); 4375 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4376 op2 = MASK_OP_BO_OP2(ctx->opcode); 4377 4378 temp = tcg_temp_new(); 4379 temp2 = tcg_temp_new(); 4380 t_off10 = tcg_constant_i32(off10); 4381 CHECK_REG_PAIR(r2); 4382 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]); 4383 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4384 4385 switch (op2) { 4386 case OPC2_32_BO_CACHEA_WI_BR: 4387 case OPC2_32_BO_CACHEA_W_BR: 4388 case OPC2_32_BO_CACHEA_I_BR: 4389 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4390 break; 4391 case OPC2_32_BO_CACHEA_WI_CIRC: 4392 case OPC2_32_BO_CACHEA_W_CIRC: 4393 case OPC2_32_BO_CACHEA_I_CIRC: 4394 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4395 break; 4396 case OPC2_32_BO_ST_A_BR: 4397 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4398 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4399 break; 4400 case OPC2_32_BO_ST_A_CIRC: 4401 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4402 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4403 break; 4404 case OPC2_32_BO_ST_B_BR: 4405 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); 4406 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4407 break; 4408 case OPC2_32_BO_ST_B_CIRC: 4409 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); 4410 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4411 break; 4412 case OPC2_32_BO_ST_D_BR: 4413 CHECK_REG_PAIR(r1); 4414 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx); 4415 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4416 break; 4417 case OPC2_32_BO_ST_D_CIRC: 4418 CHECK_REG_PAIR(r1); 4419 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4420 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); 4421 tcg_gen_addi_tl(temp, temp, 4); 4422 tcg_gen_rem_tl(temp, temp, temp2); 4423 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4424 tcg_gen_qemu_st_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL); 4425 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4426 break; 4427 case OPC2_32_BO_ST_DA_BR: 4428 CHECK_REG_PAIR(r1); 4429 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx); 4430 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4431 break; 4432 case OPC2_32_BO_ST_DA_CIRC: 4433 CHECK_REG_PAIR(r1); 4434 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4435 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); 4436 tcg_gen_addi_tl(temp, temp, 4); 4437 tcg_gen_rem_tl(temp, temp, temp2); 4438 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4439 tcg_gen_qemu_st_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL); 4440 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4441 break; 4442 case OPC2_32_BO_ST_H_BR: 4443 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4444 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4445 break; 4446 case OPC2_32_BO_ST_H_CIRC: 4447 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4448 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4449 break; 4450 case OPC2_32_BO_ST_Q_BR: 4451 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4452 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW); 4453 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4454 break; 4455 case OPC2_32_BO_ST_Q_CIRC: 4456 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4457 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW); 4458 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4459 break; 4460 case OPC2_32_BO_ST_W_BR: 4461 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4462 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4463 break; 4464 case OPC2_32_BO_ST_W_CIRC: 4465 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4466 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4467 break; 4468 default: 4469 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4470 } 4471 } 4472 4473 static void decode_bo_addrmode_ld_post_pre_base(DisasContext *ctx) 4474 { 4475 uint32_t op2; 4476 uint32_t off10; 4477 int32_t r1, r2; 4478 TCGv temp; 4479 4480 r1 = MASK_OP_BO_S1D(ctx->opcode); 4481 r2 = MASK_OP_BO_S2(ctx->opcode); 4482 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4483 op2 = MASK_OP_BO_OP2(ctx->opcode); 4484 4485 switch (op2) { 4486 case OPC2_32_BO_LD_A_SHORTOFF: 4487 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4488 break; 4489 case OPC2_32_BO_LD_A_POSTINC: 4490 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, 4491 MO_LEUL); 4492 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4493 break; 4494 case OPC2_32_BO_LD_A_PREINC: 4495 gen_ld_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4496 break; 4497 case OPC2_32_BO_LD_B_SHORTOFF: 4498 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB); 4499 break; 4500 case OPC2_32_BO_LD_B_POSTINC: 4501 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4502 MO_SB); 4503 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4504 break; 4505 case OPC2_32_BO_LD_B_PREINC: 4506 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB); 4507 break; 4508 case OPC2_32_BO_LD_BU_SHORTOFF: 4509 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); 4510 break; 4511 case OPC2_32_BO_LD_BU_POSTINC: 4512 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4513 MO_UB); 4514 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4515 break; 4516 case OPC2_32_BO_LD_BU_PREINC: 4517 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); 4518 break; 4519 case OPC2_32_BO_LD_D_SHORTOFF: 4520 CHECK_REG_PAIR(r1); 4521 gen_offset_ld_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], 4522 off10, ctx); 4523 break; 4524 case OPC2_32_BO_LD_D_POSTINC: 4525 CHECK_REG_PAIR(r1); 4526 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx); 4527 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4528 break; 4529 case OPC2_32_BO_LD_D_PREINC: 4530 CHECK_REG_PAIR(r1); 4531 temp = tcg_temp_new(); 4532 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4533 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); 4534 tcg_gen_mov_tl(cpu_gpr_a[r2], temp); 4535 break; 4536 case OPC2_32_BO_LD_DA_SHORTOFF: 4537 CHECK_REG_PAIR(r1); 4538 gen_offset_ld_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], 4539 off10, ctx); 4540 break; 4541 case OPC2_32_BO_LD_DA_POSTINC: 4542 CHECK_REG_PAIR(r1); 4543 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx); 4544 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4545 break; 4546 case OPC2_32_BO_LD_DA_PREINC: 4547 CHECK_REG_PAIR(r1); 4548 temp = tcg_temp_new(); 4549 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4550 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); 4551 tcg_gen_mov_tl(cpu_gpr_a[r2], temp); 4552 break; 4553 case OPC2_32_BO_LD_H_SHORTOFF: 4554 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW); 4555 break; 4556 case OPC2_32_BO_LD_H_POSTINC: 4557 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4558 MO_LESW); 4559 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4560 break; 4561 case OPC2_32_BO_LD_H_PREINC: 4562 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW); 4563 break; 4564 case OPC2_32_BO_LD_HU_SHORTOFF: 4565 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4566 break; 4567 case OPC2_32_BO_LD_HU_POSTINC: 4568 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4569 MO_LEUW); 4570 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4571 break; 4572 case OPC2_32_BO_LD_HU_PREINC: 4573 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4574 break; 4575 case OPC2_32_BO_LD_Q_SHORTOFF: 4576 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4577 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 4578 break; 4579 case OPC2_32_BO_LD_Q_POSTINC: 4580 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4581 MO_LEUW); 4582 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 4583 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4584 break; 4585 case OPC2_32_BO_LD_Q_PREINC: 4586 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4587 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 4588 break; 4589 case OPC2_32_BO_LD_W_SHORTOFF: 4590 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4591 break; 4592 case OPC2_32_BO_LD_W_POSTINC: 4593 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4594 MO_LEUL); 4595 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4596 break; 4597 case OPC2_32_BO_LD_W_PREINC: 4598 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4599 break; 4600 default: 4601 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4602 } 4603 } 4604 4605 static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx) 4606 { 4607 uint32_t op2; 4608 uint32_t off10; 4609 int r1, r2; 4610 TCGv temp, temp2, t_off10; 4611 4612 r1 = MASK_OP_BO_S1D(ctx->opcode); 4613 r2 = MASK_OP_BO_S2(ctx->opcode); 4614 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4615 op2 = MASK_OP_BO_OP2(ctx->opcode); 4616 4617 temp = tcg_temp_new(); 4618 temp2 = tcg_temp_new(); 4619 t_off10 = tcg_constant_i32(off10); 4620 CHECK_REG_PAIR(r2); 4621 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]); 4622 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4623 4624 4625 switch (op2) { 4626 case OPC2_32_BO_LD_A_BR: 4627 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4628 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4629 break; 4630 case OPC2_32_BO_LD_A_CIRC: 4631 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4632 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4633 break; 4634 case OPC2_32_BO_LD_B_BR: 4635 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB); 4636 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4637 break; 4638 case OPC2_32_BO_LD_B_CIRC: 4639 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB); 4640 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4641 break; 4642 case OPC2_32_BO_LD_BU_BR: 4643 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); 4644 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4645 break; 4646 case OPC2_32_BO_LD_BU_CIRC: 4647 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); 4648 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4649 break; 4650 case OPC2_32_BO_LD_D_BR: 4651 CHECK_REG_PAIR(r1); 4652 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx); 4653 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4654 break; 4655 case OPC2_32_BO_LD_D_CIRC: 4656 CHECK_REG_PAIR(r1); 4657 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4658 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); 4659 tcg_gen_addi_tl(temp, temp, 4); 4660 tcg_gen_rem_tl(temp, temp, temp2); 4661 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4662 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL); 4663 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4664 break; 4665 case OPC2_32_BO_LD_DA_BR: 4666 CHECK_REG_PAIR(r1); 4667 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx); 4668 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4669 break; 4670 case OPC2_32_BO_LD_DA_CIRC: 4671 CHECK_REG_PAIR(r1); 4672 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4673 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); 4674 tcg_gen_addi_tl(temp, temp, 4); 4675 tcg_gen_rem_tl(temp, temp, temp2); 4676 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4677 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL); 4678 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4679 break; 4680 case OPC2_32_BO_LD_H_BR: 4681 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW); 4682 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4683 break; 4684 case OPC2_32_BO_LD_H_CIRC: 4685 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW); 4686 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4687 break; 4688 case OPC2_32_BO_LD_HU_BR: 4689 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4690 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4691 break; 4692 case OPC2_32_BO_LD_HU_CIRC: 4693 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4694 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4695 break; 4696 case OPC2_32_BO_LD_Q_BR: 4697 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4698 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 4699 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4700 break; 4701 case OPC2_32_BO_LD_Q_CIRC: 4702 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4703 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 4704 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4705 break; 4706 case OPC2_32_BO_LD_W_BR: 4707 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4708 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4709 break; 4710 case OPC2_32_BO_LD_W_CIRC: 4711 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4712 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4713 break; 4714 default: 4715 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4716 } 4717 } 4718 4719 static void decode_bo_addrmode_stctx_post_pre_base(DisasContext *ctx) 4720 { 4721 uint32_t op2; 4722 uint32_t off10; 4723 int r1, r2; 4724 4725 TCGv temp; 4726 4727 r1 = MASK_OP_BO_S1D(ctx->opcode); 4728 r2 = MASK_OP_BO_S2(ctx->opcode); 4729 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4730 op2 = MASK_OP_BO_OP2(ctx->opcode); 4731 4732 4733 temp = tcg_temp_new(); 4734 4735 switch (op2) { 4736 case OPC2_32_BO_LDLCX_SHORTOFF: 4737 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4738 gen_helper_ldlcx(tcg_env, temp); 4739 break; 4740 case OPC2_32_BO_LDMST_SHORTOFF: 4741 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4742 gen_ldmst(ctx, r1, temp); 4743 break; 4744 case OPC2_32_BO_LDMST_POSTINC: 4745 gen_ldmst(ctx, r1, cpu_gpr_a[r2]); 4746 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4747 break; 4748 case OPC2_32_BO_LDMST_PREINC: 4749 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4750 gen_ldmst(ctx, r1, cpu_gpr_a[r2]); 4751 break; 4752 case OPC2_32_BO_LDUCX_SHORTOFF: 4753 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4754 gen_helper_lducx(tcg_env, temp); 4755 break; 4756 case OPC2_32_BO_LEA_SHORTOFF: 4757 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], off10); 4758 break; 4759 case OPC2_32_BO_STLCX_SHORTOFF: 4760 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4761 gen_helper_stlcx(tcg_env, temp); 4762 break; 4763 case OPC2_32_BO_STUCX_SHORTOFF: 4764 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4765 gen_helper_stucx(tcg_env, temp); 4766 break; 4767 case OPC2_32_BO_SWAP_W_SHORTOFF: 4768 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4769 gen_swap(ctx, r1, temp); 4770 break; 4771 case OPC2_32_BO_SWAP_W_POSTINC: 4772 gen_swap(ctx, r1, cpu_gpr_a[r2]); 4773 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4774 break; 4775 case OPC2_32_BO_SWAP_W_PREINC: 4776 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4777 gen_swap(ctx, r1, cpu_gpr_a[r2]); 4778 break; 4779 case OPC2_32_BO_CMPSWAP_W_SHORTOFF: 4780 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4781 gen_cmpswap(ctx, r1, temp); 4782 break; 4783 case OPC2_32_BO_CMPSWAP_W_POSTINC: 4784 gen_cmpswap(ctx, r1, cpu_gpr_a[r2]); 4785 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4786 break; 4787 case OPC2_32_BO_CMPSWAP_W_PREINC: 4788 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4789 gen_cmpswap(ctx, r1, cpu_gpr_a[r2]); 4790 break; 4791 case OPC2_32_BO_SWAPMSK_W_SHORTOFF: 4792 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4793 gen_swapmsk(ctx, r1, temp); 4794 break; 4795 case OPC2_32_BO_SWAPMSK_W_POSTINC: 4796 gen_swapmsk(ctx, r1, cpu_gpr_a[r2]); 4797 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4798 break; 4799 case OPC2_32_BO_SWAPMSK_W_PREINC: 4800 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4801 gen_swapmsk(ctx, r1, cpu_gpr_a[r2]); 4802 break; 4803 default: 4804 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4805 } 4806 } 4807 4808 static void decode_bo_addrmode_ldmst_bitreverse_circular(DisasContext *ctx) 4809 { 4810 uint32_t op2; 4811 uint32_t off10; 4812 int r1, r2; 4813 TCGv temp, temp2, t_off10; 4814 4815 r1 = MASK_OP_BO_S1D(ctx->opcode); 4816 r2 = MASK_OP_BO_S2(ctx->opcode); 4817 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4818 op2 = MASK_OP_BO_OP2(ctx->opcode); 4819 4820 temp = tcg_temp_new(); 4821 temp2 = tcg_temp_new(); 4822 t_off10 = tcg_constant_i32(off10); 4823 CHECK_REG_PAIR(r2); 4824 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]); 4825 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4826 4827 switch (op2) { 4828 case OPC2_32_BO_LDMST_BR: 4829 gen_ldmst(ctx, r1, temp2); 4830 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4831 break; 4832 case OPC2_32_BO_LDMST_CIRC: 4833 gen_ldmst(ctx, r1, temp2); 4834 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4835 break; 4836 case OPC2_32_BO_SWAP_W_BR: 4837 gen_swap(ctx, r1, temp2); 4838 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4839 break; 4840 case OPC2_32_BO_SWAP_W_CIRC: 4841 gen_swap(ctx, r1, temp2); 4842 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4843 break; 4844 case OPC2_32_BO_CMPSWAP_W_BR: 4845 gen_cmpswap(ctx, r1, temp2); 4846 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4847 break; 4848 case OPC2_32_BO_CMPSWAP_W_CIRC: 4849 gen_cmpswap(ctx, r1, temp2); 4850 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4851 break; 4852 case OPC2_32_BO_SWAPMSK_W_BR: 4853 gen_swapmsk(ctx, r1, temp2); 4854 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4855 break; 4856 case OPC2_32_BO_SWAPMSK_W_CIRC: 4857 gen_swapmsk(ctx, r1, temp2); 4858 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4859 break; 4860 default: 4861 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4862 } 4863 } 4864 4865 static void decode_bol_opc(DisasContext *ctx, int32_t op1) 4866 { 4867 int r1, r2; 4868 int32_t address; 4869 TCGv temp; 4870 4871 r1 = MASK_OP_BOL_S1D(ctx->opcode); 4872 r2 = MASK_OP_BOL_S2(ctx->opcode); 4873 address = MASK_OP_BOL_OFF16_SEXT(ctx->opcode); 4874 4875 switch (op1) { 4876 case OPC1_32_BOL_LD_A_LONGOFF: 4877 temp = tcg_temp_new(); 4878 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address); 4879 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LEUL); 4880 break; 4881 case OPC1_32_BOL_LD_W_LONGOFF: 4882 temp = tcg_temp_new(); 4883 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address); 4884 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUL); 4885 break; 4886 case OPC1_32_BOL_LEA_LONGOFF: 4887 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], address); 4888 break; 4889 case OPC1_32_BOL_ST_A_LONGOFF: 4890 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4891 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], address, MO_LEUL); 4892 } else { 4893 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4894 } 4895 break; 4896 case OPC1_32_BOL_ST_W_LONGOFF: 4897 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUL); 4898 break; 4899 case OPC1_32_BOL_LD_B_LONGOFF: 4900 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4901 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB); 4902 } else { 4903 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4904 } 4905 break; 4906 case OPC1_32_BOL_LD_BU_LONGOFF: 4907 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4908 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_UB); 4909 } else { 4910 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4911 } 4912 break; 4913 case OPC1_32_BOL_LD_H_LONGOFF: 4914 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4915 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW); 4916 } else { 4917 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4918 } 4919 break; 4920 case OPC1_32_BOL_LD_HU_LONGOFF: 4921 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4922 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUW); 4923 } else { 4924 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4925 } 4926 break; 4927 case OPC1_32_BOL_ST_B_LONGOFF: 4928 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4929 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB); 4930 } else { 4931 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4932 } 4933 break; 4934 case OPC1_32_BOL_ST_H_LONGOFF: 4935 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4936 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW); 4937 } else { 4938 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4939 } 4940 break; 4941 default: 4942 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4943 } 4944 } 4945 4946 /* RC format */ 4947 static void decode_rc_logical_shift(DisasContext *ctx) 4948 { 4949 uint32_t op2; 4950 int r1, r2; 4951 int32_t const9; 4952 TCGv temp; 4953 4954 r2 = MASK_OP_RC_D(ctx->opcode); 4955 r1 = MASK_OP_RC_S1(ctx->opcode); 4956 const9 = MASK_OP_RC_CONST9(ctx->opcode); 4957 op2 = MASK_OP_RC_OP2(ctx->opcode); 4958 4959 switch (op2) { 4960 case OPC2_32_RC_AND: 4961 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 4962 break; 4963 case OPC2_32_RC_ANDN: 4964 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9); 4965 break; 4966 case OPC2_32_RC_NAND: 4967 temp = tcg_temp_new(); 4968 tcg_gen_movi_tl(temp, const9); 4969 tcg_gen_nand_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp); 4970 break; 4971 case OPC2_32_RC_NOR: 4972 temp = tcg_temp_new(); 4973 tcg_gen_movi_tl(temp, const9); 4974 tcg_gen_nor_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp); 4975 break; 4976 case OPC2_32_RC_OR: 4977 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 4978 break; 4979 case OPC2_32_RC_ORN: 4980 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9); 4981 break; 4982 case OPC2_32_RC_SH: 4983 const9 = sextract32(const9, 0, 6); 4984 gen_shi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 4985 break; 4986 case OPC2_32_RC_SH_H: 4987 const9 = sextract32(const9, 0, 5); 4988 gen_sh_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 4989 break; 4990 case OPC2_32_RC_SHA: 4991 const9 = sextract32(const9, 0, 6); 4992 gen_shaci(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 4993 break; 4994 case OPC2_32_RC_SHA_H: 4995 const9 = sextract32(const9, 0, 5); 4996 gen_sha_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 4997 break; 4998 case OPC2_32_RC_SHAS: 4999 gen_shasi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5000 break; 5001 case OPC2_32_RC_XNOR: 5002 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5003 tcg_gen_not_tl(cpu_gpr_d[r2], cpu_gpr_d[r2]); 5004 break; 5005 case OPC2_32_RC_XOR: 5006 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5007 break; 5008 case OPC2_32_RC_SHUFFLE: 5009 if (has_feature(ctx, TRICORE_FEATURE_162)) { 5010 temp = tcg_constant_i32(const9); 5011 gen_helper_shuffle(cpu_gpr_d[r2], cpu_gpr_d[r1], temp); 5012 } else { 5013 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5014 } 5015 break; 5016 default: 5017 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5018 } 5019 } 5020 5021 static void decode_rc_accumulator(DisasContext *ctx) 5022 { 5023 uint32_t op2; 5024 int r1, r2; 5025 int16_t const9; 5026 5027 TCGv temp; 5028 5029 r2 = MASK_OP_RC_D(ctx->opcode); 5030 r1 = MASK_OP_RC_S1(ctx->opcode); 5031 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode); 5032 5033 op2 = MASK_OP_RC_OP2(ctx->opcode); 5034 5035 temp = tcg_temp_new(); 5036 5037 switch (op2) { 5038 case OPC2_32_RC_ABSDIF: 5039 gen_absdifi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5040 break; 5041 case OPC2_32_RC_ABSDIFS: 5042 gen_absdifsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5043 break; 5044 case OPC2_32_RC_ADD: 5045 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5046 break; 5047 case OPC2_32_RC_ADDC: 5048 gen_addci_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5049 break; 5050 case OPC2_32_RC_ADDS: 5051 gen_addsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5052 break; 5053 case OPC2_32_RC_ADDS_U: 5054 gen_addsui(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5055 break; 5056 case OPC2_32_RC_ADDX: 5057 gen_addi_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5058 break; 5059 case OPC2_32_RC_AND_EQ: 5060 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], 5061 const9, &tcg_gen_and_tl); 5062 break; 5063 case OPC2_32_RC_AND_GE: 5064 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5065 const9, &tcg_gen_and_tl); 5066 break; 5067 case OPC2_32_RC_AND_GE_U: 5068 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5069 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5070 const9, &tcg_gen_and_tl); 5071 break; 5072 case OPC2_32_RC_AND_LT: 5073 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], 5074 const9, &tcg_gen_and_tl); 5075 break; 5076 case OPC2_32_RC_AND_LT_U: 5077 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5078 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5079 const9, &tcg_gen_and_tl); 5080 break; 5081 case OPC2_32_RC_AND_NE: 5082 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5083 const9, &tcg_gen_and_tl); 5084 break; 5085 case OPC2_32_RC_EQ: 5086 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5087 break; 5088 case OPC2_32_RC_EQANY_B: 5089 gen_eqany_bi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5090 break; 5091 case OPC2_32_RC_EQANY_H: 5092 gen_eqany_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5093 break; 5094 case OPC2_32_RC_GE: 5095 tcg_gen_setcondi_tl(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5096 break; 5097 case OPC2_32_RC_GE_U: 5098 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5099 tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5100 break; 5101 case OPC2_32_RC_LT: 5102 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5103 break; 5104 case OPC2_32_RC_LT_U: 5105 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5106 tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5107 break; 5108 case OPC2_32_RC_MAX: 5109 tcg_gen_movi_tl(temp, const9); 5110 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, 5111 cpu_gpr_d[r1], temp); 5112 break; 5113 case OPC2_32_RC_MAX_U: 5114 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode)); 5115 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, 5116 cpu_gpr_d[r1], temp); 5117 break; 5118 case OPC2_32_RC_MIN: 5119 tcg_gen_movi_tl(temp, const9); 5120 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, 5121 cpu_gpr_d[r1], temp); 5122 break; 5123 case OPC2_32_RC_MIN_U: 5124 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode)); 5125 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, 5126 cpu_gpr_d[r1], temp); 5127 break; 5128 case OPC2_32_RC_NE: 5129 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5130 break; 5131 case OPC2_32_RC_OR_EQ: 5132 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], 5133 const9, &tcg_gen_or_tl); 5134 break; 5135 case OPC2_32_RC_OR_GE: 5136 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5137 const9, &tcg_gen_or_tl); 5138 break; 5139 case OPC2_32_RC_OR_GE_U: 5140 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5141 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5142 const9, &tcg_gen_or_tl); 5143 break; 5144 case OPC2_32_RC_OR_LT: 5145 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], 5146 const9, &tcg_gen_or_tl); 5147 break; 5148 case OPC2_32_RC_OR_LT_U: 5149 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5150 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5151 const9, &tcg_gen_or_tl); 5152 break; 5153 case OPC2_32_RC_OR_NE: 5154 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5155 const9, &tcg_gen_or_tl); 5156 break; 5157 case OPC2_32_RC_RSUB: 5158 tcg_gen_movi_tl(temp, const9); 5159 gen_sub_d(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]); 5160 break; 5161 case OPC2_32_RC_RSUBS: 5162 tcg_gen_movi_tl(temp, const9); 5163 gen_subs(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]); 5164 break; 5165 case OPC2_32_RC_RSUBS_U: 5166 tcg_gen_movi_tl(temp, const9); 5167 gen_subsu(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]); 5168 break; 5169 case OPC2_32_RC_SH_EQ: 5170 gen_sh_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5171 break; 5172 case OPC2_32_RC_SH_GE: 5173 gen_sh_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5174 break; 5175 case OPC2_32_RC_SH_GE_U: 5176 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5177 gen_sh_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5178 break; 5179 case OPC2_32_RC_SH_LT: 5180 gen_sh_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5181 break; 5182 case OPC2_32_RC_SH_LT_U: 5183 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5184 gen_sh_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5185 break; 5186 case OPC2_32_RC_SH_NE: 5187 gen_sh_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5188 break; 5189 case OPC2_32_RC_XOR_EQ: 5190 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], 5191 const9, &tcg_gen_xor_tl); 5192 break; 5193 case OPC2_32_RC_XOR_GE: 5194 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5195 const9, &tcg_gen_xor_tl); 5196 break; 5197 case OPC2_32_RC_XOR_GE_U: 5198 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5199 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5200 const9, &tcg_gen_xor_tl); 5201 break; 5202 case OPC2_32_RC_XOR_LT: 5203 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], 5204 const9, &tcg_gen_xor_tl); 5205 break; 5206 case OPC2_32_RC_XOR_LT_U: 5207 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5208 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5209 const9, &tcg_gen_xor_tl); 5210 break; 5211 case OPC2_32_RC_XOR_NE: 5212 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5213 const9, &tcg_gen_xor_tl); 5214 break; 5215 default: 5216 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5217 } 5218 } 5219 5220 static void decode_rc_serviceroutine(DisasContext *ctx) 5221 { 5222 uint32_t op2; 5223 uint32_t const9; 5224 5225 op2 = MASK_OP_RC_OP2(ctx->opcode); 5226 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5227 5228 switch (op2) { 5229 case OPC2_32_RC_BISR: 5230 if (ctx->priv == TRICORE_PRIV_SM) { 5231 gen_helper_1arg(bisr, const9); 5232 } else { 5233 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); 5234 } 5235 break; 5236 case OPC2_32_RC_SYSCALL: 5237 generate_trap(ctx, TRAPC_SYSCALL, const9 & 0xff); 5238 break; 5239 default: 5240 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5241 } 5242 } 5243 5244 static void decode_rc_mul(DisasContext *ctx) 5245 { 5246 uint32_t op2; 5247 int r1, r2; 5248 int16_t const9; 5249 5250 r2 = MASK_OP_RC_D(ctx->opcode); 5251 r1 = MASK_OP_RC_S1(ctx->opcode); 5252 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode); 5253 5254 op2 = MASK_OP_RC_OP2(ctx->opcode); 5255 5256 switch (op2) { 5257 case OPC2_32_RC_MUL_32: 5258 gen_muli_i32s(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5259 break; 5260 case OPC2_32_RC_MUL_64: 5261 CHECK_REG_PAIR(r2); 5262 gen_muli_i64s(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9); 5263 break; 5264 case OPC2_32_RC_MULS_32: 5265 gen_mulsi_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5266 break; 5267 case OPC2_32_RC_MUL_U_64: 5268 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5269 CHECK_REG_PAIR(r2); 5270 gen_muli_i64u(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9); 5271 break; 5272 case OPC2_32_RC_MULS_U_32: 5273 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5274 gen_mulsui_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5275 break; 5276 default: 5277 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5278 } 5279 } 5280 5281 /* RCPW format */ 5282 static void decode_rcpw_insert(DisasContext *ctx) 5283 { 5284 uint32_t op2; 5285 int r1, r2; 5286 int32_t pos, width, const4; 5287 5288 TCGv temp; 5289 5290 op2 = MASK_OP_RCPW_OP2(ctx->opcode); 5291 r1 = MASK_OP_RCPW_S1(ctx->opcode); 5292 r2 = MASK_OP_RCPW_D(ctx->opcode); 5293 const4 = MASK_OP_RCPW_CONST4(ctx->opcode); 5294 width = MASK_OP_RCPW_WIDTH(ctx->opcode); 5295 pos = MASK_OP_RCPW_POS(ctx->opcode); 5296 5297 switch (op2) { 5298 case OPC2_32_RCPW_IMASK: 5299 CHECK_REG_PAIR(r2); 5300 /* if pos + width > 32 undefined result */ 5301 if (pos + width <= 32) { 5302 tcg_gen_movi_tl(cpu_gpr_d[r2+1], ((1u << width) - 1) << pos); 5303 tcg_gen_movi_tl(cpu_gpr_d[r2], (const4 << pos)); 5304 } 5305 break; 5306 case OPC2_32_RCPW_INSERT: 5307 /* tcg_gen_deposit_tl() does not handle the case of width = 0 */ 5308 if (width == 0) { 5309 tcg_gen_mov_tl(cpu_gpr_d[r2], cpu_gpr_d[r1]); 5310 /* if pos + width > 32 undefined result */ 5311 } else if (pos + width <= 32) { 5312 temp = tcg_constant_i32(const4); 5313 tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, width); 5314 } 5315 break; 5316 default: 5317 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5318 } 5319 } 5320 5321 /* RCRW format */ 5322 5323 static void decode_rcrw_insert(DisasContext *ctx) 5324 { 5325 uint32_t op2; 5326 int r1, r3, r4; 5327 int32_t width, const4; 5328 5329 TCGv temp, temp2, temp3; 5330 5331 op2 = MASK_OP_RCRW_OP2(ctx->opcode); 5332 r1 = MASK_OP_RCRW_S1(ctx->opcode); 5333 r3 = MASK_OP_RCRW_S3(ctx->opcode); 5334 r4 = MASK_OP_RCRW_D(ctx->opcode); 5335 width = MASK_OP_RCRW_WIDTH(ctx->opcode); 5336 const4 = MASK_OP_RCRW_CONST4(ctx->opcode); 5337 5338 temp = tcg_temp_new(); 5339 temp2 = tcg_temp_new(); 5340 5341 switch (op2) { 5342 case OPC2_32_RCRW_IMASK: 5343 CHECK_REG_PAIR(r4); 5344 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); 5345 tcg_gen_movi_tl(temp2, (1 << width) - 1); 5346 tcg_gen_shl_tl(cpu_gpr_d[r4 + 1], temp2, temp); 5347 tcg_gen_movi_tl(temp2, const4); 5348 tcg_gen_shl_tl(cpu_gpr_d[r4], temp2, temp); 5349 break; 5350 case OPC2_32_RCRW_INSERT: 5351 temp3 = tcg_temp_new(); 5352 5353 tcg_gen_movi_tl(temp, width); 5354 tcg_gen_movi_tl(temp2, const4); 5355 tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f); 5356 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], temp2, temp, temp3); 5357 break; 5358 default: 5359 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5360 } 5361 } 5362 5363 /* RCR format */ 5364 5365 static void decode_rcr_cond_select(DisasContext *ctx) 5366 { 5367 uint32_t op2; 5368 int r1, r3, r4; 5369 int32_t const9; 5370 5371 TCGv temp, temp2; 5372 5373 op2 = MASK_OP_RCR_OP2(ctx->opcode); 5374 r1 = MASK_OP_RCR_S1(ctx->opcode); 5375 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode); 5376 r3 = MASK_OP_RCR_S3(ctx->opcode); 5377 r4 = MASK_OP_RCR_D(ctx->opcode); 5378 5379 switch (op2) { 5380 case OPC2_32_RCR_CADD: 5381 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const9, cpu_gpr_d[r4], 5382 cpu_gpr_d[r3]); 5383 break; 5384 case OPC2_32_RCR_CADDN: 5385 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const9, cpu_gpr_d[r4], 5386 cpu_gpr_d[r3]); 5387 break; 5388 case OPC2_32_RCR_SEL: 5389 temp = tcg_constant_i32(0); 5390 temp2 = tcg_constant_i32(const9); 5391 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, 5392 cpu_gpr_d[r1], temp2); 5393 break; 5394 case OPC2_32_RCR_SELN: 5395 temp = tcg_constant_i32(0); 5396 temp2 = tcg_constant_i32(const9); 5397 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, 5398 cpu_gpr_d[r1], temp2); 5399 break; 5400 default: 5401 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5402 } 5403 } 5404 5405 static void decode_rcr_madd(DisasContext *ctx) 5406 { 5407 uint32_t op2; 5408 int r1, r3, r4; 5409 int32_t const9; 5410 5411 5412 op2 = MASK_OP_RCR_OP2(ctx->opcode); 5413 r1 = MASK_OP_RCR_S1(ctx->opcode); 5414 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode); 5415 r3 = MASK_OP_RCR_S3(ctx->opcode); 5416 r4 = MASK_OP_RCR_D(ctx->opcode); 5417 5418 switch (op2) { 5419 case OPC2_32_RCR_MADD_32: 5420 gen_maddi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5421 break; 5422 case OPC2_32_RCR_MADD_64: 5423 CHECK_REG_PAIR(r4); 5424 CHECK_REG_PAIR(r3); 5425 gen_maddi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5426 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5427 break; 5428 case OPC2_32_RCR_MADDS_32: 5429 gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5430 break; 5431 case OPC2_32_RCR_MADDS_64: 5432 CHECK_REG_PAIR(r4); 5433 CHECK_REG_PAIR(r3); 5434 gen_maddsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5435 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5436 break; 5437 case OPC2_32_RCR_MADD_U_64: 5438 CHECK_REG_PAIR(r4); 5439 CHECK_REG_PAIR(r3); 5440 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5441 gen_maddui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5442 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5443 break; 5444 case OPC2_32_RCR_MADDS_U_32: 5445 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5446 gen_maddsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5447 break; 5448 case OPC2_32_RCR_MADDS_U_64: 5449 CHECK_REG_PAIR(r4); 5450 CHECK_REG_PAIR(r3); 5451 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5452 gen_maddsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5453 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5454 break; 5455 default: 5456 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5457 } 5458 } 5459 5460 static void decode_rcr_msub(DisasContext *ctx) 5461 { 5462 uint32_t op2; 5463 int r1, r3, r4; 5464 int32_t const9; 5465 5466 5467 op2 = MASK_OP_RCR_OP2(ctx->opcode); 5468 r1 = MASK_OP_RCR_S1(ctx->opcode); 5469 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode); 5470 r3 = MASK_OP_RCR_S3(ctx->opcode); 5471 r4 = MASK_OP_RCR_D(ctx->opcode); 5472 5473 switch (op2) { 5474 case OPC2_32_RCR_MSUB_32: 5475 gen_msubi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5476 break; 5477 case OPC2_32_RCR_MSUB_64: 5478 CHECK_REG_PAIR(r4); 5479 CHECK_REG_PAIR(r3); 5480 gen_msubi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5481 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5482 break; 5483 case OPC2_32_RCR_MSUBS_32: 5484 gen_msubsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5485 break; 5486 case OPC2_32_RCR_MSUBS_64: 5487 CHECK_REG_PAIR(r4); 5488 CHECK_REG_PAIR(r3); 5489 gen_msubsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5490 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5491 break; 5492 case OPC2_32_RCR_MSUB_U_64: 5493 CHECK_REG_PAIR(r4); 5494 CHECK_REG_PAIR(r3); 5495 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5496 gen_msubui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5497 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5498 break; 5499 case OPC2_32_RCR_MSUBS_U_32: 5500 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5501 gen_msubsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5502 break; 5503 case OPC2_32_RCR_MSUBS_U_64: 5504 CHECK_REG_PAIR(r4); 5505 CHECK_REG_PAIR(r3); 5506 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5507 gen_msubsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5508 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5509 break; 5510 default: 5511 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5512 } 5513 } 5514 5515 /* RLC format */ 5516 5517 static void decode_rlc_opc(DisasContext *ctx, 5518 uint32_t op1) 5519 { 5520 int32_t const16; 5521 int r1, r2; 5522 5523 const16 = MASK_OP_RLC_CONST16_SEXT(ctx->opcode); 5524 r1 = MASK_OP_RLC_S1(ctx->opcode); 5525 r2 = MASK_OP_RLC_D(ctx->opcode); 5526 5527 switch (op1) { 5528 case OPC1_32_RLC_ADDI: 5529 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16); 5530 break; 5531 case OPC1_32_RLC_ADDIH: 5532 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16 << 16); 5533 break; 5534 case OPC1_32_RLC_ADDIH_A: 5535 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r1], const16 << 16); 5536 break; 5537 case OPC1_32_RLC_MFCR: 5538 const16 = MASK_OP_RLC_CONST16(ctx->opcode); 5539 gen_mfcr(ctx, cpu_gpr_d[r2], const16); 5540 break; 5541 case OPC1_32_RLC_MOV: 5542 tcg_gen_movi_tl(cpu_gpr_d[r2], const16); 5543 break; 5544 case OPC1_32_RLC_MOV_64: 5545 if (has_feature(ctx, TRICORE_FEATURE_16)) { 5546 CHECK_REG_PAIR(r2); 5547 tcg_gen_movi_tl(cpu_gpr_d[r2], const16); 5548 tcg_gen_movi_tl(cpu_gpr_d[r2+1], const16 >> 15); 5549 } else { 5550 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5551 } 5552 break; 5553 case OPC1_32_RLC_MOV_U: 5554 const16 = MASK_OP_RLC_CONST16(ctx->opcode); 5555 tcg_gen_movi_tl(cpu_gpr_d[r2], const16); 5556 break; 5557 case OPC1_32_RLC_MOV_H: 5558 tcg_gen_movi_tl(cpu_gpr_d[r2], const16 << 16); 5559 break; 5560 case OPC1_32_RLC_MOVH_A: 5561 tcg_gen_movi_tl(cpu_gpr_a[r2], const16 << 16); 5562 break; 5563 case OPC1_32_RLC_MTCR: 5564 const16 = MASK_OP_RLC_CONST16(ctx->opcode); 5565 gen_mtcr(ctx, cpu_gpr_d[r1], const16); 5566 break; 5567 default: 5568 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5569 } 5570 } 5571 5572 /* RR format */ 5573 static void decode_rr_accumulator(DisasContext *ctx) 5574 { 5575 uint32_t op2; 5576 int r3, r2, r1; 5577 5578 TCGv temp; 5579 5580 r3 = MASK_OP_RR_D(ctx->opcode); 5581 r2 = MASK_OP_RR_S2(ctx->opcode); 5582 r1 = MASK_OP_RR_S1(ctx->opcode); 5583 op2 = MASK_OP_RR_OP2(ctx->opcode); 5584 5585 switch (op2) { 5586 case OPC2_32_RR_ABS: 5587 gen_abs(cpu_gpr_d[r3], cpu_gpr_d[r2]); 5588 break; 5589 case OPC2_32_RR_ABS_B: 5590 gen_helper_abs_b(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r2]); 5591 break; 5592 case OPC2_32_RR_ABS_H: 5593 gen_helper_abs_h(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r2]); 5594 break; 5595 case OPC2_32_RR_ABSDIF: 5596 gen_absdif(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5597 break; 5598 case OPC2_32_RR_ABSDIF_B: 5599 gen_helper_absdif_b(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], 5600 cpu_gpr_d[r2]); 5601 break; 5602 case OPC2_32_RR_ABSDIF_H: 5603 gen_helper_absdif_h(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], 5604 cpu_gpr_d[r2]); 5605 break; 5606 case OPC2_32_RR_ABSDIFS: 5607 gen_helper_absdif_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], 5608 cpu_gpr_d[r2]); 5609 break; 5610 case OPC2_32_RR_ABSDIFS_H: 5611 gen_helper_absdif_h_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], 5612 cpu_gpr_d[r2]); 5613 break; 5614 case OPC2_32_RR_ABSS: 5615 gen_helper_abs_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r2]); 5616 break; 5617 case OPC2_32_RR_ABSS_H: 5618 gen_helper_abs_h_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r2]); 5619 break; 5620 case OPC2_32_RR_ADD: 5621 gen_add_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5622 break; 5623 case OPC2_32_RR_ADD_B: 5624 gen_helper_add_b(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 5625 break; 5626 case OPC2_32_RR_ADD_H: 5627 gen_helper_add_h(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 5628 break; 5629 case OPC2_32_RR_ADDC: 5630 gen_addc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5631 break; 5632 case OPC2_32_RR_ADDS: 5633 gen_adds(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5634 break; 5635 case OPC2_32_RR_ADDS_H: 5636 gen_helper_add_h_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], 5637 cpu_gpr_d[r2]); 5638 break; 5639 case OPC2_32_RR_ADDS_HU: 5640 gen_helper_add_h_suov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], 5641 cpu_gpr_d[r2]); 5642 break; 5643 case OPC2_32_RR_ADDS_U: 5644 gen_helper_add_suov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], 5645 cpu_gpr_d[r2]); 5646 break; 5647 case OPC2_32_RR_ADDX: 5648 gen_add_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5649 break; 5650 case OPC2_32_RR_AND_EQ: 5651 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 5652 cpu_gpr_d[r2], &tcg_gen_and_tl); 5653 break; 5654 case OPC2_32_RR_AND_GE: 5655 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5656 cpu_gpr_d[r2], &tcg_gen_and_tl); 5657 break; 5658 case OPC2_32_RR_AND_GE_U: 5659 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5660 cpu_gpr_d[r2], &tcg_gen_and_tl); 5661 break; 5662 case OPC2_32_RR_AND_LT: 5663 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5664 cpu_gpr_d[r2], &tcg_gen_and_tl); 5665 break; 5666 case OPC2_32_RR_AND_LT_U: 5667 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5668 cpu_gpr_d[r2], &tcg_gen_and_tl); 5669 break; 5670 case OPC2_32_RR_AND_NE: 5671 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5672 cpu_gpr_d[r2], &tcg_gen_and_tl); 5673 break; 5674 case OPC2_32_RR_EQ: 5675 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 5676 cpu_gpr_d[r2]); 5677 break; 5678 case OPC2_32_RR_EQ_B: 5679 gen_helper_eq_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5680 break; 5681 case OPC2_32_RR_EQ_H: 5682 gen_helper_eq_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5683 break; 5684 case OPC2_32_RR_EQ_W: 5685 tcg_gen_negsetcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], 5686 cpu_gpr_d[r1], cpu_gpr_d[r2]); 5687 break; 5688 case OPC2_32_RR_EQANY_B: 5689 gen_helper_eqany_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5690 break; 5691 case OPC2_32_RR_EQANY_H: 5692 gen_helper_eqany_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5693 break; 5694 case OPC2_32_RR_GE: 5695 tcg_gen_setcond_tl(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5696 cpu_gpr_d[r2]); 5697 break; 5698 case OPC2_32_RR_GE_U: 5699 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5700 cpu_gpr_d[r2]); 5701 break; 5702 case OPC2_32_RR_LT: 5703 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5704 cpu_gpr_d[r2]); 5705 break; 5706 case OPC2_32_RR_LT_U: 5707 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5708 cpu_gpr_d[r2]); 5709 break; 5710 case OPC2_32_RR_LT_B: 5711 gen_helper_lt_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5712 break; 5713 case OPC2_32_RR_LT_BU: 5714 gen_helper_lt_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5715 break; 5716 case OPC2_32_RR_LT_H: 5717 gen_helper_lt_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5718 break; 5719 case OPC2_32_RR_LT_HU: 5720 gen_helper_lt_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5721 break; 5722 case OPC2_32_RR_LT_W: 5723 tcg_gen_negsetcond_tl(TCG_COND_LT, cpu_gpr_d[r3], 5724 cpu_gpr_d[r1], cpu_gpr_d[r2]); 5725 break; 5726 case OPC2_32_RR_LT_WU: 5727 tcg_gen_negsetcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], 5728 cpu_gpr_d[r1], cpu_gpr_d[r2]); 5729 break; 5730 case OPC2_32_RR_MAX: 5731 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5732 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5733 break; 5734 case OPC2_32_RR_MAX_U: 5735 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5736 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5737 break; 5738 case OPC2_32_RR_MAX_B: 5739 gen_helper_max_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5740 break; 5741 case OPC2_32_RR_MAX_BU: 5742 gen_helper_max_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5743 break; 5744 case OPC2_32_RR_MAX_H: 5745 gen_helper_max_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5746 break; 5747 case OPC2_32_RR_MAX_HU: 5748 gen_helper_max_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5749 break; 5750 case OPC2_32_RR_MIN: 5751 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5752 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5753 break; 5754 case OPC2_32_RR_MIN_U: 5755 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5756 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5757 break; 5758 case OPC2_32_RR_MIN_B: 5759 gen_helper_min_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5760 break; 5761 case OPC2_32_RR_MIN_BU: 5762 gen_helper_min_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5763 break; 5764 case OPC2_32_RR_MIN_H: 5765 gen_helper_min_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5766 break; 5767 case OPC2_32_RR_MIN_HU: 5768 gen_helper_min_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5769 break; 5770 case OPC2_32_RR_MOV: 5771 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); 5772 break; 5773 case OPC2_32_RR_MOV_64: 5774 if (has_feature(ctx, TRICORE_FEATURE_16)) { 5775 temp = tcg_temp_new(); 5776 5777 CHECK_REG_PAIR(r3); 5778 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 5779 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); 5780 tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp); 5781 } else { 5782 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5783 } 5784 break; 5785 case OPC2_32_RR_MOVS_64: 5786 if (has_feature(ctx, TRICORE_FEATURE_16)) { 5787 CHECK_REG_PAIR(r3); 5788 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); 5789 tcg_gen_sari_tl(cpu_gpr_d[r3 + 1], cpu_gpr_d[r2], 31); 5790 } else { 5791 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5792 } 5793 break; 5794 case OPC2_32_RR_NE: 5795 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5796 cpu_gpr_d[r2]); 5797 break; 5798 case OPC2_32_RR_OR_EQ: 5799 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 5800 cpu_gpr_d[r2], &tcg_gen_or_tl); 5801 break; 5802 case OPC2_32_RR_OR_GE: 5803 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5804 cpu_gpr_d[r2], &tcg_gen_or_tl); 5805 break; 5806 case OPC2_32_RR_OR_GE_U: 5807 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5808 cpu_gpr_d[r2], &tcg_gen_or_tl); 5809 break; 5810 case OPC2_32_RR_OR_LT: 5811 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5812 cpu_gpr_d[r2], &tcg_gen_or_tl); 5813 break; 5814 case OPC2_32_RR_OR_LT_U: 5815 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5816 cpu_gpr_d[r2], &tcg_gen_or_tl); 5817 break; 5818 case OPC2_32_RR_OR_NE: 5819 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5820 cpu_gpr_d[r2], &tcg_gen_or_tl); 5821 break; 5822 case OPC2_32_RR_SAT_B: 5823 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7f, -0x80); 5824 break; 5825 case OPC2_32_RR_SAT_BU: 5826 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xff); 5827 break; 5828 case OPC2_32_RR_SAT_H: 5829 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7fff, -0x8000); 5830 break; 5831 case OPC2_32_RR_SAT_HU: 5832 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xffff); 5833 break; 5834 case OPC2_32_RR_SH_EQ: 5835 gen_sh_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 5836 cpu_gpr_d[r2]); 5837 break; 5838 case OPC2_32_RR_SH_GE: 5839 gen_sh_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5840 cpu_gpr_d[r2]); 5841 break; 5842 case OPC2_32_RR_SH_GE_U: 5843 gen_sh_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5844 cpu_gpr_d[r2]); 5845 break; 5846 case OPC2_32_RR_SH_LT: 5847 gen_sh_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5848 cpu_gpr_d[r2]); 5849 break; 5850 case OPC2_32_RR_SH_LT_U: 5851 gen_sh_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5852 cpu_gpr_d[r2]); 5853 break; 5854 case OPC2_32_RR_SH_NE: 5855 gen_sh_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5856 cpu_gpr_d[r2]); 5857 break; 5858 case OPC2_32_RR_SUB: 5859 gen_sub_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5860 break; 5861 case OPC2_32_RR_SUB_B: 5862 gen_helper_sub_b(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 5863 break; 5864 case OPC2_32_RR_SUB_H: 5865 gen_helper_sub_h(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 5866 break; 5867 case OPC2_32_RR_SUBC: 5868 gen_subc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5869 break; 5870 case OPC2_32_RR_SUBS: 5871 gen_subs(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5872 break; 5873 case OPC2_32_RR_SUBS_U: 5874 gen_subsu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5875 break; 5876 case OPC2_32_RR_SUBS_H: 5877 gen_helper_sub_h_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], 5878 cpu_gpr_d[r2]); 5879 break; 5880 case OPC2_32_RR_SUBS_HU: 5881 gen_helper_sub_h_suov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], 5882 cpu_gpr_d[r2]); 5883 break; 5884 case OPC2_32_RR_SUBX: 5885 gen_sub_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5886 break; 5887 case OPC2_32_RR_XOR_EQ: 5888 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 5889 cpu_gpr_d[r2], &tcg_gen_xor_tl); 5890 break; 5891 case OPC2_32_RR_XOR_GE: 5892 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5893 cpu_gpr_d[r2], &tcg_gen_xor_tl); 5894 break; 5895 case OPC2_32_RR_XOR_GE_U: 5896 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5897 cpu_gpr_d[r2], &tcg_gen_xor_tl); 5898 break; 5899 case OPC2_32_RR_XOR_LT: 5900 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5901 cpu_gpr_d[r2], &tcg_gen_xor_tl); 5902 break; 5903 case OPC2_32_RR_XOR_LT_U: 5904 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5905 cpu_gpr_d[r2], &tcg_gen_xor_tl); 5906 break; 5907 case OPC2_32_RR_XOR_NE: 5908 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5909 cpu_gpr_d[r2], &tcg_gen_xor_tl); 5910 break; 5911 default: 5912 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5913 } 5914 } 5915 5916 static void decode_rr_logical_shift(DisasContext *ctx) 5917 { 5918 uint32_t op2; 5919 int r3, r2, r1; 5920 5921 r3 = MASK_OP_RR_D(ctx->opcode); 5922 r2 = MASK_OP_RR_S2(ctx->opcode); 5923 r1 = MASK_OP_RR_S1(ctx->opcode); 5924 op2 = MASK_OP_RR_OP2(ctx->opcode); 5925 5926 switch (op2) { 5927 case OPC2_32_RR_AND: 5928 tcg_gen_and_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5929 break; 5930 case OPC2_32_RR_ANDN: 5931 tcg_gen_andc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5932 break; 5933 case OPC2_32_RR_CLO: 5934 tcg_gen_not_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 5935 tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], TARGET_LONG_BITS); 5936 break; 5937 case OPC2_32_RR_CLO_H: 5938 gen_helper_clo_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); 5939 break; 5940 case OPC2_32_RR_CLS: 5941 tcg_gen_clrsb_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 5942 break; 5943 case OPC2_32_RR_CLS_H: 5944 gen_helper_cls_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); 5945 break; 5946 case OPC2_32_RR_CLZ: 5947 tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], TARGET_LONG_BITS); 5948 break; 5949 case OPC2_32_RR_CLZ_H: 5950 gen_helper_clz_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); 5951 break; 5952 case OPC2_32_RR_NAND: 5953 tcg_gen_nand_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5954 break; 5955 case OPC2_32_RR_NOR: 5956 tcg_gen_nor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5957 break; 5958 case OPC2_32_RR_OR: 5959 tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5960 break; 5961 case OPC2_32_RR_ORN: 5962 tcg_gen_orc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5963 break; 5964 case OPC2_32_RR_SH: 5965 gen_helper_sh(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5966 break; 5967 case OPC2_32_RR_SH_H: 5968 gen_helper_sh_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5969 break; 5970 case OPC2_32_RR_SHA: 5971 gen_helper_sha(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 5972 break; 5973 case OPC2_32_RR_SHA_H: 5974 gen_helper_sha_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5975 break; 5976 case OPC2_32_RR_SHAS: 5977 gen_shas(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5978 break; 5979 case OPC2_32_RR_XNOR: 5980 tcg_gen_eqv_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5981 break; 5982 case OPC2_32_RR_XOR: 5983 tcg_gen_xor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5984 break; 5985 default: 5986 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5987 } 5988 } 5989 5990 static void decode_rr_address(DisasContext *ctx) 5991 { 5992 uint32_t op2, n; 5993 int r1, r2, r3; 5994 TCGv temp; 5995 5996 op2 = MASK_OP_RR_OP2(ctx->opcode); 5997 r3 = MASK_OP_RR_D(ctx->opcode); 5998 r2 = MASK_OP_RR_S2(ctx->opcode); 5999 r1 = MASK_OP_RR_S1(ctx->opcode); 6000 n = MASK_OP_RR_N(ctx->opcode); 6001 6002 switch (op2) { 6003 case OPC2_32_RR_ADD_A: 6004 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]); 6005 break; 6006 case OPC2_32_RR_ADDSC_A: 6007 temp = tcg_temp_new(); 6008 tcg_gen_shli_tl(temp, cpu_gpr_d[r1], n); 6009 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r2], temp); 6010 break; 6011 case OPC2_32_RR_ADDSC_AT: 6012 temp = tcg_temp_new(); 6013 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 3); 6014 tcg_gen_add_tl(temp, cpu_gpr_a[r2], temp); 6015 tcg_gen_andi_tl(cpu_gpr_a[r3], temp, 0xFFFFFFFC); 6016 break; 6017 case OPC2_32_RR_EQ_A: 6018 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], 6019 cpu_gpr_a[r2]); 6020 break; 6021 case OPC2_32_RR_EQZ: 6022 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], 0); 6023 break; 6024 case OPC2_32_RR_GE_A: 6025 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_a[r1], 6026 cpu_gpr_a[r2]); 6027 break; 6028 case OPC2_32_RR_LT_A: 6029 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_a[r1], 6030 cpu_gpr_a[r2]); 6031 break; 6032 case OPC2_32_RR_MOV_A: 6033 tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_d[r2]); 6034 break; 6035 case OPC2_32_RR_MOV_AA: 6036 tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_a[r2]); 6037 break; 6038 case OPC2_32_RR_MOV_D: 6039 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_a[r2]); 6040 break; 6041 case OPC2_32_RR_NE_A: 6042 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1], 6043 cpu_gpr_a[r2]); 6044 break; 6045 case OPC2_32_RR_NEZ_A: 6046 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1], 0); 6047 break; 6048 case OPC2_32_RR_SUB_A: 6049 tcg_gen_sub_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]); 6050 break; 6051 default: 6052 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6053 } 6054 } 6055 6056 static void decode_rr_idirect(DisasContext *ctx) 6057 { 6058 uint32_t op2; 6059 int r1; 6060 6061 op2 = MASK_OP_RR_OP2(ctx->opcode); 6062 r1 = MASK_OP_RR_S1(ctx->opcode); 6063 6064 switch (op2) { 6065 case OPC2_32_RR_JI: 6066 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); 6067 break; 6068 case OPC2_32_RR_JLI: 6069 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); 6070 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); 6071 break; 6072 case OPC2_32_RR_CALLI: 6073 gen_helper_1arg(call, ctx->pc_succ_insn); 6074 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); 6075 break; 6076 case OPC2_32_RR_FCALLI: 6077 gen_fcall_save_ctx(ctx); 6078 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); 6079 break; 6080 default: 6081 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6082 return; 6083 } 6084 ctx->base.is_jmp = DISAS_JUMP; 6085 } 6086 6087 static void decode_rr_divide(DisasContext *ctx) 6088 { 6089 uint32_t op2; 6090 int r1, r2, r3; 6091 6092 TCGv temp, temp2, temp3; 6093 6094 op2 = MASK_OP_RR_OP2(ctx->opcode); 6095 r3 = MASK_OP_RR_D(ctx->opcode); 6096 r2 = MASK_OP_RR_S2(ctx->opcode); 6097 r1 = MASK_OP_RR_S1(ctx->opcode); 6098 6099 switch (op2) { 6100 case OPC2_32_RR_BMERGE: 6101 gen_helper_bmerge(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6102 break; 6103 case OPC2_32_RR_BSPLIT: 6104 CHECK_REG_PAIR(r3); 6105 gen_bsplit(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]); 6106 break; 6107 case OPC2_32_RR_DVINIT_B: 6108 CHECK_REG_PAIR(r3); 6109 gen_dvinit_b(ctx, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6110 cpu_gpr_d[r2]); 6111 break; 6112 case OPC2_32_RR_DVINIT_BU: 6113 temp = tcg_temp_new(); 6114 temp2 = tcg_temp_new(); 6115 temp3 = tcg_temp_new(); 6116 CHECK_REG_PAIR(r3); 6117 tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 8); 6118 /* reset av */ 6119 tcg_gen_movi_tl(cpu_PSW_AV, 0); 6120 if (!has_feature(ctx, TRICORE_FEATURE_131)) { 6121 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */ 6122 tcg_gen_abs_tl(temp, temp3); 6123 tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]); 6124 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2); 6125 } else { 6126 /* overflow = (D[b] == 0) */ 6127 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0); 6128 } 6129 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 6130 /* sv */ 6131 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 6132 /* write result */ 6133 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 24); 6134 tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3); 6135 break; 6136 case OPC2_32_RR_DVINIT_H: 6137 CHECK_REG_PAIR(r3); 6138 gen_dvinit_h(ctx, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6139 cpu_gpr_d[r2]); 6140 break; 6141 case OPC2_32_RR_DVINIT_HU: 6142 temp = tcg_temp_new(); 6143 temp2 = tcg_temp_new(); 6144 temp3 = tcg_temp_new(); 6145 CHECK_REG_PAIR(r3); 6146 tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 16); 6147 /* reset av */ 6148 tcg_gen_movi_tl(cpu_PSW_AV, 0); 6149 if (!has_feature(ctx, TRICORE_FEATURE_131)) { 6150 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */ 6151 tcg_gen_abs_tl(temp, temp3); 6152 tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]); 6153 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2); 6154 } else { 6155 /* overflow = (D[b] == 0) */ 6156 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0); 6157 } 6158 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 6159 /* sv */ 6160 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 6161 /* write result */ 6162 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 16); 6163 tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3); 6164 break; 6165 case OPC2_32_RR_DVINIT: 6166 temp = tcg_temp_new(); 6167 temp2 = tcg_temp_new(); 6168 CHECK_REG_PAIR(r3); 6169 /* overflow = ((D[b] == 0) || 6170 ((D[b] == 0xFFFFFFFF) && (D[a] == 0x80000000))) */ 6171 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, cpu_gpr_d[r2], 0xffffffff); 6172 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r1], 0x80000000); 6173 tcg_gen_and_tl(temp, temp, temp2); 6174 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r2], 0); 6175 tcg_gen_or_tl(cpu_PSW_V, temp, temp2); 6176 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 6177 /* sv */ 6178 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 6179 /* reset av */ 6180 tcg_gen_movi_tl(cpu_PSW_AV, 0); 6181 /* write result */ 6182 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6183 /* sign extend to high reg */ 6184 tcg_gen_sari_tl(cpu_gpr_d[r3+1], cpu_gpr_d[r1], 31); 6185 break; 6186 case OPC2_32_RR_DVINIT_U: 6187 CHECK_REG_PAIR(r3); 6188 /* overflow = (D[b] == 0) */ 6189 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0); 6190 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 6191 /* sv */ 6192 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 6193 /* reset av */ 6194 tcg_gen_movi_tl(cpu_PSW_AV, 0); 6195 /* write result */ 6196 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6197 /* zero extend to high reg*/ 6198 tcg_gen_movi_tl(cpu_gpr_d[r3+1], 0); 6199 break; 6200 case OPC2_32_RR_PARITY: 6201 gen_helper_parity(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6202 break; 6203 case OPC2_32_RR_UNPACK: 6204 CHECK_REG_PAIR(r3); 6205 gen_unpack(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]); 6206 break; 6207 case OPC2_32_RR_CRC32_B: 6208 if (has_feature(ctx, TRICORE_FEATURE_162)) { 6209 gen_helper_crc32b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6210 } else { 6211 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6212 } 6213 break; 6214 case OPC2_32_RR_CRC32: /* CRC32B.W in 1.6.2 */ 6215 if (has_feature(ctx, TRICORE_FEATURE_161)) { 6216 gen_helper_crc32_be(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6217 } else { 6218 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6219 } 6220 break; 6221 case OPC2_32_RR_CRC32L_W: 6222 if (has_feature(ctx, TRICORE_FEATURE_162)) { 6223 gen_helper_crc32_le(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6224 } else { 6225 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6226 } 6227 break; 6228 6229 case OPC2_32_RR_POPCNT_W: 6230 if (has_feature(ctx, TRICORE_FEATURE_162)) { 6231 tcg_gen_ctpop_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6232 } else { 6233 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6234 } 6235 break; 6236 case OPC2_32_RR_DIV: 6237 if (has_feature(ctx, TRICORE_FEATURE_16)) { 6238 CHECK_REG_PAIR(r3); 6239 GEN_HELPER_RR(divide, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6240 cpu_gpr_d[r2]); 6241 } else { 6242 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6243 } 6244 break; 6245 case OPC2_32_RR_DIV_U: 6246 if (has_feature(ctx, TRICORE_FEATURE_16)) { 6247 CHECK_REG_PAIR(r3); 6248 GEN_HELPER_RR(divide_u, cpu_gpr_d[r3], cpu_gpr_d[r3+1], 6249 cpu_gpr_d[r1], cpu_gpr_d[r2]); 6250 } else { 6251 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6252 } 6253 break; 6254 case OPC2_32_RR_MUL_F: 6255 gen_helper_fmul(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6256 break; 6257 case OPC2_32_RR_DIV_F: 6258 gen_helper_fdiv(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6259 break; 6260 case OPC2_32_RR_FTOHP: 6261 if (has_feature(ctx, TRICORE_FEATURE_162)) { 6262 gen_helper_ftohp(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); 6263 } else { 6264 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6265 } 6266 break; 6267 case OPC2_32_RR_HPTOF: 6268 if (has_feature(ctx, TRICORE_FEATURE_162)) { 6269 gen_helper_hptof(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); 6270 } else { 6271 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6272 } 6273 break; 6274 case OPC2_32_RR_CMP_F: 6275 gen_helper_fcmp(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6276 break; 6277 case OPC2_32_RR_FTOI: 6278 gen_helper_ftoi(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); 6279 break; 6280 case OPC2_32_RR_ITOF: 6281 gen_helper_itof(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); 6282 break; 6283 case OPC2_32_RR_FTOU: 6284 gen_helper_ftou(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); 6285 break; 6286 case OPC2_32_RR_FTOUZ: 6287 if (has_feature(ctx, TRICORE_FEATURE_131)) { 6288 gen_helper_ftouz(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); 6289 } else { 6290 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6291 } 6292 break; 6293 case OPC2_32_RR_UPDFL: 6294 gen_helper_updfl(tcg_env, cpu_gpr_d[r1]); 6295 break; 6296 case OPC2_32_RR_UTOF: 6297 gen_helper_utof(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); 6298 break; 6299 case OPC2_32_RR_FTOIZ: 6300 gen_helper_ftoiz(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); 6301 break; 6302 case OPC2_32_RR_QSEED_F: 6303 gen_helper_qseed(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); 6304 break; 6305 default: 6306 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6307 } 6308 } 6309 6310 /* RR1 Format */ 6311 static void decode_rr1_mul(DisasContext *ctx) 6312 { 6313 uint32_t op2; 6314 6315 int r1, r2, r3; 6316 TCGv n; 6317 TCGv_i64 temp64; 6318 6319 r1 = MASK_OP_RR1_S1(ctx->opcode); 6320 r2 = MASK_OP_RR1_S2(ctx->opcode); 6321 r3 = MASK_OP_RR1_D(ctx->opcode); 6322 n = tcg_constant_i32(MASK_OP_RR1_N(ctx->opcode)); 6323 op2 = MASK_OP_RR1_OP2(ctx->opcode); 6324 6325 switch (op2) { 6326 case OPC2_32_RR1_MUL_H_32_LL: 6327 temp64 = tcg_temp_new_i64(); 6328 CHECK_REG_PAIR(r3); 6329 GEN_HELPER_LL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6330 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6331 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); 6332 break; 6333 case OPC2_32_RR1_MUL_H_32_LU: 6334 temp64 = tcg_temp_new_i64(); 6335 CHECK_REG_PAIR(r3); 6336 GEN_HELPER_LU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6337 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6338 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); 6339 break; 6340 case OPC2_32_RR1_MUL_H_32_UL: 6341 temp64 = tcg_temp_new_i64(); 6342 CHECK_REG_PAIR(r3); 6343 GEN_HELPER_UL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6344 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6345 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); 6346 break; 6347 case OPC2_32_RR1_MUL_H_32_UU: 6348 temp64 = tcg_temp_new_i64(); 6349 CHECK_REG_PAIR(r3); 6350 GEN_HELPER_UU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6351 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6352 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); 6353 break; 6354 case OPC2_32_RR1_MULM_H_64_LL: 6355 temp64 = tcg_temp_new_i64(); 6356 CHECK_REG_PAIR(r3); 6357 GEN_HELPER_LL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6358 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6359 /* reset V bit */ 6360 tcg_gen_movi_tl(cpu_PSW_V, 0); 6361 /* reset AV bit */ 6362 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 6363 break; 6364 case OPC2_32_RR1_MULM_H_64_LU: 6365 temp64 = tcg_temp_new_i64(); 6366 CHECK_REG_PAIR(r3); 6367 GEN_HELPER_LU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6368 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6369 /* reset V bit */ 6370 tcg_gen_movi_tl(cpu_PSW_V, 0); 6371 /* reset AV bit */ 6372 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 6373 break; 6374 case OPC2_32_RR1_MULM_H_64_UL: 6375 temp64 = tcg_temp_new_i64(); 6376 CHECK_REG_PAIR(r3); 6377 GEN_HELPER_UL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6378 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6379 /* reset V bit */ 6380 tcg_gen_movi_tl(cpu_PSW_V, 0); 6381 /* reset AV bit */ 6382 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 6383 break; 6384 case OPC2_32_RR1_MULM_H_64_UU: 6385 temp64 = tcg_temp_new_i64(); 6386 CHECK_REG_PAIR(r3); 6387 GEN_HELPER_UU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6388 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6389 /* reset V bit */ 6390 tcg_gen_movi_tl(cpu_PSW_V, 0); 6391 /* reset AV bit */ 6392 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 6393 break; 6394 case OPC2_32_RR1_MULR_H_16_LL: 6395 GEN_HELPER_LL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6396 gen_calc_usb_mulr_h(cpu_gpr_d[r3]); 6397 break; 6398 case OPC2_32_RR1_MULR_H_16_LU: 6399 GEN_HELPER_LU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6400 gen_calc_usb_mulr_h(cpu_gpr_d[r3]); 6401 break; 6402 case OPC2_32_RR1_MULR_H_16_UL: 6403 GEN_HELPER_UL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6404 gen_calc_usb_mulr_h(cpu_gpr_d[r3]); 6405 break; 6406 case OPC2_32_RR1_MULR_H_16_UU: 6407 GEN_HELPER_UU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6408 gen_calc_usb_mulr_h(cpu_gpr_d[r3]); 6409 break; 6410 default: 6411 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6412 } 6413 } 6414 6415 static void decode_rr1_mulq(DisasContext *ctx) 6416 { 6417 uint32_t op2; 6418 int r1, r2, r3; 6419 uint32_t n; 6420 6421 TCGv temp, temp2; 6422 6423 r1 = MASK_OP_RR1_S1(ctx->opcode); 6424 r2 = MASK_OP_RR1_S2(ctx->opcode); 6425 r3 = MASK_OP_RR1_D(ctx->opcode); 6426 n = MASK_OP_RR1_N(ctx->opcode); 6427 op2 = MASK_OP_RR1_OP2(ctx->opcode); 6428 6429 temp = tcg_temp_new(); 6430 temp2 = tcg_temp_new(); 6431 6432 switch (op2) { 6433 case OPC2_32_RR1_MUL_Q_32: 6434 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], cpu_gpr_d[r2], n, 32); 6435 break; 6436 case OPC2_32_RR1_MUL_Q_64: 6437 CHECK_REG_PAIR(r3); 6438 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 6439 n, 0); 6440 break; 6441 case OPC2_32_RR1_MUL_Q_32_L: 6442 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 6443 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16); 6444 break; 6445 case OPC2_32_RR1_MUL_Q_64_L: 6446 CHECK_REG_PAIR(r3); 6447 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 6448 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0); 6449 break; 6450 case OPC2_32_RR1_MUL_Q_32_U: 6451 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 6452 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16); 6453 break; 6454 case OPC2_32_RR1_MUL_Q_64_U: 6455 CHECK_REG_PAIR(r3); 6456 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 6457 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0); 6458 break; 6459 case OPC2_32_RR1_MUL_Q_32_LL: 6460 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 6461 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 6462 gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n); 6463 break; 6464 case OPC2_32_RR1_MUL_Q_32_UU: 6465 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 6466 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 6467 gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n); 6468 break; 6469 case OPC2_32_RR1_MULR_Q_32_L: 6470 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 6471 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 6472 gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n); 6473 break; 6474 case OPC2_32_RR1_MULR_Q_32_U: 6475 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 6476 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 6477 gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n); 6478 break; 6479 default: 6480 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6481 } 6482 } 6483 6484 /* RR2 format */ 6485 static void decode_rr2_mul(DisasContext *ctx) 6486 { 6487 uint32_t op2; 6488 int r1, r2, r3; 6489 6490 op2 = MASK_OP_RR2_OP2(ctx->opcode); 6491 r1 = MASK_OP_RR2_S1(ctx->opcode); 6492 r2 = MASK_OP_RR2_S2(ctx->opcode); 6493 r3 = MASK_OP_RR2_D(ctx->opcode); 6494 switch (op2) { 6495 case OPC2_32_RR2_MUL_32: 6496 gen_mul_i32s(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6497 break; 6498 case OPC2_32_RR2_MUL_64: 6499 CHECK_REG_PAIR(r3); 6500 gen_mul_i64s(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6501 cpu_gpr_d[r2]); 6502 break; 6503 case OPC2_32_RR2_MULS_32: 6504 gen_helper_mul_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], 6505 cpu_gpr_d[r2]); 6506 break; 6507 case OPC2_32_RR2_MUL_U_64: 6508 CHECK_REG_PAIR(r3); 6509 gen_mul_i64u(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6510 cpu_gpr_d[r2]); 6511 break; 6512 case OPC2_32_RR2_MULS_U_32: 6513 gen_helper_mul_suov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], 6514 cpu_gpr_d[r2]); 6515 break; 6516 default: 6517 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6518 } 6519 } 6520 6521 /* RRPW format */ 6522 static void decode_rrpw_extract_insert(DisasContext *ctx) 6523 { 6524 uint32_t op2; 6525 int r1, r2, r3; 6526 int32_t pos, width; 6527 TCGv temp; 6528 6529 op2 = MASK_OP_RRPW_OP2(ctx->opcode); 6530 r1 = MASK_OP_RRPW_S1(ctx->opcode); 6531 r2 = MASK_OP_RRPW_S2(ctx->opcode); 6532 r3 = MASK_OP_RRPW_D(ctx->opcode); 6533 pos = MASK_OP_RRPW_POS(ctx->opcode); 6534 width = MASK_OP_RRPW_WIDTH(ctx->opcode); 6535 6536 switch (op2) { 6537 case OPC2_32_RRPW_EXTR: 6538 if (width == 0) { 6539 tcg_gen_movi_tl(cpu_gpr_d[r3], 0); 6540 } else if (pos + width <= 32) { 6541 tcg_gen_sextract_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], pos, width); 6542 } 6543 break; 6544 case OPC2_32_RRPW_EXTR_U: 6545 if (width == 0) { 6546 tcg_gen_movi_tl(cpu_gpr_d[r3], 0); 6547 } else { 6548 tcg_gen_extract_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], pos, width); 6549 } 6550 break; 6551 case OPC2_32_RRPW_IMASK: 6552 CHECK_REG_PAIR(r3); 6553 6554 if (pos + width <= 32) { 6555 temp = tcg_temp_new(); 6556 tcg_gen_movi_tl(temp, ((1u << width) - 1) << pos); 6557 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], pos); 6558 tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp); 6559 } 6560 6561 break; 6562 case OPC2_32_RRPW_INSERT: 6563 /* tcg_gen_deposit_tl() does not handle the case of width = 0 */ 6564 if (width == 0) { 6565 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6566 } else if (pos + width <= 32) { 6567 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 6568 pos, width); 6569 } 6570 break; 6571 default: 6572 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6573 } 6574 } 6575 6576 /* RRR format */ 6577 static void decode_rrr_cond_select(DisasContext *ctx) 6578 { 6579 uint32_t op2; 6580 int r1, r2, r3, r4; 6581 TCGv temp; 6582 6583 op2 = MASK_OP_RRR_OP2(ctx->opcode); 6584 r1 = MASK_OP_RRR_S1(ctx->opcode); 6585 r2 = MASK_OP_RRR_S2(ctx->opcode); 6586 r3 = MASK_OP_RRR_S3(ctx->opcode); 6587 r4 = MASK_OP_RRR_D(ctx->opcode); 6588 6589 switch (op2) { 6590 case OPC2_32_RRR_CADD: 6591 gen_cond_add(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], 6592 cpu_gpr_d[r4], cpu_gpr_d[r3]); 6593 break; 6594 case OPC2_32_RRR_CADDN: 6595 gen_cond_add(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4], 6596 cpu_gpr_d[r3]); 6597 break; 6598 case OPC2_32_RRR_CSUB: 6599 gen_cond_sub(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4], 6600 cpu_gpr_d[r3]); 6601 break; 6602 case OPC2_32_RRR_CSUBN: 6603 gen_cond_sub(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4], 6604 cpu_gpr_d[r3]); 6605 break; 6606 case OPC2_32_RRR_SEL: 6607 temp = tcg_constant_i32(0); 6608 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, 6609 cpu_gpr_d[r1], cpu_gpr_d[r2]); 6610 break; 6611 case OPC2_32_RRR_SELN: 6612 temp = tcg_constant_i32(0); 6613 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, 6614 cpu_gpr_d[r1], cpu_gpr_d[r2]); 6615 break; 6616 default: 6617 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6618 } 6619 } 6620 6621 static void decode_rrr_divide(DisasContext *ctx) 6622 { 6623 uint32_t op2; 6624 6625 int r1, r2, r3, r4; 6626 6627 op2 = MASK_OP_RRR_OP2(ctx->opcode); 6628 r1 = MASK_OP_RRR_S1(ctx->opcode); 6629 r2 = MASK_OP_RRR_S2(ctx->opcode); 6630 r3 = MASK_OP_RRR_S3(ctx->opcode); 6631 r4 = MASK_OP_RRR_D(ctx->opcode); 6632 6633 switch (op2) { 6634 case OPC2_32_RRR_DVADJ: 6635 CHECK_REG_PAIR(r3); 6636 CHECK_REG_PAIR(r4); 6637 GEN_HELPER_RRR(dvadj, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6638 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6639 break; 6640 case OPC2_32_RRR_DVSTEP: 6641 CHECK_REG_PAIR(r3); 6642 CHECK_REG_PAIR(r4); 6643 GEN_HELPER_RRR(dvstep, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6644 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6645 break; 6646 case OPC2_32_RRR_DVSTEP_U: 6647 CHECK_REG_PAIR(r3); 6648 CHECK_REG_PAIR(r4); 6649 GEN_HELPER_RRR(dvstep_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6650 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6651 break; 6652 case OPC2_32_RRR_IXMAX: 6653 CHECK_REG_PAIR(r3); 6654 CHECK_REG_PAIR(r4); 6655 GEN_HELPER_RRR(ixmax, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6656 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6657 break; 6658 case OPC2_32_RRR_IXMAX_U: 6659 CHECK_REG_PAIR(r3); 6660 CHECK_REG_PAIR(r4); 6661 GEN_HELPER_RRR(ixmax_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6662 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6663 break; 6664 case OPC2_32_RRR_IXMIN: 6665 CHECK_REG_PAIR(r3); 6666 CHECK_REG_PAIR(r4); 6667 GEN_HELPER_RRR(ixmin, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6668 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6669 break; 6670 case OPC2_32_RRR_IXMIN_U: 6671 CHECK_REG_PAIR(r3); 6672 CHECK_REG_PAIR(r4); 6673 GEN_HELPER_RRR(ixmin_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6674 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6675 break; 6676 case OPC2_32_RRR_PACK: 6677 CHECK_REG_PAIR(r3); 6678 gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3], 6679 cpu_gpr_d[r3+1], cpu_gpr_d[r1]); 6680 break; 6681 case OPC2_32_RRR_CRCN: 6682 if (has_feature(ctx, TRICORE_FEATURE_162)) { 6683 gen_helper_crcn(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], 6684 cpu_gpr_d[r3]); 6685 } else { 6686 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6687 } 6688 break; 6689 case OPC2_32_RRR_ADD_F: 6690 gen_helper_fadd(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r3]); 6691 break; 6692 case OPC2_32_RRR_SUB_F: 6693 gen_helper_fsub(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r3]); 6694 break; 6695 case OPC2_32_RRR_MADD_F: 6696 gen_helper_fmadd(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], 6697 cpu_gpr_d[r2], cpu_gpr_d[r3]); 6698 break; 6699 case OPC2_32_RRR_MSUB_F: 6700 gen_helper_fmsub(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], 6701 cpu_gpr_d[r2], cpu_gpr_d[r3]); 6702 break; 6703 default: 6704 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6705 } 6706 } 6707 6708 /* RRR2 format */ 6709 static void decode_rrr2_madd(DisasContext *ctx) 6710 { 6711 uint32_t op2; 6712 uint32_t r1, r2, r3, r4; 6713 6714 op2 = MASK_OP_RRR2_OP2(ctx->opcode); 6715 r1 = MASK_OP_RRR2_S1(ctx->opcode); 6716 r2 = MASK_OP_RRR2_S2(ctx->opcode); 6717 r3 = MASK_OP_RRR2_S3(ctx->opcode); 6718 r4 = MASK_OP_RRR2_D(ctx->opcode); 6719 switch (op2) { 6720 case OPC2_32_RRR2_MADD_32: 6721 gen_madd32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], 6722 cpu_gpr_d[r2]); 6723 break; 6724 case OPC2_32_RRR2_MADD_64: 6725 CHECK_REG_PAIR(r4); 6726 CHECK_REG_PAIR(r3); 6727 gen_madd64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6728 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6729 break; 6730 case OPC2_32_RRR2_MADDS_32: 6731 gen_helper_madd32_ssov(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], 6732 cpu_gpr_d[r3], cpu_gpr_d[r2]); 6733 break; 6734 case OPC2_32_RRR2_MADDS_64: 6735 CHECK_REG_PAIR(r4); 6736 CHECK_REG_PAIR(r3); 6737 gen_madds_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6738 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6739 break; 6740 case OPC2_32_RRR2_MADD_U_64: 6741 CHECK_REG_PAIR(r4); 6742 CHECK_REG_PAIR(r3); 6743 gen_maddu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6744 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6745 break; 6746 case OPC2_32_RRR2_MADDS_U_32: 6747 gen_helper_madd32_suov(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], 6748 cpu_gpr_d[r3], cpu_gpr_d[r2]); 6749 break; 6750 case OPC2_32_RRR2_MADDS_U_64: 6751 CHECK_REG_PAIR(r4); 6752 CHECK_REG_PAIR(r3); 6753 gen_maddsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6754 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6755 break; 6756 default: 6757 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6758 } 6759 } 6760 6761 static void decode_rrr2_msub(DisasContext *ctx) 6762 { 6763 uint32_t op2; 6764 uint32_t r1, r2, r3, r4; 6765 6766 op2 = MASK_OP_RRR2_OP2(ctx->opcode); 6767 r1 = MASK_OP_RRR2_S1(ctx->opcode); 6768 r2 = MASK_OP_RRR2_S2(ctx->opcode); 6769 r3 = MASK_OP_RRR2_S3(ctx->opcode); 6770 r4 = MASK_OP_RRR2_D(ctx->opcode); 6771 6772 switch (op2) { 6773 case OPC2_32_RRR2_MSUB_32: 6774 gen_msub32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], 6775 cpu_gpr_d[r2]); 6776 break; 6777 case OPC2_32_RRR2_MSUB_64: 6778 CHECK_REG_PAIR(r4); 6779 CHECK_REG_PAIR(r3); 6780 gen_msub64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6781 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6782 break; 6783 case OPC2_32_RRR2_MSUBS_32: 6784 gen_helper_msub32_ssov(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], 6785 cpu_gpr_d[r3], cpu_gpr_d[r2]); 6786 break; 6787 case OPC2_32_RRR2_MSUBS_64: 6788 CHECK_REG_PAIR(r4); 6789 CHECK_REG_PAIR(r3); 6790 gen_msubs_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6791 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6792 break; 6793 case OPC2_32_RRR2_MSUB_U_64: 6794 CHECK_REG_PAIR(r4); 6795 CHECK_REG_PAIR(r3); 6796 gen_msubu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6797 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6798 break; 6799 case OPC2_32_RRR2_MSUBS_U_32: 6800 gen_helper_msub32_suov(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], 6801 cpu_gpr_d[r3], cpu_gpr_d[r2]); 6802 break; 6803 case OPC2_32_RRR2_MSUBS_U_64: 6804 CHECK_REG_PAIR(r4); 6805 CHECK_REG_PAIR(r3); 6806 gen_msubsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6807 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6808 break; 6809 default: 6810 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6811 } 6812 } 6813 6814 /* RRR1 format */ 6815 static void decode_rrr1_madd(DisasContext *ctx) 6816 { 6817 uint32_t op2; 6818 uint32_t r1, r2, r3, r4, n; 6819 6820 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 6821 r1 = MASK_OP_RRR1_S1(ctx->opcode); 6822 r2 = MASK_OP_RRR1_S2(ctx->opcode); 6823 r3 = MASK_OP_RRR1_S3(ctx->opcode); 6824 r4 = MASK_OP_RRR1_D(ctx->opcode); 6825 n = MASK_OP_RRR1_N(ctx->opcode); 6826 6827 switch (op2) { 6828 case OPC2_32_RRR1_MADD_H_LL: 6829 CHECK_REG_PAIR(r4); 6830 CHECK_REG_PAIR(r3); 6831 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6832 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 6833 break; 6834 case OPC2_32_RRR1_MADD_H_LU: 6835 CHECK_REG_PAIR(r4); 6836 CHECK_REG_PAIR(r3); 6837 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6838 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 6839 break; 6840 case OPC2_32_RRR1_MADD_H_UL: 6841 CHECK_REG_PAIR(r4); 6842 CHECK_REG_PAIR(r3); 6843 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6844 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 6845 break; 6846 case OPC2_32_RRR1_MADD_H_UU: 6847 CHECK_REG_PAIR(r4); 6848 CHECK_REG_PAIR(r3); 6849 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6850 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 6851 break; 6852 case OPC2_32_RRR1_MADDS_H_LL: 6853 CHECK_REG_PAIR(r4); 6854 CHECK_REG_PAIR(r3); 6855 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6856 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 6857 break; 6858 case OPC2_32_RRR1_MADDS_H_LU: 6859 CHECK_REG_PAIR(r4); 6860 CHECK_REG_PAIR(r3); 6861 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6862 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 6863 break; 6864 case OPC2_32_RRR1_MADDS_H_UL: 6865 CHECK_REG_PAIR(r4); 6866 CHECK_REG_PAIR(r3); 6867 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6868 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 6869 break; 6870 case OPC2_32_RRR1_MADDS_H_UU: 6871 CHECK_REG_PAIR(r4); 6872 CHECK_REG_PAIR(r3); 6873 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6874 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 6875 break; 6876 case OPC2_32_RRR1_MADDM_H_LL: 6877 CHECK_REG_PAIR(r4); 6878 CHECK_REG_PAIR(r3); 6879 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6880 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 6881 break; 6882 case OPC2_32_RRR1_MADDM_H_LU: 6883 CHECK_REG_PAIR(r4); 6884 CHECK_REG_PAIR(r3); 6885 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6886 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 6887 break; 6888 case OPC2_32_RRR1_MADDM_H_UL: 6889 CHECK_REG_PAIR(r4); 6890 CHECK_REG_PAIR(r3); 6891 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6892 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 6893 break; 6894 case OPC2_32_RRR1_MADDM_H_UU: 6895 CHECK_REG_PAIR(r4); 6896 CHECK_REG_PAIR(r3); 6897 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6898 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 6899 break; 6900 case OPC2_32_RRR1_MADDMS_H_LL: 6901 CHECK_REG_PAIR(r4); 6902 CHECK_REG_PAIR(r3); 6903 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6904 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 6905 break; 6906 case OPC2_32_RRR1_MADDMS_H_LU: 6907 CHECK_REG_PAIR(r4); 6908 CHECK_REG_PAIR(r3); 6909 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6910 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 6911 break; 6912 case OPC2_32_RRR1_MADDMS_H_UL: 6913 CHECK_REG_PAIR(r4); 6914 CHECK_REG_PAIR(r3); 6915 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6916 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 6917 break; 6918 case OPC2_32_RRR1_MADDMS_H_UU: 6919 CHECK_REG_PAIR(r4); 6920 CHECK_REG_PAIR(r3); 6921 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6922 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 6923 break; 6924 case OPC2_32_RRR1_MADDR_H_LL: 6925 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6926 cpu_gpr_d[r2], n, MODE_LL); 6927 break; 6928 case OPC2_32_RRR1_MADDR_H_LU: 6929 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6930 cpu_gpr_d[r2], n, MODE_LU); 6931 break; 6932 case OPC2_32_RRR1_MADDR_H_UL: 6933 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6934 cpu_gpr_d[r2], n, MODE_UL); 6935 break; 6936 case OPC2_32_RRR1_MADDR_H_UU: 6937 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6938 cpu_gpr_d[r2], n, MODE_UU); 6939 break; 6940 case OPC2_32_RRR1_MADDRS_H_LL: 6941 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6942 cpu_gpr_d[r2], n, MODE_LL); 6943 break; 6944 case OPC2_32_RRR1_MADDRS_H_LU: 6945 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6946 cpu_gpr_d[r2], n, MODE_LU); 6947 break; 6948 case OPC2_32_RRR1_MADDRS_H_UL: 6949 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6950 cpu_gpr_d[r2], n, MODE_UL); 6951 break; 6952 case OPC2_32_RRR1_MADDRS_H_UU: 6953 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6954 cpu_gpr_d[r2], n, MODE_UU); 6955 break; 6956 default: 6957 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6958 } 6959 } 6960 6961 static void decode_rrr1_maddq_h(DisasContext *ctx) 6962 { 6963 uint32_t op2; 6964 uint32_t r1, r2, r3, r4, n; 6965 TCGv temp, temp2; 6966 6967 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 6968 r1 = MASK_OP_RRR1_S1(ctx->opcode); 6969 r2 = MASK_OP_RRR1_S2(ctx->opcode); 6970 r3 = MASK_OP_RRR1_S3(ctx->opcode); 6971 r4 = MASK_OP_RRR1_D(ctx->opcode); 6972 n = MASK_OP_RRR1_N(ctx->opcode); 6973 6974 temp = tcg_temp_new(); 6975 temp2 = tcg_temp_new(); 6976 6977 switch (op2) { 6978 case OPC2_32_RRR1_MADD_Q_32: 6979 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6980 cpu_gpr_d[r2], n, 32); 6981 break; 6982 case OPC2_32_RRR1_MADD_Q_64: 6983 CHECK_REG_PAIR(r4); 6984 CHECK_REG_PAIR(r3); 6985 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6986 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 6987 n); 6988 break; 6989 case OPC2_32_RRR1_MADD_Q_32_L: 6990 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 6991 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6992 temp, n, 16); 6993 break; 6994 case OPC2_32_RRR1_MADD_Q_64_L: 6995 CHECK_REG_PAIR(r4); 6996 CHECK_REG_PAIR(r3); 6997 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 6998 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6999 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7000 n); 7001 break; 7002 case OPC2_32_RRR1_MADD_Q_32_U: 7003 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7004 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7005 temp, n, 16); 7006 break; 7007 case OPC2_32_RRR1_MADD_Q_64_U: 7008 CHECK_REG_PAIR(r4); 7009 CHECK_REG_PAIR(r3); 7010 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7011 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7012 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7013 n); 7014 break; 7015 case OPC2_32_RRR1_MADD_Q_32_LL: 7016 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7017 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7018 gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7019 break; 7020 case OPC2_32_RRR1_MADD_Q_64_LL: 7021 CHECK_REG_PAIR(r4); 7022 CHECK_REG_PAIR(r3); 7023 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7024 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7025 gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7026 cpu_gpr_d[r3+1], temp, temp2, n); 7027 break; 7028 case OPC2_32_RRR1_MADD_Q_32_UU: 7029 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7030 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7031 gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7032 break; 7033 case OPC2_32_RRR1_MADD_Q_64_UU: 7034 CHECK_REG_PAIR(r4); 7035 CHECK_REG_PAIR(r3); 7036 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7037 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7038 gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7039 cpu_gpr_d[r3+1], temp, temp2, n); 7040 break; 7041 case OPC2_32_RRR1_MADDS_Q_32: 7042 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7043 cpu_gpr_d[r2], n, 32); 7044 break; 7045 case OPC2_32_RRR1_MADDS_Q_64: 7046 CHECK_REG_PAIR(r4); 7047 CHECK_REG_PAIR(r3); 7048 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7049 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7050 n); 7051 break; 7052 case OPC2_32_RRR1_MADDS_Q_32_L: 7053 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7054 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7055 temp, n, 16); 7056 break; 7057 case OPC2_32_RRR1_MADDS_Q_64_L: 7058 CHECK_REG_PAIR(r4); 7059 CHECK_REG_PAIR(r3); 7060 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7061 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7062 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7063 n); 7064 break; 7065 case OPC2_32_RRR1_MADDS_Q_32_U: 7066 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7067 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7068 temp, n, 16); 7069 break; 7070 case OPC2_32_RRR1_MADDS_Q_64_U: 7071 CHECK_REG_PAIR(r4); 7072 CHECK_REG_PAIR(r3); 7073 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7074 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7075 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7076 n); 7077 break; 7078 case OPC2_32_RRR1_MADDS_Q_32_LL: 7079 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7080 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7081 gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7082 break; 7083 case OPC2_32_RRR1_MADDS_Q_64_LL: 7084 CHECK_REG_PAIR(r4); 7085 CHECK_REG_PAIR(r3); 7086 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7087 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7088 gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7089 cpu_gpr_d[r3+1], temp, temp2, n); 7090 break; 7091 case OPC2_32_RRR1_MADDS_Q_32_UU: 7092 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7093 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7094 gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7095 break; 7096 case OPC2_32_RRR1_MADDS_Q_64_UU: 7097 CHECK_REG_PAIR(r4); 7098 CHECK_REG_PAIR(r3); 7099 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7100 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7101 gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7102 cpu_gpr_d[r3+1], temp, temp2, n); 7103 break; 7104 case OPC2_32_RRR1_MADDR_H_64_UL: 7105 CHECK_REG_PAIR(r3); 7106 gen_maddr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], 7107 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); 7108 break; 7109 case OPC2_32_RRR1_MADDRS_H_64_UL: 7110 CHECK_REG_PAIR(r3); 7111 gen_maddr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], 7112 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); 7113 break; 7114 case OPC2_32_RRR1_MADDR_Q_32_LL: 7115 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7116 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7117 gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7118 break; 7119 case OPC2_32_RRR1_MADDR_Q_32_UU: 7120 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7121 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7122 gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7123 break; 7124 case OPC2_32_RRR1_MADDRS_Q_32_LL: 7125 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7126 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7127 gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7128 break; 7129 case OPC2_32_RRR1_MADDRS_Q_32_UU: 7130 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7131 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7132 gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7133 break; 7134 default: 7135 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7136 } 7137 } 7138 7139 static void decode_rrr1_maddsu_h(DisasContext *ctx) 7140 { 7141 uint32_t op2; 7142 uint32_t r1, r2, r3, r4, n; 7143 7144 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 7145 r1 = MASK_OP_RRR1_S1(ctx->opcode); 7146 r2 = MASK_OP_RRR1_S2(ctx->opcode); 7147 r3 = MASK_OP_RRR1_S3(ctx->opcode); 7148 r4 = MASK_OP_RRR1_D(ctx->opcode); 7149 n = MASK_OP_RRR1_N(ctx->opcode); 7150 7151 switch (op2) { 7152 case OPC2_32_RRR1_MADDSU_H_32_LL: 7153 CHECK_REG_PAIR(r4); 7154 CHECK_REG_PAIR(r3); 7155 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7156 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7157 break; 7158 case OPC2_32_RRR1_MADDSU_H_32_LU: 7159 CHECK_REG_PAIR(r4); 7160 CHECK_REG_PAIR(r3); 7161 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7162 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7163 break; 7164 case OPC2_32_RRR1_MADDSU_H_32_UL: 7165 CHECK_REG_PAIR(r4); 7166 CHECK_REG_PAIR(r3); 7167 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7168 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7169 break; 7170 case OPC2_32_RRR1_MADDSU_H_32_UU: 7171 CHECK_REG_PAIR(r4); 7172 CHECK_REG_PAIR(r3); 7173 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7174 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7175 break; 7176 case OPC2_32_RRR1_MADDSUS_H_32_LL: 7177 CHECK_REG_PAIR(r4); 7178 CHECK_REG_PAIR(r3); 7179 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7180 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7181 n, MODE_LL); 7182 break; 7183 case OPC2_32_RRR1_MADDSUS_H_32_LU: 7184 CHECK_REG_PAIR(r4); 7185 CHECK_REG_PAIR(r3); 7186 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7187 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7188 n, MODE_LU); 7189 break; 7190 case OPC2_32_RRR1_MADDSUS_H_32_UL: 7191 CHECK_REG_PAIR(r4); 7192 CHECK_REG_PAIR(r3); 7193 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7194 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7195 n, MODE_UL); 7196 break; 7197 case OPC2_32_RRR1_MADDSUS_H_32_UU: 7198 CHECK_REG_PAIR(r4); 7199 CHECK_REG_PAIR(r3); 7200 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7201 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7202 n, MODE_UU); 7203 break; 7204 case OPC2_32_RRR1_MADDSUM_H_64_LL: 7205 CHECK_REG_PAIR(r4); 7206 CHECK_REG_PAIR(r3); 7207 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7208 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7209 n, MODE_LL); 7210 break; 7211 case OPC2_32_RRR1_MADDSUM_H_64_LU: 7212 CHECK_REG_PAIR(r4); 7213 CHECK_REG_PAIR(r3); 7214 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7215 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7216 n, MODE_LU); 7217 break; 7218 case OPC2_32_RRR1_MADDSUM_H_64_UL: 7219 CHECK_REG_PAIR(r4); 7220 CHECK_REG_PAIR(r3); 7221 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7222 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7223 n, MODE_UL); 7224 break; 7225 case OPC2_32_RRR1_MADDSUM_H_64_UU: 7226 CHECK_REG_PAIR(r4); 7227 CHECK_REG_PAIR(r3); 7228 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7229 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7230 n, MODE_UU); 7231 break; 7232 case OPC2_32_RRR1_MADDSUMS_H_64_LL: 7233 CHECK_REG_PAIR(r4); 7234 CHECK_REG_PAIR(r3); 7235 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7236 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7237 n, MODE_LL); 7238 break; 7239 case OPC2_32_RRR1_MADDSUMS_H_64_LU: 7240 CHECK_REG_PAIR(r4); 7241 CHECK_REG_PAIR(r3); 7242 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7243 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7244 n, MODE_LU); 7245 break; 7246 case OPC2_32_RRR1_MADDSUMS_H_64_UL: 7247 CHECK_REG_PAIR(r4); 7248 CHECK_REG_PAIR(r3); 7249 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7250 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7251 n, MODE_UL); 7252 break; 7253 case OPC2_32_RRR1_MADDSUMS_H_64_UU: 7254 CHECK_REG_PAIR(r4); 7255 CHECK_REG_PAIR(r3); 7256 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7257 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7258 n, MODE_UU); 7259 break; 7260 case OPC2_32_RRR1_MADDSUR_H_16_LL: 7261 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7262 cpu_gpr_d[r2], n, MODE_LL); 7263 break; 7264 case OPC2_32_RRR1_MADDSUR_H_16_LU: 7265 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7266 cpu_gpr_d[r2], n, MODE_LU); 7267 break; 7268 case OPC2_32_RRR1_MADDSUR_H_16_UL: 7269 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7270 cpu_gpr_d[r2], n, MODE_UL); 7271 break; 7272 case OPC2_32_RRR1_MADDSUR_H_16_UU: 7273 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7274 cpu_gpr_d[r2], n, MODE_UU); 7275 break; 7276 case OPC2_32_RRR1_MADDSURS_H_16_LL: 7277 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7278 cpu_gpr_d[r2], n, MODE_LL); 7279 break; 7280 case OPC2_32_RRR1_MADDSURS_H_16_LU: 7281 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7282 cpu_gpr_d[r2], n, MODE_LU); 7283 break; 7284 case OPC2_32_RRR1_MADDSURS_H_16_UL: 7285 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7286 cpu_gpr_d[r2], n, MODE_UL); 7287 break; 7288 case OPC2_32_RRR1_MADDSURS_H_16_UU: 7289 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7290 cpu_gpr_d[r2], n, MODE_UU); 7291 break; 7292 default: 7293 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7294 } 7295 } 7296 7297 static void decode_rrr1_msub(DisasContext *ctx) 7298 { 7299 uint32_t op2; 7300 uint32_t r1, r2, r3, r4, n; 7301 7302 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 7303 r1 = MASK_OP_RRR1_S1(ctx->opcode); 7304 r2 = MASK_OP_RRR1_S2(ctx->opcode); 7305 r3 = MASK_OP_RRR1_S3(ctx->opcode); 7306 r4 = MASK_OP_RRR1_D(ctx->opcode); 7307 n = MASK_OP_RRR1_N(ctx->opcode); 7308 7309 switch (op2) { 7310 case OPC2_32_RRR1_MSUB_H_LL: 7311 CHECK_REG_PAIR(r4); 7312 CHECK_REG_PAIR(r3); 7313 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7314 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7315 break; 7316 case OPC2_32_RRR1_MSUB_H_LU: 7317 CHECK_REG_PAIR(r4); 7318 CHECK_REG_PAIR(r3); 7319 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7320 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7321 break; 7322 case OPC2_32_RRR1_MSUB_H_UL: 7323 CHECK_REG_PAIR(r4); 7324 CHECK_REG_PAIR(r3); 7325 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7326 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7327 break; 7328 case OPC2_32_RRR1_MSUB_H_UU: 7329 CHECK_REG_PAIR(r4); 7330 CHECK_REG_PAIR(r3); 7331 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7332 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7333 break; 7334 case OPC2_32_RRR1_MSUBS_H_LL: 7335 CHECK_REG_PAIR(r4); 7336 CHECK_REG_PAIR(r3); 7337 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7338 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7339 break; 7340 case OPC2_32_RRR1_MSUBS_H_LU: 7341 CHECK_REG_PAIR(r4); 7342 CHECK_REG_PAIR(r3); 7343 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7344 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7345 break; 7346 case OPC2_32_RRR1_MSUBS_H_UL: 7347 CHECK_REG_PAIR(r4); 7348 CHECK_REG_PAIR(r3); 7349 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7350 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7351 break; 7352 case OPC2_32_RRR1_MSUBS_H_UU: 7353 CHECK_REG_PAIR(r4); 7354 CHECK_REG_PAIR(r3); 7355 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7356 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7357 break; 7358 case OPC2_32_RRR1_MSUBM_H_LL: 7359 CHECK_REG_PAIR(r4); 7360 CHECK_REG_PAIR(r3); 7361 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7362 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7363 break; 7364 case OPC2_32_RRR1_MSUBM_H_LU: 7365 CHECK_REG_PAIR(r4); 7366 CHECK_REG_PAIR(r3); 7367 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7368 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7369 break; 7370 case OPC2_32_RRR1_MSUBM_H_UL: 7371 CHECK_REG_PAIR(r4); 7372 CHECK_REG_PAIR(r3); 7373 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7374 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7375 break; 7376 case OPC2_32_RRR1_MSUBM_H_UU: 7377 CHECK_REG_PAIR(r4); 7378 CHECK_REG_PAIR(r3); 7379 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7380 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7381 break; 7382 case OPC2_32_RRR1_MSUBMS_H_LL: 7383 CHECK_REG_PAIR(r4); 7384 CHECK_REG_PAIR(r3); 7385 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7386 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7387 break; 7388 case OPC2_32_RRR1_MSUBMS_H_LU: 7389 CHECK_REG_PAIR(r4); 7390 CHECK_REG_PAIR(r3); 7391 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7392 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7393 break; 7394 case OPC2_32_RRR1_MSUBMS_H_UL: 7395 CHECK_REG_PAIR(r4); 7396 CHECK_REG_PAIR(r3); 7397 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7398 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7399 break; 7400 case OPC2_32_RRR1_MSUBMS_H_UU: 7401 CHECK_REG_PAIR(r4); 7402 CHECK_REG_PAIR(r3); 7403 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7404 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7405 break; 7406 case OPC2_32_RRR1_MSUBR_H_LL: 7407 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7408 cpu_gpr_d[r2], n, MODE_LL); 7409 break; 7410 case OPC2_32_RRR1_MSUBR_H_LU: 7411 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7412 cpu_gpr_d[r2], n, MODE_LU); 7413 break; 7414 case OPC2_32_RRR1_MSUBR_H_UL: 7415 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7416 cpu_gpr_d[r2], n, MODE_UL); 7417 break; 7418 case OPC2_32_RRR1_MSUBR_H_UU: 7419 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7420 cpu_gpr_d[r2], n, MODE_UU); 7421 break; 7422 case OPC2_32_RRR1_MSUBRS_H_LL: 7423 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7424 cpu_gpr_d[r2], n, MODE_LL); 7425 break; 7426 case OPC2_32_RRR1_MSUBRS_H_LU: 7427 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7428 cpu_gpr_d[r2], n, MODE_LU); 7429 break; 7430 case OPC2_32_RRR1_MSUBRS_H_UL: 7431 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7432 cpu_gpr_d[r2], n, MODE_UL); 7433 break; 7434 case OPC2_32_RRR1_MSUBRS_H_UU: 7435 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7436 cpu_gpr_d[r2], n, MODE_UU); 7437 break; 7438 default: 7439 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7440 } 7441 } 7442 7443 static void decode_rrr1_msubq_h(DisasContext *ctx) 7444 { 7445 uint32_t op2; 7446 uint32_t r1, r2, r3, r4, n; 7447 TCGv temp, temp2; 7448 7449 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 7450 r1 = MASK_OP_RRR1_S1(ctx->opcode); 7451 r2 = MASK_OP_RRR1_S2(ctx->opcode); 7452 r3 = MASK_OP_RRR1_S3(ctx->opcode); 7453 r4 = MASK_OP_RRR1_D(ctx->opcode); 7454 n = MASK_OP_RRR1_N(ctx->opcode); 7455 7456 temp = tcg_temp_new(); 7457 temp2 = tcg_temp_new(); 7458 7459 switch (op2) { 7460 case OPC2_32_RRR1_MSUB_Q_32: 7461 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7462 cpu_gpr_d[r2], n, 32); 7463 break; 7464 case OPC2_32_RRR1_MSUB_Q_64: 7465 CHECK_REG_PAIR(r4); 7466 CHECK_REG_PAIR(r3); 7467 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7468 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7469 n); 7470 break; 7471 case OPC2_32_RRR1_MSUB_Q_32_L: 7472 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7473 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7474 temp, n, 16); 7475 break; 7476 case OPC2_32_RRR1_MSUB_Q_64_L: 7477 CHECK_REG_PAIR(r4); 7478 CHECK_REG_PAIR(r3); 7479 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7480 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7481 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7482 n); 7483 break; 7484 case OPC2_32_RRR1_MSUB_Q_32_U: 7485 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7486 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7487 temp, n, 16); 7488 break; 7489 case OPC2_32_RRR1_MSUB_Q_64_U: 7490 CHECK_REG_PAIR(r4); 7491 CHECK_REG_PAIR(r3); 7492 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7493 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7494 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7495 n); 7496 break; 7497 case OPC2_32_RRR1_MSUB_Q_32_LL: 7498 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7499 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7500 gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7501 break; 7502 case OPC2_32_RRR1_MSUB_Q_64_LL: 7503 CHECK_REG_PAIR(r4); 7504 CHECK_REG_PAIR(r3); 7505 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7506 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7507 gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7508 cpu_gpr_d[r3+1], temp, temp2, n); 7509 break; 7510 case OPC2_32_RRR1_MSUB_Q_32_UU: 7511 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7512 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7513 gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7514 break; 7515 case OPC2_32_RRR1_MSUB_Q_64_UU: 7516 CHECK_REG_PAIR(r4); 7517 CHECK_REG_PAIR(r3); 7518 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7519 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7520 gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7521 cpu_gpr_d[r3+1], temp, temp2, n); 7522 break; 7523 case OPC2_32_RRR1_MSUBS_Q_32: 7524 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7525 cpu_gpr_d[r2], n, 32); 7526 break; 7527 case OPC2_32_RRR1_MSUBS_Q_64: 7528 CHECK_REG_PAIR(r4); 7529 CHECK_REG_PAIR(r3); 7530 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7531 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7532 n); 7533 break; 7534 case OPC2_32_RRR1_MSUBS_Q_32_L: 7535 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7536 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7537 temp, n, 16); 7538 break; 7539 case OPC2_32_RRR1_MSUBS_Q_64_L: 7540 CHECK_REG_PAIR(r4); 7541 CHECK_REG_PAIR(r3); 7542 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7543 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7544 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7545 n); 7546 break; 7547 case OPC2_32_RRR1_MSUBS_Q_32_U: 7548 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7549 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7550 temp, n, 16); 7551 break; 7552 case OPC2_32_RRR1_MSUBS_Q_64_U: 7553 CHECK_REG_PAIR(r4); 7554 CHECK_REG_PAIR(r3); 7555 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7556 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7557 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7558 n); 7559 break; 7560 case OPC2_32_RRR1_MSUBS_Q_32_LL: 7561 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7562 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7563 gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7564 break; 7565 case OPC2_32_RRR1_MSUBS_Q_64_LL: 7566 CHECK_REG_PAIR(r4); 7567 CHECK_REG_PAIR(r3); 7568 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7569 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7570 gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7571 cpu_gpr_d[r3+1], temp, temp2, n); 7572 break; 7573 case OPC2_32_RRR1_MSUBS_Q_32_UU: 7574 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7575 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7576 gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7577 break; 7578 case OPC2_32_RRR1_MSUBS_Q_64_UU: 7579 CHECK_REG_PAIR(r4); 7580 CHECK_REG_PAIR(r3); 7581 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7582 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7583 gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7584 cpu_gpr_d[r3+1], temp, temp2, n); 7585 break; 7586 case OPC2_32_RRR1_MSUBR_H_64_UL: 7587 CHECK_REG_PAIR(r3); 7588 gen_msubr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], 7589 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); 7590 break; 7591 case OPC2_32_RRR1_MSUBRS_H_64_UL: 7592 CHECK_REG_PAIR(r3); 7593 gen_msubr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], 7594 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); 7595 break; 7596 case OPC2_32_RRR1_MSUBR_Q_32_LL: 7597 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7598 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7599 gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7600 break; 7601 case OPC2_32_RRR1_MSUBR_Q_32_UU: 7602 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7603 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7604 gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7605 break; 7606 case OPC2_32_RRR1_MSUBRS_Q_32_LL: 7607 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7608 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7609 gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7610 break; 7611 case OPC2_32_RRR1_MSUBRS_Q_32_UU: 7612 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7613 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7614 gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7615 break; 7616 default: 7617 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7618 } 7619 } 7620 7621 static void decode_rrr1_msubad_h(DisasContext *ctx) 7622 { 7623 uint32_t op2; 7624 uint32_t r1, r2, r3, r4, n; 7625 7626 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 7627 r1 = MASK_OP_RRR1_S1(ctx->opcode); 7628 r2 = MASK_OP_RRR1_S2(ctx->opcode); 7629 r3 = MASK_OP_RRR1_S3(ctx->opcode); 7630 r4 = MASK_OP_RRR1_D(ctx->opcode); 7631 n = MASK_OP_RRR1_N(ctx->opcode); 7632 7633 switch (op2) { 7634 case OPC2_32_RRR1_MSUBAD_H_32_LL: 7635 CHECK_REG_PAIR(r4); 7636 CHECK_REG_PAIR(r3); 7637 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7638 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7639 break; 7640 case OPC2_32_RRR1_MSUBAD_H_32_LU: 7641 CHECK_REG_PAIR(r4); 7642 CHECK_REG_PAIR(r3); 7643 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7644 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7645 break; 7646 case OPC2_32_RRR1_MSUBAD_H_32_UL: 7647 CHECK_REG_PAIR(r4); 7648 CHECK_REG_PAIR(r3); 7649 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7650 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7651 break; 7652 case OPC2_32_RRR1_MSUBAD_H_32_UU: 7653 CHECK_REG_PAIR(r4); 7654 CHECK_REG_PAIR(r3); 7655 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7656 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7657 break; 7658 case OPC2_32_RRR1_MSUBADS_H_32_LL: 7659 CHECK_REG_PAIR(r4); 7660 CHECK_REG_PAIR(r3); 7661 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7662 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7663 n, MODE_LL); 7664 break; 7665 case OPC2_32_RRR1_MSUBADS_H_32_LU: 7666 CHECK_REG_PAIR(r4); 7667 CHECK_REG_PAIR(r3); 7668 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7669 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7670 n, MODE_LU); 7671 break; 7672 case OPC2_32_RRR1_MSUBADS_H_32_UL: 7673 CHECK_REG_PAIR(r4); 7674 CHECK_REG_PAIR(r3); 7675 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7676 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7677 n, MODE_UL); 7678 break; 7679 case OPC2_32_RRR1_MSUBADS_H_32_UU: 7680 CHECK_REG_PAIR(r4); 7681 CHECK_REG_PAIR(r3); 7682 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7683 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7684 n, MODE_UU); 7685 break; 7686 case OPC2_32_RRR1_MSUBADM_H_64_LL: 7687 CHECK_REG_PAIR(r4); 7688 CHECK_REG_PAIR(r3); 7689 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7690 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7691 n, MODE_LL); 7692 break; 7693 case OPC2_32_RRR1_MSUBADM_H_64_LU: 7694 CHECK_REG_PAIR(r4); 7695 CHECK_REG_PAIR(r3); 7696 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7697 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7698 n, MODE_LU); 7699 break; 7700 case OPC2_32_RRR1_MSUBADM_H_64_UL: 7701 CHECK_REG_PAIR(r4); 7702 CHECK_REG_PAIR(r3); 7703 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7704 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7705 n, MODE_UL); 7706 break; 7707 case OPC2_32_RRR1_MSUBADM_H_64_UU: 7708 CHECK_REG_PAIR(r4); 7709 CHECK_REG_PAIR(r3); 7710 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7711 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7712 n, MODE_UU); 7713 break; 7714 case OPC2_32_RRR1_MSUBADMS_H_64_LL: 7715 CHECK_REG_PAIR(r4); 7716 CHECK_REG_PAIR(r3); 7717 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7718 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7719 n, MODE_LL); 7720 break; 7721 case OPC2_32_RRR1_MSUBADMS_H_64_LU: 7722 CHECK_REG_PAIR(r4); 7723 CHECK_REG_PAIR(r3); 7724 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7725 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7726 n, MODE_LU); 7727 break; 7728 case OPC2_32_RRR1_MSUBADMS_H_64_UL: 7729 CHECK_REG_PAIR(r4); 7730 CHECK_REG_PAIR(r3); 7731 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7732 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7733 n, MODE_UL); 7734 break; 7735 case OPC2_32_RRR1_MSUBADMS_H_64_UU: 7736 CHECK_REG_PAIR(r4); 7737 CHECK_REG_PAIR(r3); 7738 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7739 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7740 n, MODE_UU); 7741 break; 7742 case OPC2_32_RRR1_MSUBADR_H_16_LL: 7743 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7744 cpu_gpr_d[r2], n, MODE_LL); 7745 break; 7746 case OPC2_32_RRR1_MSUBADR_H_16_LU: 7747 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7748 cpu_gpr_d[r2], n, MODE_LU); 7749 break; 7750 case OPC2_32_RRR1_MSUBADR_H_16_UL: 7751 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7752 cpu_gpr_d[r2], n, MODE_UL); 7753 break; 7754 case OPC2_32_RRR1_MSUBADR_H_16_UU: 7755 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7756 cpu_gpr_d[r2], n, MODE_UU); 7757 break; 7758 case OPC2_32_RRR1_MSUBADRS_H_16_LL: 7759 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7760 cpu_gpr_d[r2], n, MODE_LL); 7761 break; 7762 case OPC2_32_RRR1_MSUBADRS_H_16_LU: 7763 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7764 cpu_gpr_d[r2], n, MODE_LU); 7765 break; 7766 case OPC2_32_RRR1_MSUBADRS_H_16_UL: 7767 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7768 cpu_gpr_d[r2], n, MODE_UL); 7769 break; 7770 case OPC2_32_RRR1_MSUBADRS_H_16_UU: 7771 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7772 cpu_gpr_d[r2], n, MODE_UU); 7773 break; 7774 default: 7775 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7776 } 7777 } 7778 7779 /* RRRR format */ 7780 static void decode_rrrr_extract_insert(DisasContext *ctx) 7781 { 7782 uint32_t op2; 7783 int r1, r2, r3, r4; 7784 TCGv tmp_width, tmp_pos; 7785 7786 r1 = MASK_OP_RRRR_S1(ctx->opcode); 7787 r2 = MASK_OP_RRRR_S2(ctx->opcode); 7788 r3 = MASK_OP_RRRR_S3(ctx->opcode); 7789 r4 = MASK_OP_RRRR_D(ctx->opcode); 7790 op2 = MASK_OP_RRRR_OP2(ctx->opcode); 7791 7792 tmp_pos = tcg_temp_new(); 7793 tmp_width = tcg_temp_new(); 7794 7795 switch (op2) { 7796 case OPC2_32_RRRR_DEXTR: 7797 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f); 7798 if (r1 == r2) { 7799 tcg_gen_rotl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos); 7800 } else { 7801 TCGv msw = tcg_temp_new(); 7802 TCGv zero = tcg_constant_tl(0); 7803 tcg_gen_shl_tl(tmp_width, cpu_gpr_d[r1], tmp_pos); 7804 tcg_gen_subfi_tl(msw, 32, tmp_pos); 7805 tcg_gen_shr_tl(msw, cpu_gpr_d[r2], msw); 7806 /* 7807 * if pos == 0, then we do cpu_gpr_d[r2] << 32, which is undefined 7808 * behaviour. So check that case here and set the low bits to zero 7809 * which effectivly returns cpu_gpr_d[r1] 7810 */ 7811 tcg_gen_movcond_tl(TCG_COND_EQ, msw, tmp_pos, zero, zero, msw); 7812 tcg_gen_or_tl(cpu_gpr_d[r4], tmp_width, msw); 7813 } 7814 break; 7815 case OPC2_32_RRRR_EXTR: 7816 case OPC2_32_RRRR_EXTR_U: 7817 CHECK_REG_PAIR(r3); 7818 tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f); 7819 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f); 7820 tcg_gen_add_tl(tmp_pos, tmp_pos, tmp_width); 7821 tcg_gen_subfi_tl(tmp_pos, 32, tmp_pos); 7822 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos); 7823 tcg_gen_subfi_tl(tmp_width, 32, tmp_width); 7824 if (op2 == OPC2_32_RRRR_EXTR) { 7825 tcg_gen_sar_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width); 7826 } else { 7827 tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width); 7828 } 7829 break; 7830 case OPC2_32_RRRR_INSERT: 7831 CHECK_REG_PAIR(r3); 7832 tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f); 7833 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f); 7834 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], tmp_width, 7835 tmp_pos); 7836 break; 7837 default: 7838 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7839 } 7840 } 7841 7842 /* RRRW format */ 7843 static void decode_rrrw_extract_insert(DisasContext *ctx) 7844 { 7845 uint32_t op2; 7846 int r1, r2, r3, r4; 7847 int32_t width; 7848 7849 TCGv temp, temp2; 7850 7851 op2 = MASK_OP_RRRW_OP2(ctx->opcode); 7852 r1 = MASK_OP_RRRW_S1(ctx->opcode); 7853 r2 = MASK_OP_RRRW_S2(ctx->opcode); 7854 r3 = MASK_OP_RRRW_S3(ctx->opcode); 7855 r4 = MASK_OP_RRRW_D(ctx->opcode); 7856 width = MASK_OP_RRRW_WIDTH(ctx->opcode); 7857 7858 temp = tcg_temp_new(); 7859 7860 switch (op2) { 7861 case OPC2_32_RRRW_EXTR: 7862 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); 7863 tcg_gen_addi_tl(temp, temp, width); 7864 tcg_gen_subfi_tl(temp, 32, temp); 7865 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp); 7866 tcg_gen_sari_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], 32 - width); 7867 break; 7868 case OPC2_32_RRRW_EXTR_U: 7869 if (width == 0) { 7870 tcg_gen_movi_tl(cpu_gpr_d[r4], 0); 7871 } else { 7872 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); 7873 tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp); 7874 tcg_gen_andi_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], ~0u >> (32-width)); 7875 } 7876 break; 7877 case OPC2_32_RRRW_IMASK: 7878 temp2 = tcg_temp_new(); 7879 CHECK_REG_PAIR(r4); 7880 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); 7881 tcg_gen_movi_tl(temp2, (1 << width) - 1); 7882 tcg_gen_shl_tl(temp2, temp2, temp); 7883 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r2], temp); 7884 tcg_gen_mov_tl(cpu_gpr_d[r4+1], temp2); 7885 break; 7886 case OPC2_32_RRRW_INSERT: 7887 temp2 = tcg_temp_new(); 7888 7889 tcg_gen_movi_tl(temp, width); 7890 tcg_gen_andi_tl(temp2, cpu_gpr_d[r3], 0x1f); 7891 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], temp, temp2); 7892 break; 7893 default: 7894 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7895 } 7896 } 7897 7898 /* SYS Format*/ 7899 static void decode_sys_interrupts(DisasContext *ctx) 7900 { 7901 uint32_t op2; 7902 uint32_t r1; 7903 TCGLabel *l1; 7904 TCGv tmp; 7905 7906 op2 = MASK_OP_SYS_OP2(ctx->opcode); 7907 r1 = MASK_OP_SYS_S1D(ctx->opcode); 7908 7909 switch (op2) { 7910 case OPC2_32_SYS_DEBUG: 7911 /* raise EXCP_DEBUG */ 7912 break; 7913 case OPC2_32_SYS_DISABLE: 7914 if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) { 7915 tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~ctx->icr_ie_mask); 7916 } else { 7917 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); 7918 } 7919 break; 7920 case OPC2_32_SYS_DISABLE_D: 7921 if (has_feature(ctx, TRICORE_FEATURE_16)) { 7922 if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) { 7923 tcg_gen_extract_tl(cpu_gpr_d[r1], cpu_ICR, 7924 ctx->icr_ie_offset, 1); 7925 tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~ctx->icr_ie_mask); 7926 } else { 7927 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); 7928 } 7929 } else { 7930 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7931 } 7932 case OPC2_32_SYS_DSYNC: 7933 break; 7934 case OPC2_32_SYS_ENABLE: 7935 if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) { 7936 tcg_gen_ori_tl(cpu_ICR, cpu_ICR, ctx->icr_ie_mask); 7937 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 7938 } else { 7939 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); 7940 } 7941 break; 7942 case OPC2_32_SYS_ISYNC: 7943 break; 7944 case OPC2_32_SYS_NOP: 7945 break; 7946 case OPC2_32_SYS_RET: 7947 gen_compute_branch(ctx, op2, 0, 0, 0, 0); 7948 break; 7949 case OPC2_32_SYS_FRET: 7950 gen_fret(ctx); 7951 break; 7952 case OPC2_32_SYS_RFE: 7953 gen_helper_rfe(tcg_env); 7954 ctx->base.is_jmp = DISAS_EXIT; 7955 break; 7956 case OPC2_32_SYS_RFM: 7957 if (ctx->priv == TRICORE_PRIV_SM) { 7958 tmp = tcg_temp_new(); 7959 l1 = gen_new_label(); 7960 7961 tcg_gen_ld32u_tl(tmp, tcg_env, offsetof(CPUTriCoreState, DBGSR)); 7962 tcg_gen_andi_tl(tmp, tmp, MASK_DBGSR_DE); 7963 tcg_gen_brcondi_tl(TCG_COND_NE, tmp, 1, l1); 7964 gen_helper_rfm(tcg_env); 7965 gen_set_label(l1); 7966 ctx->base.is_jmp = DISAS_EXIT; 7967 } else { 7968 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); 7969 } 7970 break; 7971 case OPC2_32_SYS_RSLCX: 7972 gen_helper_rslcx(tcg_env); 7973 break; 7974 case OPC2_32_SYS_SVLCX: 7975 gen_helper_svlcx(tcg_env); 7976 break; 7977 case OPC2_32_SYS_RESTORE: 7978 if (has_feature(ctx, TRICORE_FEATURE_16)) { 7979 if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) { 7980 tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], 7981 ctx->icr_ie_offset, 1); 7982 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 7983 } else { 7984 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); 7985 } 7986 } else { 7987 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7988 } 7989 break; 7990 case OPC2_32_SYS_TRAPSV: 7991 l1 = gen_new_label(); 7992 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_SV, 0, l1); 7993 generate_trap(ctx, TRAPC_ASSERT, TIN5_SOVF); 7994 gen_set_label(l1); 7995 break; 7996 case OPC2_32_SYS_TRAPV: 7997 l1 = gen_new_label(); 7998 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_V, 0, l1); 7999 generate_trap(ctx, TRAPC_ASSERT, TIN5_OVF); 8000 gen_set_label(l1); 8001 break; 8002 default: 8003 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 8004 } 8005 } 8006 8007 static void decode_32Bit_opc(DisasContext *ctx) 8008 { 8009 int op1, op2; 8010 int32_t r1, r2, r3; 8011 int32_t address, const16; 8012 int8_t b, const4; 8013 int32_t bpos; 8014 TCGv temp, temp2, temp3; 8015 8016 op1 = MASK_OP_MAJOR(ctx->opcode); 8017 8018 /* handle JNZ.T opcode only being 7 bit long */ 8019 if (unlikely((op1 & 0x7f) == OPCM_32_BRN_JTT)) { 8020 op1 = OPCM_32_BRN_JTT; 8021 } 8022 8023 switch (op1) { 8024 /* ABS-format */ 8025 case OPCM_32_ABS_LDW: 8026 decode_abs_ldw(ctx); 8027 break; 8028 case OPCM_32_ABS_LDB: 8029 decode_abs_ldb(ctx); 8030 break; 8031 case OPCM_32_ABS_LDMST_SWAP: 8032 decode_abs_ldst_swap(ctx); 8033 break; 8034 case OPCM_32_ABS_LDST_CONTEXT: 8035 decode_abs_ldst_context(ctx); 8036 break; 8037 case OPCM_32_ABS_STORE: 8038 decode_abs_store(ctx); 8039 break; 8040 case OPCM_32_ABS_STOREB_H: 8041 decode_abs_storeb_h(ctx); 8042 break; 8043 case OPC1_32_ABS_STOREQ: 8044 address = MASK_OP_ABS_OFF18(ctx->opcode); 8045 r1 = MASK_OP_ABS_S1D(ctx->opcode); 8046 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 8047 temp2 = tcg_temp_new(); 8048 8049 tcg_gen_shri_tl(temp2, cpu_gpr_d[r1], 16); 8050 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_LEUW); 8051 break; 8052 case OPC1_32_ABS_LD_Q: 8053 address = MASK_OP_ABS_OFF18(ctx->opcode); 8054 r1 = MASK_OP_ABS_S1D(ctx->opcode); 8055 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 8056 8057 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); 8058 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 8059 break; 8060 case OPCM_32_ABS_LEA_LHA: 8061 address = MASK_OP_ABS_OFF18(ctx->opcode); 8062 r1 = MASK_OP_ABS_S1D(ctx->opcode); 8063 8064 if (has_feature(ctx, TRICORE_FEATURE_162)) { 8065 op2 = MASK_OP_ABS_OP2(ctx->opcode); 8066 if (op2 == OPC2_32_ABS_LHA) { 8067 tcg_gen_movi_tl(cpu_gpr_a[r1], address << 14); 8068 break; 8069 } 8070 /* otherwise translate regular LEA */ 8071 } 8072 8073 tcg_gen_movi_tl(cpu_gpr_a[r1], EA_ABS_FORMAT(address)); 8074 break; 8075 /* ABSB-format */ 8076 case OPC1_32_ABSB_ST_T: 8077 address = MASK_OP_ABS_OFF18(ctx->opcode); 8078 b = MASK_OP_ABSB_B(ctx->opcode); 8079 bpos = MASK_OP_ABSB_BPOS(ctx->opcode); 8080 8081 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 8082 temp2 = tcg_temp_new(); 8083 8084 tcg_gen_qemu_ld_tl(temp2, temp, ctx->mem_idx, MO_UB); 8085 tcg_gen_andi_tl(temp2, temp2, ~(0x1u << bpos)); 8086 tcg_gen_ori_tl(temp2, temp2, (b << bpos)); 8087 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_UB); 8088 break; 8089 /* B-format */ 8090 case OPC1_32_B_CALL: 8091 case OPC1_32_B_CALLA: 8092 case OPC1_32_B_FCALL: 8093 case OPC1_32_B_FCALLA: 8094 case OPC1_32_B_J: 8095 case OPC1_32_B_JA: 8096 case OPC1_32_B_JL: 8097 case OPC1_32_B_JLA: 8098 address = MASK_OP_B_DISP24_SEXT(ctx->opcode); 8099 gen_compute_branch(ctx, op1, 0, 0, 0, address); 8100 break; 8101 /* Bit-format */ 8102 case OPCM_32_BIT_ANDACC: 8103 decode_bit_andacc(ctx); 8104 break; 8105 case OPCM_32_BIT_LOGICAL_T1: 8106 decode_bit_logical_t(ctx); 8107 break; 8108 case OPCM_32_BIT_INSERT: 8109 decode_bit_insert(ctx); 8110 break; 8111 case OPCM_32_BIT_LOGICAL_T2: 8112 decode_bit_logical_t2(ctx); 8113 break; 8114 case OPCM_32_BIT_ORAND: 8115 decode_bit_orand(ctx); 8116 break; 8117 case OPCM_32_BIT_SH_LOGIC1: 8118 decode_bit_sh_logic1(ctx); 8119 break; 8120 case OPCM_32_BIT_SH_LOGIC2: 8121 decode_bit_sh_logic2(ctx); 8122 break; 8123 /* BO Format */ 8124 case OPCM_32_BO_ADDRMODE_POST_PRE_BASE: 8125 decode_bo_addrmode_post_pre_base(ctx); 8126 break; 8127 case OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR: 8128 decode_bo_addrmode_bitreverse_circular(ctx); 8129 break; 8130 case OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE: 8131 decode_bo_addrmode_ld_post_pre_base(ctx); 8132 break; 8133 case OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR: 8134 decode_bo_addrmode_ld_bitreverse_circular(ctx); 8135 break; 8136 case OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE: 8137 decode_bo_addrmode_stctx_post_pre_base(ctx); 8138 break; 8139 case OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR: 8140 decode_bo_addrmode_ldmst_bitreverse_circular(ctx); 8141 break; 8142 /* BOL-format */ 8143 case OPC1_32_BOL_LD_A_LONGOFF: 8144 case OPC1_32_BOL_LD_W_LONGOFF: 8145 case OPC1_32_BOL_LEA_LONGOFF: 8146 case OPC1_32_BOL_ST_W_LONGOFF: 8147 case OPC1_32_BOL_ST_A_LONGOFF: 8148 case OPC1_32_BOL_LD_B_LONGOFF: 8149 case OPC1_32_BOL_LD_BU_LONGOFF: 8150 case OPC1_32_BOL_LD_H_LONGOFF: 8151 case OPC1_32_BOL_LD_HU_LONGOFF: 8152 case OPC1_32_BOL_ST_B_LONGOFF: 8153 case OPC1_32_BOL_ST_H_LONGOFF: 8154 decode_bol_opc(ctx, op1); 8155 break; 8156 /* BRC Format */ 8157 case OPCM_32_BRC_EQ_NEQ: 8158 case OPCM_32_BRC_GE: 8159 case OPCM_32_BRC_JLT: 8160 case OPCM_32_BRC_JNE: 8161 const4 = MASK_OP_BRC_CONST4_SEXT(ctx->opcode); 8162 address = MASK_OP_BRC_DISP15_SEXT(ctx->opcode); 8163 r1 = MASK_OP_BRC_S1(ctx->opcode); 8164 gen_compute_branch(ctx, op1, r1, 0, const4, address); 8165 break; 8166 /* BRN Format */ 8167 case OPCM_32_BRN_JTT: 8168 address = MASK_OP_BRN_DISP15_SEXT(ctx->opcode); 8169 r1 = MASK_OP_BRN_S1(ctx->opcode); 8170 gen_compute_branch(ctx, op1, r1, 0, 0, address); 8171 break; 8172 /* BRR Format */ 8173 case OPCM_32_BRR_EQ_NEQ: 8174 case OPCM_32_BRR_ADDR_EQ_NEQ: 8175 case OPCM_32_BRR_GE: 8176 case OPCM_32_BRR_JLT: 8177 case OPCM_32_BRR_JNE: 8178 case OPCM_32_BRR_JNZ: 8179 case OPCM_32_BRR_LOOP: 8180 address = MASK_OP_BRR_DISP15_SEXT(ctx->opcode); 8181 r2 = MASK_OP_BRR_S2(ctx->opcode); 8182 r1 = MASK_OP_BRR_S1(ctx->opcode); 8183 gen_compute_branch(ctx, op1, r1, r2, 0, address); 8184 break; 8185 /* RC Format */ 8186 case OPCM_32_RC_LOGICAL_SHIFT: 8187 decode_rc_logical_shift(ctx); 8188 break; 8189 case OPCM_32_RC_ACCUMULATOR: 8190 decode_rc_accumulator(ctx); 8191 break; 8192 case OPCM_32_RC_SERVICEROUTINE: 8193 decode_rc_serviceroutine(ctx); 8194 break; 8195 case OPCM_32_RC_MUL: 8196 decode_rc_mul(ctx); 8197 break; 8198 /* RCPW Format */ 8199 case OPCM_32_RCPW_MASK_INSERT: 8200 decode_rcpw_insert(ctx); 8201 break; 8202 /* RCRR Format */ 8203 case OPC1_32_RCRR_INSERT: 8204 r1 = MASK_OP_RCRR_S1(ctx->opcode); 8205 r2 = MASK_OP_RCRR_S3(ctx->opcode); 8206 r3 = MASK_OP_RCRR_D(ctx->opcode); 8207 const16 = MASK_OP_RCRR_CONST4(ctx->opcode); 8208 temp = tcg_constant_i32(const16); 8209 temp2 = tcg_temp_new(); /* width*/ 8210 temp3 = tcg_temp_new(); /* pos */ 8211 8212 CHECK_REG_PAIR(r2); 8213 8214 tcg_gen_andi_tl(temp2, cpu_gpr_d[r2 + 1], 0x1f); 8215 tcg_gen_andi_tl(temp3, cpu_gpr_d[r2], 0x1f); 8216 8217 gen_insert(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, temp2, temp3); 8218 break; 8219 /* RCRW Format */ 8220 case OPCM_32_RCRW_MASK_INSERT: 8221 decode_rcrw_insert(ctx); 8222 break; 8223 /* RCR Format */ 8224 case OPCM_32_RCR_COND_SELECT: 8225 decode_rcr_cond_select(ctx); 8226 break; 8227 case OPCM_32_RCR_MADD: 8228 decode_rcr_madd(ctx); 8229 break; 8230 case OPCM_32_RCR_MSUB: 8231 decode_rcr_msub(ctx); 8232 break; 8233 /* RLC Format */ 8234 case OPC1_32_RLC_ADDI: 8235 case OPC1_32_RLC_ADDIH: 8236 case OPC1_32_RLC_ADDIH_A: 8237 case OPC1_32_RLC_MFCR: 8238 case OPC1_32_RLC_MOV: 8239 case OPC1_32_RLC_MOV_64: 8240 case OPC1_32_RLC_MOV_U: 8241 case OPC1_32_RLC_MOV_H: 8242 case OPC1_32_RLC_MOVH_A: 8243 case OPC1_32_RLC_MTCR: 8244 decode_rlc_opc(ctx, op1); 8245 break; 8246 /* RR Format */ 8247 case OPCM_32_RR_ACCUMULATOR: 8248 decode_rr_accumulator(ctx); 8249 break; 8250 case OPCM_32_RR_LOGICAL_SHIFT: 8251 decode_rr_logical_shift(ctx); 8252 break; 8253 case OPCM_32_RR_ADDRESS: 8254 decode_rr_address(ctx); 8255 break; 8256 case OPCM_32_RR_IDIRECT: 8257 decode_rr_idirect(ctx); 8258 break; 8259 case OPCM_32_RR_DIVIDE: 8260 decode_rr_divide(ctx); 8261 break; 8262 /* RR1 Format */ 8263 case OPCM_32_RR1_MUL: 8264 decode_rr1_mul(ctx); 8265 break; 8266 case OPCM_32_RR1_MULQ: 8267 decode_rr1_mulq(ctx); 8268 break; 8269 /* RR2 format */ 8270 case OPCM_32_RR2_MUL: 8271 decode_rr2_mul(ctx); 8272 break; 8273 /* RRPW format */ 8274 case OPCM_32_RRPW_EXTRACT_INSERT: 8275 decode_rrpw_extract_insert(ctx); 8276 break; 8277 case OPC1_32_RRPW_DEXTR: 8278 r1 = MASK_OP_RRPW_S1(ctx->opcode); 8279 r2 = MASK_OP_RRPW_S2(ctx->opcode); 8280 r3 = MASK_OP_RRPW_D(ctx->opcode); 8281 const16 = MASK_OP_RRPW_POS(ctx->opcode); 8282 8283 tcg_gen_extract2_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], cpu_gpr_d[r1], 8284 32 - const16); 8285 break; 8286 /* RRR Format */ 8287 case OPCM_32_RRR_COND_SELECT: 8288 decode_rrr_cond_select(ctx); 8289 break; 8290 case OPCM_32_RRR_DIVIDE: 8291 decode_rrr_divide(ctx); 8292 break; 8293 /* RRR2 Format */ 8294 case OPCM_32_RRR2_MADD: 8295 decode_rrr2_madd(ctx); 8296 break; 8297 case OPCM_32_RRR2_MSUB: 8298 decode_rrr2_msub(ctx); 8299 break; 8300 /* RRR1 format */ 8301 case OPCM_32_RRR1_MADD: 8302 decode_rrr1_madd(ctx); 8303 break; 8304 case OPCM_32_RRR1_MADDQ_H: 8305 decode_rrr1_maddq_h(ctx); 8306 break; 8307 case OPCM_32_RRR1_MADDSU_H: 8308 decode_rrr1_maddsu_h(ctx); 8309 break; 8310 case OPCM_32_RRR1_MSUB_H: 8311 decode_rrr1_msub(ctx); 8312 break; 8313 case OPCM_32_RRR1_MSUB_Q: 8314 decode_rrr1_msubq_h(ctx); 8315 break; 8316 case OPCM_32_RRR1_MSUBAD_H: 8317 decode_rrr1_msubad_h(ctx); 8318 break; 8319 /* RRRR format */ 8320 case OPCM_32_RRRR_EXTRACT_INSERT: 8321 decode_rrrr_extract_insert(ctx); 8322 break; 8323 /* RRRW format */ 8324 case OPCM_32_RRRW_EXTRACT_INSERT: 8325 decode_rrrw_extract_insert(ctx); 8326 break; 8327 /* SYS format */ 8328 case OPCM_32_SYS_INTERRUPTS: 8329 decode_sys_interrupts(ctx); 8330 break; 8331 case OPC1_32_SYS_RSTV: 8332 tcg_gen_movi_tl(cpu_PSW_V, 0); 8333 tcg_gen_mov_tl(cpu_PSW_SV, cpu_PSW_V); 8334 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 8335 tcg_gen_mov_tl(cpu_PSW_SAV, cpu_PSW_V); 8336 break; 8337 default: 8338 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 8339 } 8340 } 8341 8342 static bool tricore_insn_is_16bit(uint32_t insn) 8343 { 8344 return (insn & 0x1) == 0; 8345 } 8346 8347 static void tricore_tr_init_disas_context(DisasContextBase *dcbase, 8348 CPUState *cs) 8349 { 8350 DisasContext *ctx = container_of(dcbase, DisasContext, base); 8351 CPUTriCoreState *env = cpu_env(cs); 8352 ctx->mem_idx = cpu_mmu_index(cs, false); 8353 8354 uint32_t tb_flags = (uint32_t)ctx->base.tb->flags; 8355 ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV); 8356 8357 ctx->features = env->features; 8358 if (has_feature(ctx, TRICORE_FEATURE_161)) { 8359 ctx->icr_ie_mask = R_ICR_IE_161_MASK; 8360 ctx->icr_ie_offset = R_ICR_IE_161_SHIFT; 8361 } else { 8362 ctx->icr_ie_mask = R_ICR_IE_13_MASK; 8363 ctx->icr_ie_offset = R_ICR_IE_13_SHIFT; 8364 } 8365 } 8366 8367 static void tricore_tr_tb_start(DisasContextBase *db, CPUState *cpu) 8368 { 8369 } 8370 8371 static void tricore_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 8372 { 8373 DisasContext *ctx = container_of(dcbase, DisasContext, base); 8374 8375 tcg_gen_insn_start(ctx->base.pc_next); 8376 } 8377 8378 static bool insn_crosses_page(CPUTriCoreState *env, DisasContext *ctx) 8379 { 8380 /* 8381 * Return true if the insn at ctx->base.pc_next might cross a page boundary. 8382 * (False positives are OK, false negatives are not.) 8383 * Our caller ensures we are only called if dc->base.pc_next is less than 8384 * 4 bytes from the page boundary, so we cross the page if the first 8385 * 16 bits indicate that this is a 32 bit insn. 8386 */ 8387 uint16_t insn = translator_lduw(env, &ctx->base, ctx->base.pc_next); 8388 8389 return !tricore_insn_is_16bit(insn); 8390 } 8391 8392 8393 static void tricore_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 8394 { 8395 DisasContext *ctx = container_of(dcbase, DisasContext, base); 8396 CPUTriCoreState *env = cpu_env(cpu); 8397 uint16_t insn_lo; 8398 bool is_16bit; 8399 8400 insn_lo = translator_lduw(env, &ctx->base, ctx->base.pc_next); 8401 is_16bit = tricore_insn_is_16bit(insn_lo); 8402 if (is_16bit) { 8403 ctx->opcode = insn_lo; 8404 ctx->pc_succ_insn = ctx->base.pc_next + 2; 8405 decode_16Bit_opc(ctx); 8406 } else { 8407 uint32_t insn_hi = translator_lduw(env, &ctx->base, 8408 ctx->base.pc_next + 2); 8409 ctx->opcode = insn_hi << 16 | insn_lo; 8410 ctx->pc_succ_insn = ctx->base.pc_next + 4; 8411 decode_32Bit_opc(ctx); 8412 } 8413 ctx->base.pc_next = ctx->pc_succ_insn; 8414 8415 if (ctx->base.is_jmp == DISAS_NEXT) { 8416 target_ulong page_start; 8417 8418 page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 8419 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE 8420 || (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE - 3 8421 && insn_crosses_page(env, ctx))) { 8422 ctx->base.is_jmp = DISAS_TOO_MANY; 8423 } 8424 } 8425 } 8426 8427 static void tricore_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 8428 { 8429 DisasContext *ctx = container_of(dcbase, DisasContext, base); 8430 8431 switch (ctx->base.is_jmp) { 8432 case DISAS_TOO_MANY: 8433 gen_goto_tb(ctx, 0, ctx->base.pc_next); 8434 break; 8435 case DISAS_EXIT_UPDATE: 8436 gen_save_pc(ctx->base.pc_next); 8437 /* fall through */ 8438 case DISAS_EXIT: 8439 tcg_gen_exit_tb(NULL, 0); 8440 break; 8441 case DISAS_JUMP: 8442 tcg_gen_lookup_and_goto_ptr(); 8443 break; 8444 case DISAS_NORETURN: 8445 break; 8446 default: 8447 g_assert_not_reached(); 8448 } 8449 } 8450 8451 static const TranslatorOps tricore_tr_ops = { 8452 .init_disas_context = tricore_tr_init_disas_context, 8453 .tb_start = tricore_tr_tb_start, 8454 .insn_start = tricore_tr_insn_start, 8455 .translate_insn = tricore_tr_translate_insn, 8456 .tb_stop = tricore_tr_tb_stop, 8457 }; 8458 8459 void tricore_translate_code(CPUState *cs, TranslationBlock *tb, 8460 int *max_insns, vaddr pc, void *host_pc) 8461 { 8462 DisasContext ctx; 8463 translator_loop(cs, tb, max_insns, pc, host_pc, 8464 &tricore_tr_ops, &ctx.base); 8465 } 8466 8467 /* 8468 * 8469 * Initialization 8470 * 8471 */ 8472 8473 void cpu_state_reset(CPUTriCoreState *env) 8474 { 8475 /* Reset Regs to Default Value */ 8476 env->PSW = 0xb80; 8477 fpu_set_state(env); 8478 } 8479 8480 static void tricore_tcg_init_csfr(void) 8481 { 8482 cpu_PCXI = tcg_global_mem_new(tcg_env, 8483 offsetof(CPUTriCoreState, PCXI), "PCXI"); 8484 cpu_PSW = tcg_global_mem_new(tcg_env, 8485 offsetof(CPUTriCoreState, PSW), "PSW"); 8486 cpu_PC = tcg_global_mem_new(tcg_env, 8487 offsetof(CPUTriCoreState, PC), "PC"); 8488 cpu_ICR = tcg_global_mem_new(tcg_env, 8489 offsetof(CPUTriCoreState, ICR), "ICR"); 8490 } 8491 8492 void tricore_tcg_init(void) 8493 { 8494 int i; 8495 8496 /* reg init */ 8497 for (i = 0 ; i < 16 ; i++) { 8498 cpu_gpr_a[i] = tcg_global_mem_new(tcg_env, 8499 offsetof(CPUTriCoreState, gpr_a[i]), 8500 regnames_a[i]); 8501 } 8502 for (i = 0 ; i < 16 ; i++) { 8503 cpu_gpr_d[i] = tcg_global_mem_new(tcg_env, 8504 offsetof(CPUTriCoreState, gpr_d[i]), 8505 regnames_d[i]); 8506 } 8507 tricore_tcg_init_csfr(); 8508 /* init PSW flag cache */ 8509 cpu_PSW_C = tcg_global_mem_new(tcg_env, 8510 offsetof(CPUTriCoreState, PSW_USB_C), 8511 "PSW_C"); 8512 cpu_PSW_V = tcg_global_mem_new(tcg_env, 8513 offsetof(CPUTriCoreState, PSW_USB_V), 8514 "PSW_V"); 8515 cpu_PSW_SV = tcg_global_mem_new(tcg_env, 8516 offsetof(CPUTriCoreState, PSW_USB_SV), 8517 "PSW_SV"); 8518 cpu_PSW_AV = tcg_global_mem_new(tcg_env, 8519 offsetof(CPUTriCoreState, PSW_USB_AV), 8520 "PSW_AV"); 8521 cpu_PSW_SAV = tcg_global_mem_new(tcg_env, 8522 offsetof(CPUTriCoreState, PSW_USB_SAV), 8523 "PSW_SAV"); 8524 } 8525